High breakdown voltage normally off Ga₂O₃ transistors on silicon substrates using GaN buffer Open Access

Beta gallium oxide (β-Ga₂O₃) has emerged as a leading ultra-wide bandgap (UWBG) semiconductor material with a bandgap of approximately 4.9 eV,¹ significantly higher than other WBG materials such as silicon carbide (SiC) and gallium nitride (GaN).^2,3 This large bandgap allows Ga₂O₃ to sustain a critical breakdown field of up to ∼8 MV cm⁻¹, enabling its use in applications that require high-voltage and high-power capabilities.⁴ Furthermore, Ga₂O₃ exhibits a high Baliga's figure of merit,⁵ which is a key indicator of power semiconductor performance. These properties make Ga₂O₃ a promising candidate for a wide range of high-power and high-frequency applications, including power electronics, radio frequency (RF) devices, and solar-blind ultraviolet photodetectors.^6–9 Despite its advantages, several challenges hinder the widespread use of Ga₂O₃ in commercial applications. These include its intrinsically low thermal conductivity,¹⁰ which limits the device's ability to manage heat during high-power operation, and the difficulty of achieving efficient p-type doping,^11,12 which is essential for fabricating complementary devices like bipolar junction transistors.

To address these material limitations, heterogeneous integration of Ga₂O₃ with substrates such as silicon (Si), GaN, SiC, and diamond has become an important strategy.^13–17 Heterogeneous substrates are crucial for enabling large-scale manufacturing, improving device performance, and overcoming thermal management issues. This integration can significantly enhance thermal conductivity by leveraging the properties of the underlying substrate while maintaining the high-performance characteristics of Ga₂O₃. Various methods have been proposed for fabricating Ga₂O₃ devices on foreign substrates, including techniques like wafer bonding,¹⁸ layer transfer,^13,19 and direct epitaxy growth such as pulsed laser deposition (PLD),²⁰ molecular beam epitaxy (MBE),^21–23 and metalorganic chemical vapor deposition (MOCVD).²⁴ Xu et al. reported the heterogeneous integration of Ga₂O₃ metal-oxide field-effect transistors (MOSFETs) on SiC and Si substrates through a method based on ion-cut technology.²⁵ 

Although Ga₂O₃-on-SiC substrates offer the advantage of high thermal conductivity, they are expensive and not compatible with Si process technology for monolithic integration with different material systems. In contrast, Ga₂O₃-on-GaN buffer layers on Si substrates offer a more scalable, cost-effective solution without compromising performance. GaN serves as an excellent buffer layer due to its high thermal conductivity and wide bandgap, making it an ideal material to support Ga₂O₃-based devices while enabling the integration of Ga₂O₃ with Si substrates. This integration allows for the development of high-performance Ga₂O₃-based metal-oxide-semiconductor field-effect transistors (MOSFETs) that can be efficiently scaled for commercial use in power electronics and RF systems. Given Ga₂O₃’s higher breakdown voltage compared to GaN, it complements GaN's superior mobility. This allows high-speed control circuitry to be implemented with GaN technology, while high-power devices are realized using Ga₂O₃, leveraging both technologies to develop monolithic power-integrated circuits (ICs). This work showcases the feasibility of monolithically integrating Ga₂O₃ with GaN-based devices, paving the way for next-generation high-power and high-efficiency electronics.

Herein, we demonstrated the fabrication of enhancement-mode (E-mode) Ga₂O₃ MOSFETs on GaN buffer layers integrated onto silicon substrates. The devices exhibit a breakdown voltage of ∼540 V at V_GS = 0 V, which is the highest reported for β-Ga2O3 MOSFETs on Si substrates. The threshold voltage (V_TH) is measured at 3 V, and the low subthreshold swing (SS) is 167 mV/dec with gate leakage current of ∼10⁻⁷mA/mm, which is comparable to or better than previously reported values for similar devices.^20,26–29 These characteristics make the devices well-suited for high-power applications, such as power switching and RF amplification, where high-voltage handling and low losses are crucial.

The epitaxial information of the wafer is shown in Fig. 1(a). A ∼50 nm Si-doped β-Ga₂O₃ film was grown on semi-insulating 4.7-μm thick GaN buffer with a carbon doping concentration of 5  $×$ 10¹⁹ cm⁻³ on p-Si (111) substrates. The laser ablation frequency was maintained at 5 Hz, the oxygen partial pressure at 5 mTorr, and the laser energy at 102 mJ throughout the growth process. The Hall measurement shows the electron concentration and bulk mobility of the β-Ga₂O₃ were ∼1.2  $×$ 10¹⁸ cm⁻³ and ∼2.06 cm² V⁻¹ s⁻¹, respectively. The relatively low bulk mobility of the epitaxial Ga₂O₃ film is primarily due to its polycrystalline nature, and lattice mismatch-induced defects from growth on GaN/Si substrates.²⁴ Mobility can be improved by adopting advanced growth techniques such as MOCVD and applying post-growth high-temperature annealing to enhance crystallinity and reduce defect densities.³⁰  Figure 1(b) shows the XRD pattern of the β-Ga₂O₃ film grown on GaN buffer-on-Si substrates. The XRD peaks at (⁠ $−$201), (⁠ $−$402), and (⁠ $−$603) confirm the mono-orientation of the polycrystalline β-Ga₂O₃ film grown on heterogeneous GaN buffer-on-Si substrates.²⁰ The atomic force microscopy (AFM) measurement was done before and after the growth of the β-Ga₂O₃ film. The root mean square (RMS) surface roughness of the GaN buffer before the growth of β-Ga₂O₃ film was ∼0.23 nm for a scanning area of 5  $×$ 5 μm² as depicted in Fig. 1(c). Furthermore, a slight increase in the RMS surface roughness was observed after the growth of the β-Ga₂O₃ film, measured at ∼0.57 nm for a scanning area of 5  $×$ 5 μm² as shown in Fig. 1(d).

A 3D schematic, fabrication process, and scanning electron microscopy (SEM) of fabricated β-Ga₂O₃ thin film transistors (TFTs) on GaN-on-Si substrates is shown in Fig. 2. The fabrication begins with the wafer cleaning for 5 min in HF solution, followed by the growth of a ∼50 nm Si-doped β-Ga₂O₃ layer on GaN buffer using PLD at 700 °C. The source (S) and drain (D) Ohmic terminals using Ti/Au (20/150 nm) were formed. A ∼25-nm Al₂O₃ gate dielectric was deposited by atomic layer deposition (ALD) at 250 °C, followed by gate metal deposition of Ti/Au (20/100 nm). Finally, the S- and D-pads were opened by inductively coupled plasma reactive ion etching (ICP-RIE) of Al₂O₃ dielectric for probe contacts. A gate length (L_g) of 4 μm, source-to-gate (L_SG) distance of 3 μm, and gate to-drain (L_GD) distance of 18 μm were considered for device fabrication.

The fabricated device performance was characterized using a Keysight B1505A power device analyzer. An initial test of the metal–semiconductor interface was performed to achieve the effective operation of β-Ga₂O₃ TFTs. Contact resistance (R_C) and transfer length (L_T) were measured using a transfer length method (TLM). The test structure had 150  $×$ 150 μm² square contact with spacing between two contacts varying from 5 to 30 μm. Figure 3(a) shows the current–voltage (I–V) characteristics of the TLM structure on a linear scale, showing the Ohmic behavior of the contacts. The current decreased with increasing spacing between the two contacts as the on resistance (R_on) of the channel increased. Figure 3(b) displays the resistance vs different spacing between the contacts plot, yielding R_C of ∼0.69 kΩ  $·$ mm and L_T of ∼0.75 μm. The R_C can be further improved by incorporating a high-doped β-Ga₂O₃ layer for the contact formation. To ease the fabrication process, we have formed the contact directly on the moderately doped β-Ga₂O₃ channel.

Figure 4 shows the I–V characteristics of E-mode β-Ga₂O₃ transistors fabricated on heterogeneous substrates (GaN-on-Si). The logarithmic transfer characteristic (I_DS–V_DS) at different drain-to-source voltage (V_DS) from 1 to 5 V with a step size of 1 V is illustrated in Fig. 4(a). The low SS and high current on/off ratios (I_on/I_off) of ∼167 mV/dec and ∼10⁶ were calculated, respectively. The off-state gate leakage current (I_{GS, off}) of ∼10⁻⁷mA/mm was obtained for the forward gate-to-source voltage (V_GS) of 8 V. The low I_{GS, off} was realized due to Al₂O₃ gate dielectric based on metal-oxide-semiconductor (MOS) structure. The V_TH of the fabricated E-mode β-Ga₂O₃ MOSFETs was calculated by linear extrapolation of the I_DS–V_GS curve at the maximum point of transconductance (⁠ $gm$⁠) [Fig. 4(b)]. A positive V_TH of 3 V was obtained at V_DS = 5 V, showing advantages for fail-safe operation of power systems. The positive V_TH of β-Ga₂O₃ MOSFETs is contributed by both the top-side and bottom-side depletion, along with possible phase-induced insulating regions near the β-Ga₂O₃/GaN interface.²⁰ V_TH of the fabricated device was controlled using the thickness of the β-Ga₂O₃ channel.

To provide a clearer perspective and comparison of device performance, Table I highlights the fundamental characteristics of β-Ga₂O₃ MOSFETs on heterogeneous substrates utilizing various growth techniques. Reported research to date indicates that β-Ga₂O₃ FET devices utilizing SiC substrates have demonstrated enhanced performance through different growth techniques. Nonetheless, despite advancements in β-Ga₂O₃ thin film growth technology via various growth methods on heterogeneous substrates, there is no demonstration of β-Ga₂O₃ power MOSFETs utilizing GaN buffer-on-Si substrates. Therefore, we assert that this study will initiate a new phase in the investigation of β-Ga₂O₃ MOSFETs on GaN buffer-on-Si substrates, utilizing the platform for integration with the GaN-based high-performance power and RF devices. The device demonstrated in this study, using PLD growth, exhibited the highest breakdown compared to β-Ga₂O₃ MOSFETs on Si substrates. The development of β-Ga₂O₃ thin films on GaN-on-Si substrates via PLD not only indicates enhanced device performance but also provides a path for further improvement in the quality of the epitaxy on GaN and heterogeneous integration at the circuity level for future power ICs.

In summary, we have effectively exhibited E-mode β-Ga₂O₃ MOSFETs on GaN buffer layers on Si substrates using PLD growth. The β-Ga₂O₃ MOSFETs have a threshold voltage of 3 V with a high breakdown voltage of ∼540 V at V_GS = 0 V. The devices also showed a low subthreshold swing of ∼167 mV/dec with a low gate leakage current of ∼10⁻⁷mA/mm in the forward bias operation of the transistors. These results highlight the significant potential of β-Ga₂O₃ MOSFETs for high-performance applications, demonstrating that economical and scalable PLD growth of β-Ga₂O₃ thin films on low-cost, commercially available GaN-on-Si substrates can be a promising route for the integration of GaN-based devices in future power and RF electronics.

The authors are grateful for the support of KAUST Nanofabrication Core Lab and funding support of the Baseline Fund BAS/1/1664-01-01.