Gate-controlled near-surface Josephson junctions Open Access

The increasing interest in quantum computation has put efforts toward the realization of hybrid superconductor–semiconductor devices with highly transparent interfaces.^1–4 The potential application in emerging quantum technologies spans from superconducting quantum computation^5,6 to electrically tuned parametric amplifiers.^7,8 To fully understand and optimize advanced circuits containing hybrid devices, a compact device model is required, that is, a mathematical description of the system using parametric equations. In the literature, there are several works on implementations of compact models for superconductor/insulator/superconductor-based Josephson junctions (JJs)^9–11 and gate-tunable superconductor/semiconductor/superconductor junctions.^12–14 However, there is lack of work that combines processing, measurements, and modeling to facilitate circuit simulations of actual quasi-ballistic non-ideal hybrid devices, which is essential for system-level integration.

We investigate the superconducting properties of a near-surface Al–InGaAs–Al Josephson field-effect transistor (JoFET). The channel is located directly at the surface, allowing for fabrication of short-gate length devices with high gate control. In addition, we use a thinner gate oxide compared to similar works,^15,16 which increases the electrostatic control even further. Such geometry is needed for very short gate length scaling, similar to that of high-performance field-effect transistors.

To facilitate circuit simulations of our device, we developed a compact model, which considers the gate tunability of the semiconductor, the carrier density-dependent mobility and transmission coefficient, semiconductor band tails, non-ideal interfaces, and nonlinear excess resistances, allowing for circuit modeling with more realistic JoFETs.

InGaAs JoFETs were fabricated on a wafer with a layer stack according to Table I, where the 2DEG consists of layers 4, 5, and 6. The epitaxial layer stack is designed for maximum electron carrier concentration in the high indium part of the composite channel, layer 5.

The devices were electrically isolated by resist masking using direct laser writing (DLW), followed by a mesa wet etch into layer 1 using H₃PO₄:H₂O₂:H₂O (1:1:25). Next, source and drain contacts (Ti/Al, 5/40 nm) were defined by electron beam lithography (EBL) followed by e-beam evaporation and liftoff. Titanium is known for its rapid reaction with oxygen and its oxygen-scavenging effects.^17,18 The thin Ti layer in our device serves the purpose of decreasing the amount of free oxygen in the air in the evaporator chamber. This is achieved by formation of titanium oxides, thereby minimizing the formation of insulating low-k Al₂O₃ at the semiconductor–superconductor interface. Just before evaporation, the native oxide on InGaAs was removed in HCl:H₂O (1:20). Next, the gate oxide was deposited by ALD (Al₂O₃/HfO_2, 1/10 nm, 300 °C/120 °C), followed by deposition of the gate contact (Ti/Pd/Au, 5/5/200 nm) by e-beam evaporation and liftoff. The ALD process involves pre-pulsing of trimethylaluminum to restore surface As atoms to a bulk-like bonding configuration and reduce the density of interface traps.¹⁹ Subsequently, the bilayer of Al₂O₃ and HfO₂ is deposited, resulting in a high-quality interface with a low equivalent oxide thickness. The device characterized in this work has a device width of $W=4$μm and a gate length of $L g=210$ nm. A schematic of the device and fabrication steps are shown in Fig. 1.

The devices were characterized at cryogenic temperatures in a Triton dilution refrigerator from Oxford Instruments, with a base chamber temperature at 15 mK. Current-driven measurements were performed as four-point measurements, where the voltage drop was measured over the inner contacts. An alternative device geometry, featuring a T-gate to minimize parasitic capacitances or a junction involving superconductor, semiconductor, and normal conductor, would have facilitated a more in-depth exploration of RF-performance and the induced superconducting gap. A magnetic field evaluation of the induced supercurrent is presented in the supplementary material. However, the primary aim of our device was to validate our DC circuit simulations. Therefore, the simpler device design was adopted. The carrier mobility was extracted by Hall measurements in a closed cycle helium refrigerator at 9 K, with an applied magnetic field from −1 T to 1 T perpendicular to the sample surface.

We implemented a Verilog-A code to model the behavior of our device in Advanced Design System (ADS). A circuit schematic of the system used is shown in Fig. 2(a). A voltage source, $V drive$⁠, in series with a 20 MΩ resistor is used to simulate current-driven measurement similar to the real experiments. $R g$ and $V g$ represents the gate finger resistance and the applied gate voltage, respectively. Two parasitic capacitances, $C p 2$⁠, are included due to an overlap between the gate contact and the source–drain contacts. The part of the circuit within the dashed line in Fig. 2(a) is implemented in a Verilog-A code, where JJ represents the Josephson junction. The full device is characterized by contact resistance, $R c$⁠, normal channel resistance, $R c h$⁠, a nonlinear excess resistance, $R e x$⁠, and total intrinsic gate capacitance, $C gg$⁠. $C gg$ is obtained from reference C–V measurements,²⁰ including the influences of centroid capacitance and quantum capacitance based on the effective mass obtained through k·p modeling.²¹  $C p$ is determined from the overlap area between the gate electrode and source–drain electrodes, using the relative permittivity of the gate oxide,²⁰ and assuming a parallel plate capacitor. Their corresponding values are $C g g=5.58$ fF and $C p=160$ fF, and thus $C g g≪ C p$⁠.

The device shows good electrostatic control, with a normal current subthreshold swing of $SS ∼130$ mV/decade at 15 mK and $V d s=50$ mV. Even lower swings can be achieved by sulfur passivation,^20,21,31 which however is not directly compatible with the gate-last process utilized here. From Hall effect measurements, $μ n ∼7700$ cm²/V s and $n s ∼4× 10 12$ cm⁻² were extracted at 9 K and $V g s=0 V$⁠, which correspond to a mean free path $λ ∼400$ nm $> L g$⁠, indicating that the device is operating close to the ballistic limit for $V g s≫ V T$⁠. For lower carrier concentrations, we expect the mobility to decrease due to remote coulomb scattering,³² and we have observed from reference samples that $μ n∝ n s 2.1$ for low $n s$⁠. The crossover from diffusive to ballistic regime is important to consider for devices operating close to $V T$⁠, which will influence both the normal resistance and the critical current. Relating $λ$ to the coherence length, $ξ 0$⁠, using Eq. (S1) in the supplementary material, gives $λ≪ ξ 0 ∼$ 4000 nm, and the device is thus in the ballistic dirty limit.¹⁵ This gives a dirty coherence length, $ξ 0 , d= ξ 0 λ ∼>1300$ nm, close to the coherence length of Al.³³ 

In Fig. 3(a), the gate and temperature dependence of $I c$ is presented, showing a good electrostatic control of $I c$⁠, and a decrease in $I c$ with increasing temperature, related to a decreased induced superconducting gap. At 700 mK, the V–I plateaus have disappeared, and $I c$ is not possible to extract anymore. We, therefore, conclude that $T c≈700$ mK. The noise in Fig. 3(a) at 700 mK is only related to uncertainty in the low current $I c$ extraction.

In Fig. 3(b), the standard figure of merit for hybrid JJs, $R N$ times $I c$⁠, is plotted vs $V g s$⁠. The measured and simulated data from circuit simulations shows excellent agreement. The inset shows $I c$ and $R N$ plotted vs $V g s$⁠, showing a strong initial increase in $I c$ above $V T$ and then a more gradual increase, deviating somewhat from the ideal $I c∝ V g s − V T$ behavior, see Eqs. (5)–(7). The strong increase close to $V T$ is related to an increase in the mean free path due to the increased mobility, with a gentler increase for larger gate overdrives as the mobility is more constant. At large positive $V g s$⁠, when $R c h$ is negligible, $R N$ is approximately equal to $2 R c ∼1100$ Ω. In the compact modeling, $R c=550$ Ω was used. In Fig. 3(c), the normalized product of $I e x$ times $R N$ is plotted vs $V g s$⁠. The Andreev reflection across the junction gives rise to an excess current, $I e x=I− V J J R N$⁠, which can be found from the V–I curves, three of which are shown in the inset, by extrapolation back to the $V J J=0$ axis.³⁴ The product $I e x R N$ shows no clear gate voltage dependence, which indicates that $I e x R N$ is not affected by the change in carrier concentration in the 2DEG, but rather depends on the interface transparency Z of the superconductor–semiconductor interface.¹⁵ It is clear that $I e x<0$⁠, which indicates that the current gain due to the Andreev reflection is smaller than the current loss due to the normal reflection process. Therefore, the excess current observed in this device is rather a deficit current,³⁵ suggesting a $Z>1.2.$³⁰ The presence of the interface barriers implies a small Andreev reflection coefficient, meaning few carriers that penetrate from the 2DEG into the superconductor, effectively producing a deficit current.³⁶ This is in line with transmission line measurements on reference samples, showing a specific contact resistance between Al and the InGaAs stack, $R c≈ 10 4$ Ω μm, as compared with optimized ohmic contact technology yielding $R c< 10 3$ Ω μm.

In Figs. 3(b) and 3(c), the data obtained from circuit simulations using our compact model of the JoFET are indicated in black and show excellent agreement with the measured data. The gate-dependent fitting parameters used in the compact model of the JoFET are presented in Fig. 3(d) as a function of $V g s$⁠. The data points correspond to exact fittings to the measured data, while the gate dependence used in the final model is obtained by fitting exponentials to these data points. $R 0$ resembles $R N$ but does not increase as quickly at low $V g s$⁠. The effective transparency, $D n$⁠, follows approximately the mobility. First, a strong increase is shown close to $V T$⁠, with a maximum transmission of 3.5%, then a decrease due to the limited transparency of the Al-InGaAs contacts is observed. There is an uncertainty in $D n$⁠, which is related to the fitting value used for $V T$⁠. If $V T$ is overestimated, less modes will be conducting and $D n$ will need to be larger in order to give the same current. In the compact model, $V T$ is set to −1.5 V, and $η$ is set to 0.46.

We have fabricated and characterized a near-surface JoFET at cryogenic temperatures. Our device shows good tunability of the supercurrent and a high channel mobility of 7700 cm²/V s at 9 K. To investigate the potential of JoFETs in future gate-tunable qubit systems, we developed a Verilog-A-based compact model of the near-surface JoFET. Circuit simulations in ADS using our compact model show excellent agreement with the measured data at cryogenic temperatures. Especially, when operating close to $V T$⁠, we find that the device shows a crossover from diffusive to ballistic regime, which must be considered for device concepts operating close to $V T$⁠. Our model enables system-level investigation of circuits containing realistic, non-ideal JoFETs, which is essential for the development of gate-tunable qubits.

See the supplementary material for magnetic field evaluation of the induced supercurrent as well as an explanation of the expression for the critical current.

This work was supported in part by NanoLund and in part by the Swedish Research Council under Grant No. 2016-00891.

The authors have no conflicts to disclose.

L. Olausson and P. Olausson contributed equally to this work.

L. Olausson: Conceptualization (equal); Investigation (equal); Methodology (equal); Writing – original draft (equal); Writing – review & editing (equal). P. Olausson: Conceptualization (equal); Investigation (equal); Methodology (equal); Writing – original draft (equal); Writing – review & editing (equal). E. Lind: Conceptualization (equal); Funding acquisition (lead); Methodology (equal); Supervision (lead); Writing – review & editing (supporting).

The data that support the findings of this study are openly available in Zenodo at assigning-authority:zenodohttps://doi.org/10.5281/zenodo.10401032, Ref. 37.