This study characterizes low-resistance regions in a locally degraded multilayered ceramic capacitor (MLCC) using scanning spreading resistivity microscopy, scanning electron microscopy, and transmission electron microscopy. The MLCC consists of a core–shell structure that degrades before electrical breakdown in highly accelerated lifetime tests. Areas of local insulation degradation in the MLCC are revealed by Dy-containing solid solution grains. The characteristic grains within the low-resistance region show the resistance distribution. Degraded grains around the anode, which are assumed to strongly reflect the front-line insulation degradation, suggest that the shell and grain boundaries strongly repress insulation degradation. These results show that improved material uniformity and microstructure design are vital for achieving highly reliable MLCCs.

Recently, Ni-BaTiO3-based multilayer ceramic capacitors (MLCCs) have seen use in numerous electronic devices due to their superior performance and cost.1 MLCCs fired in a H2 and N2 atmosphere not only prevent oxidation of the Ni inner electrode but also reduce the dielectric material. Therefore, the insulation resistance has been improved and characterized to satisfy market requirements. Reliability is one of the key characteristics and is defined as the time from the onset of measuring insulation resistance to the time of failure while continuously applying a DC voltage in a high-temperature environment. The highly accelerated lifetime test (HALT) is another effective evaluation method. Generally, the MLCC lifetime is determined by the mean time to failure, which is derived from Weibull plots created by testing multiple MLCCs. Strategies to improve reliability include dielectric material composition,2–9 microstructural design,10–12 and grain-size control.13–15 Significant advances in understanding these materials have also been made via evaluation16–30 and computational techniques.31–34 These findings show that oxygen vacancies degrade the insulation in these materials.16–21 Given that the above approaches increase the “average” lifetime of dielectric materials, these findings are widely applied in current MLCC products.

Companies must also work on improving the quality of their products. Given that the lifetime of MLCCs may vary from one device to another, even within the same lot, the insulation degradation may also vary between devices. Thus, a proper understanding of the mechanism of this degradation is essential. Toward this end, our group has been working on sample preparation and evaluation techniques to clarify the causes of degradation.35–40 MLCCs whose resistance has been lowered by HALT to pre-breakdown levels have been processed to identify and evaluate the degraded areas, and the results show that the degradation of MLCC insulation advances significantly in regions a few micrometers in size localized near the semiconductor contacts.37,39 In addition, a non-uniform region, which is directly related to the lifetime, was identified and the local resistance distribution was imaged.38 Other useful findings were also obtained, such as the heat-generation characteristics39 of localized degraded areas and the correlation between the number of grain boundaries and the lifetime.40 These findings indicate that the weakest link model describes how the insulation degrades, so the factors that significantly affect the lifetime of each MLCC are rate-limiting to the degree of inhomogeneity. A detailed evaluation of the localized degraded areas is essential to thoroughly understand insulation degradation in ceramic materials.

This report presents a case study in which inhomogeneity in grain size and grain design is a factor in the localized degradation of MLCC insulation. A series of investigations show that the grain shells and grain boundaries play a major role in hindering insulation degradation. The results support previous suggestions regarding the role of material microstructure in reliability. These findings show that improved uniformity and microstructure design are vital for improving reliability.

Prototype MLCCs consisting of a Ni inner electrode and BaTiO3 dielectric material were fabricated by a general method that does not intentionally include any improvement in the raw process. The MLCC studies involved a 1206 EIA type with a capacitance of 4.7 μF and a rated voltage of 50 V. The MLCC was degraded under HALT conditions of 170 °C and 90 V. The rate of change in leakage current was set at the threshold for insulation degradation, and the MLCC was made low resistant until pre-breakdown (i.e., just before breakdown) by forcibly shutting off the external voltage. The MLCC was selected from the wear-out failure region of its Weibull plot. The lifetime extends from the application of the HALT voltage to the threshold (∼267 h). The MLCC pre-breakdown insulation resistance was measured at room temperature at 10 V DC for 60 s and was 3.1 (12.9) MΩ when 10 V were applied in the same (opposite) direction as HALT. After removing the terminal electrode and identifying the insulation degradation layer by dissolving Ni using an electrochemical technique, the MLCC was exfoliated using a microprobe so that the low-resistance layer remained. The degradation point was detected by infrared optical-beam-induced resistance change (IR-OBIRCH; Hamamatsu Photonics, THEMOS-1000). Subsequent processing is shown in the flow chart of Fig. 1. After processing with a focused ion beam device to a few μm before the center of the signal, the sample was mechanochemically prepared by a previously reported procedure,38 and the resistance distribution at the localized degradation area was monitored with a scanning spreading resistivity microscope (SSRM; Hitachi, AFM 5000 II).

FIG. 1.

Flow chart for evaluating locally degraded multilayered ceramic capacitor.

FIG. 1.

Flow chart for evaluating locally degraded multilayered ceramic capacitor.

Close modal

Next, the same surface was imaged using a scanning electron microscope's backscattered electron (BSE) mode and then polished again to create a new observation surface. This process was repeated to obtain information on the low-resistance areas in the depth direction, and SSRM images were acquired from three locations. SSRM measurements were done under a vacuum environment of 1 × 10−4 Pa at room temperature. The applied voltage was −4 V (probe side was positive), and the probe sweep speed was set to 4 and 1 μm/s in the wide and enlarged view, respectively. The probe sweep was in the lateral direction, and the data consisted of 512 pixels, so the resolution was about 39 nm/pixel in the wide view and about 10 nm/pixel in the enlarged view. After obtaining SSRM and BSE images of the third processing surface, a thin slice of the sample was prepared by focused ion beam machining so that the observed surface remained. Scanning transmission electron microscopy (STEM; JEOL, JEM-ARM200F) images and elemental mappings by energy-dispersive x-ray analysis (EDX; JEOL, JED-2300T) were then obtained from the same surface. The local electrical properties and microstructural data were acquired from the same observation plane to further correlate the data.

The MLCC was designed as a BaTiO3-based material with a core–shell structure containing Dy–Mg–Si. As previously reported,36,38 a single and distinct IR-OBIRCH signal point appears on the local insulation-degraded MLCC. The evaluation of this spot was performed according to the flow chart in Fig. 1. Figure 2 visualizes the resistance distribution of the local degraded area from the MLCC stacking cross section. The SSRM and BSE images form a wide view of each processing plane. Three locations were processed and observed: the center of the IR-OBIRCH signal (second processing), ∼1 μm in front of the center (first processing), and 1 μm behind (third processing). The resistance is encoded in the color tone of the SSRM images; the light areas have high resistance and the darker areas have low resistance. The low-resistance part crossing the image in a narrow line is the Ni inner electrode, which corresponds to the anode in HALT at the top and the cathode at the bottom. The normal dielectric region has a resistance of more than 100 GΩ, whereas the dielectric in the several-μm-wide region indicated by IR-OBIRCH has low resistance. Therefore, the dielectric layer lowers the resistance, forming a conductive path between the Ni electrodes. The conductive path is presumed to be cone-shaped because the low-resistance region is wider than the cathode-anode separation.

FIG. 2.

Wide-area scanning spreading resistivity microscope and backscattered electron cross-sectional images showing multilayered ceramic capacitor stacking at area of local insulation degradation.

FIG. 2.

Wide-area scanning spreading resistivity microscope and backscattered electron cross-sectional images showing multilayered ceramic capacitor stacking at area of local insulation degradation.

Close modal

The third processed SSRM image shows high dielectric resistance near the cathode. This suggests that the processing has progressed past the center of degradation, assuming that the conduction path is cone-shaped. Therefore, the third processed surface is close to the edge of the conduction path. BSE images of the same surface as imaged by SSRM are shown at the bottom of Fig. 2. The crystallites of the grains constituting the dielectric material appear clearly. Coarse grains appear in all observation planes in the conduction path near the anode, implying that these degrade the insulation in this sample. This conclusion is strongly supported by previous work.

In general, the insulation resistance of MLCC dielectric materials at high temperatures is greater at the grain boundary than in the grains.16–20 In other words, increasing the number of grains per dielectric layer in the stacking direction improves reliability, which significantly increases the mean time to failure in HALTs.14 Furthermore, the same tendency was reported for local insulation degradation.40 Therefore, the local area containing coarse grains identified in this study promotes insulation degradation because relatively few grain boundaries appear in the stacking direction compared with the normal area.

The conduction path is thus slightly inclined from the bottom right (cathode side in HALT) to the upper left (anode side in HALT), and the cathode is partially interrupted as per the BSE image of the second processing surface. Two possible reasons can explain why the conduction path forms from the right edge of the cathode: (i) The right edge of the cathode is closer to the coarse grains on the second processing surface, which is the center of the insulation-degradation area, and (ii) the edge of the cathode concentrates the local electric field.41–44 

Figures 3(a) and 3(b) show enlarged SSRM and BSE images, respectively, acquired near the cathode of the first processed surface. If insulation degradation progresses from the cathode, the conduction path boundary near the anode should have a large difference in resistance and reflect the front line of degradation, making it easy to detect. Comparing these two sets of data confirms the similar shape, size, and positional relationship of the characteristic grains on the boundary of the insulation degradation (see red arrows). This result suggests that the insulation degradation is more likely to be suppressed at shells and grain boundaries than within grains. In other words, the rate of degradation progresses more slowly at the shells and grain boundaries than within the grains so that areas of large resistance differences appear across the boundaries (the resolution of the SSRM data does not allow us to determine whether the shells resist degradation more than the grain boundaries or vice versa).

FIG. 3.

Enlarged (a) scanning spreading resistivity microscope and (b) backscattered electron image near the cathode of the first processing surface.

FIG. 3.

Enlarged (a) scanning spreading resistivity microscope and (b) backscattered electron image near the cathode of the first processing surface.

Close modal

A thinned sample was prepared to image the elemental distribution of the insulation degradation area so that the SSRM observation surface of the third processing remained. Figures 4(a)–4(c) show, respectively, the SSRM image, a TEM bright-field image, and a superimposed image created by image correlation. The shape of degraded grains inside the conduction path also appears in the SSRM image of the third processing (e.g., grains G1–G4 indicated by red arrows). Therefore, multiple coarse grains with characteristic shapes enable the images to be superimposed with high accuracy. The superimposed image shows that the coarse grains have low resistance.

FIG. 4.

(a) Scanning spreading resistivity microscope image, (b) TEM image, and (c) superimposed image created by the image correlation method on the third processed surface. Each of the grains G1–G4 is considered to overlap in panel (c).

FIG. 4.

(a) Scanning spreading resistivity microscope image, (b) TEM image, and (c) superimposed image created by the image correlation method on the third processed surface. Each of the grains G1–G4 is considered to overlap in panel (c).

Close modal

The sample was thinned to visualize the distribution of trace elements contained in the dielectric material. Figures 5(a)–5(d) show the SSRM image, the STEM image, a Dy elemental mapping image, and the resistivity distribution and Dy elemental mapping superimposed image, which is an enlargement of the upper-left anode region shown in Fig. 4. This MLCC has a core–shell structure, and this plane is presumed to be the edge of the conduction path. Therefore, the local evaluation of this plane should reveal how microstructure affects insulation degradation. The images in Figs. 5(a) and 5(b) are superimposed using several grains with distinctive shapes. Figure 5(c) shows that Dy is uniformly distributed in the coarse grains. The EDX point analysis of Ba and Ti spectra confirms that the main component is BaTiO3, indicating Dy-BaTiO3 solid solution grains. Figure 5(d) shows that core–shell grains appear, which suggests that they suppress the spread of insulation degradation. In addition, core–shell grains are dominant in most of the high-resistance regions that do not contain conduction paths. These local analyses thus clearly support the increase in the number of grain boundaries and the control of grain microstructure as an effective material design strategy for improving reliability.

FIG. 5.

(a) Scanning spreading resistivity microscope image, (b) scanning transmission electron microscopy image, (c) Dy element mapping image, and (d) resistivity distribution and Dy element mapping superposition image near the conduction path boundary of the third processing surface.

FIG. 5.

(a) Scanning spreading resistivity microscope image, (b) scanning transmission electron microscopy image, (c) Dy element mapping image, and (d) resistivity distribution and Dy element mapping superposition image near the conduction path boundary of the third processing surface.

Close modal

These data also provide suggestions for further improving the reliability of MLCCs. First, the generation of such coarse grains should be minimized, which is possible by identifying the generating mechanisms and taking countermeasures. Second, the quality of core–shell grains should be improved. At the conduction path boundaries in Fig. 5, some core–shell grains seem to suppress the spread of insulation degradation, whereas other core–shell grains have already become low resistance. The degree of degradation of core–shell grains may also depend on the positional relationship of coarse grains and other factors. However, differences in the microstructure of each core–shell grain may play a role in suppressing insulation degradation. A better understanding requires devising both evaluation and sample manufacturing techniques. The former would show the relationship between grain boundary structure and electrical properties, and the latter would prepare samples to facilitate the interpretation of the results. Cycling these techniques should clarify the essential phenomena and provide clear perspectives for improving product quality.

The authors have no conflicts to disclose.

Kazuyoshi Izawa: Conceptualization (equal); Data curation (equal); Formal analysis (equal); Writing – original draft (equal); Writing – review & editing (equal). Masashi Utsunomiya: Data curation (equal); Formal analysis (equal). Shingo Inayama: Supervision (equal); Writing – review & editing (equal). Kiyoshi Matsubara: Supervision (equal); Writing – review & editing (equal). Katsumasa Yasukawa: Supervision (equal); Writing – review & editing (equal).

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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