Layered semimetal electrodes for future heterogeneous electronics

With the CMOS integrated circuit (IC) technology reaching sub-10 nm device node, the development of future energy efficient electronics inevitably requires the inclusion of new materials or modified device/circuit architectures or a combination of both.¹ Co-integration of emerging nanomaterial with the CMOS platform is one of the forward pathways leading to the concept of CMOS + X era electronics or heterogeneous electronics.² Here, X stands for a suitable material/concept enabling significant improvement in the performance and functionalities of CMOS based ICs. Layered materials have emerged as a strong candidate to give rise to disruptive technologies on their own as well as to be the “X” factor in the CMOS + X era electronics.² In the diverse family of layered materials, a group of materials exhibit the semimetallic characteristics across all thickness range from bulk to monolayer. A number of rich physical phenomena like charge density waves,³ superconductivity,⁴ colossal magnetoresistance,⁵ quantum spin Hall insulating state,⁶ topological surface-state Fermi arcs, and chiral anomaly-induced negative magnetoresistance⁷ have been realized in these layered semimetals. Being semimetallic in nature, these materials possess excellent electrical conductivity at atomically thin dimensions and are apt for their application as a conducting electrode. Indeed, these semimetals have been utilized as an electrode material in a range of devices, such as 2D transistor,⁸ photodetector,⁹ battery,¹⁰ supercapacitor,¹¹ and fuel cell for hydrogen storage¹² applications. In this work, the suitability of the transition metal dichalcogenide based layered semimetals as an electrode is investigated by integrating them in two core device structures used in CMOS technology. The device structures are a metal–semiconductor (MS) junction with germanium (Ge) as a semiconductor substrate and a metal–oxide–semiconductor (MOS) structure with a silicon (Si) substrate. In MS diodes with n-type Ge (n-Ge) substrates, realizing low resistance Ohmic contact between the n-Ge substrate and the metallic electrode has been the long lasting challenge for the community to solve.^13,14 Ideally, a low work function (WF) metal should yield an Ohmic contact with n-Ge. However, rectifying contacts occur between metallic electrodes and the n-Ge substrates due to the large Schottky barrier height (SBH) at the interface caused by the Fermi level pinning (FLP) near the valence band edge of the semiconductor. FLP is attributed to the metal induced and defect induced gap states at the semiconductor surface.^13,14 Several strategies have been proposed to reduce the FLP in Ge based MS devices. In this direction, most recently, it has been demonstrated that the use of semimetal Bismuth (Bi) instead of the conventional metal as a contact electrode improves the device performance.^8,15 In other works, improved MS diode performance has been reported after inserting different number of graphene layers between the conventional metallic electrode and the n-Ge substrate.^16,17 However, in this approach, the SBH values seem strongly susceptible to the number of graphene layers.¹⁶ Moreover, a 3D metal is needed to make electrical contact to the ultrathin graphene, which makes its WF susceptible to the choice of the top contact metal.^16,18 Furthermore, there are theoretical predictions highlighting the use of van der Waals (vdW) layered semimetals as an electrode to improve the interface qualities and, hence, reduction of contact resistance at the MS interface leading to better device performance.^19–21 Increased interlayer interaction in transition metal dichalcogenide based vdW semimetals can result in decreased interlayer resistance in vertical direction and, hence, improved device performance.^22,23 In our second device geometry, these semimetals are integrated as an electrode in MOS capacitors with 5 nm thermally grown SiO₂ as a gate insulator on the p-Si substrate. Conventional metals, when deposited on the gate dielectric, consume and contaminate the top few nm of the underneath insulator as a result of chemical reaction at the interface.^24,25 It imposes serious reliability issues especially for ultrathin gate insulator devices. With layered semimetals as a gate electrode, it is anticipated that such unwanted reactions will not occur at the interface and the insulator will remain pristine.

In this work, we consider a range of layered semimetals e.g., T_d-WTe₂, 1T′-MoTe₂, 1T-PtTe₂, and 1T-PtSe₂ as an electrode material and integrate them as a hetero-interface onto the standard semiconductor like Si and Ge. The T_d-WTe₂ and 1T′-MoTe₂ show semimetallic behavior throughout the thickness, while the 1T-PtTe₂ and 1T-PtSe₂ have a finite bandgap in monolayer up to few layers and the gap closes in the bulk.^9,26–28 Here, two types of core devices, i.e., (i) semimetal/SiO₂/Si MOS capacitor and (ii) semimetal/n-Ge MS junction diodes, are fabricated. Interface between semimetal and the underneath material in both kinds of devices is investigated by high resolution transmission electron microscopy (HRTEM) analysis. Before integrating these semimetals into devices, their WF is evaluated by Kelvin probe force microscopy (KPFM) measurements. WF values, thus, obtained are corroborated with the SBH of the MS junction diode, capacitance–voltage (C–V) analysis of MOS devices, and density functional theory (DFT) calculations.

For KPFM experiments, the semimetals were exfoliated on the gold deposited SiO₂/Si substrate. The measurements were performed in the amplitude modulation (AM) KPFM mode in the Park AFM system under ambient conditions within a few hours after the exfoliation to avoid the surface contamination of the samples. The WF of the semimetals was extracted from the surface potential difference of the semimetal with respect to the gold. To fabricate the n-Ge MS diode, the antimony doped n-Ge wafers with resistivity 0.01–0.05 Ω·cm were thoroughly cleaned using trichloroethylene, acetone, and IPA sonication followed by 2% HF dip and DI water dip for two to three times. Just after cleaning, the crystals of T_d-WTe₂, 1T′-MoTe₂, 1T-PtTe₂, and 1T-PtSe₂ were exfoliated onto n-Ge substrates using the scotch tape method to form the semimetal contact. Here, the T_d-WTe₂, 1T′-MoTe₂, 1T-PtTe₂, and 1T-PtSe₂ crystals were purchased from the supplier HQ Graphene. To fabricate the MOS capacitors with semimetal electrodes, the boron doped p-type Si wafers were cleaned using trichloroethylene, acetone, and IPA dip followed by standard RCA1 and RCA2 cleaning and HF dip and then rinsed with DI water. Just after the cleaning, the Si wafers were loaded into the oxidation furnace to grow a thin layer of SiO₂. Thickness of SiO₂ was confirmed with the spectroscopic ellipsometer. Then, the semimetals were exfoliated onto the Si/SiO₂ stack to get the MOS capacitors. These semimetallic electrodes were directly probed using the tip of the probe station. For comparison, MOSCAPs with conventional metal titanium nitride (TiN) were also fabricated on a similarly prepared SiO₂/Si substrate using a shadow mask. Finally to complete the device fabrication, aluminum was deposited at the backside of all the n-Ge diodes and the MOS capacitors to form global Ohmic contact to the semiconductor substrates. The area of MS junction diodes or MOS capacitors was equal to the area of the flakes. The flakes with lateral size of 30 × 30 μm² were chosen carefully so that these can be probed using the tip of the probe station. The thickness of the flakes in the range of 50 nm was of our interest in these experiments as the thinner flakes because of their small lateral size cause difficulty in probing. The two probe current–voltage (I–V) and capacitance–voltage (C–V) measurements of the devices were carried out using a Cascade Microtech Manual/Thermal Probe station equipped with Keysight B1500A parameter analyzer. All the measurements were done at room temperature under dark and in ambient conditions unless mentioned.

A schematic of the semimetal–oxide–semiconductor (MOS) capacitor and semimetal/n-Ge MS diode is shown in Figs. 1(a) and 1(b), respectively. Optical microscopic (OM) image and AFM height profile of semimetal T_d-WTe₂ on the n-Ge substrate is shown in Figs. 1(c) and 1(d), respectively. Corresponding OM and AFM height profile images for other semimetals are shown in supplementary material Fig. S1. Raman spectroscopic data for all semimetals on n-Ge substrate are shown in Figs. 1(h)–1(k). Each semimetal is characterized by the presence of the characteristic in-plane and out of plane vibrational modes as shown in Figs. 1(h)–1(k). The peak positions are assigned as per the available reports in the literature.^29–32 The full width at half maxima (FWHM) of the most prominent Raman peaks of T_d-WTe₂ (⁠ $A 1 9$⁠), 1T′-MoTe₂ (⁠ $A g$⁠), 1T-PtTe₂ (⁠ $A g 1$⁠), and 1T-PtSe₂ (⁠ $E g)$ is found to be 4.3, 4.7, 5.1, and 4.6 cm⁻¹, respectively. The low FWHM values of the Raman peaks signify the high crystalline quality of the materials.^33–36 The interface quality of the heterostructure between metallic electrode and the underneath material is one of the most important factors deciding the device performance. Depending on the particular device, metallic electrodes need to be deposited on an insulator or directly on the semiconductor. In both cases, metallic electrodes may contaminate/degrade the underneath material either due to the chemical reaction between the two or due to the decaying wave function of the conventional metal atoms into the underneath material. It has been reported that in n-Ge, this interaction introduces metal induced gap states leading to the FLP while in MOS structures, this contamination leads to the poor oxide breakdown strength.^37–39 We investigated the interface between metallic electrodes (both conventional metal and the layered semimetals) and underneath material using high resolution transmission electron microscopy in both MOS and MS diode configurations. The cross-sectional HRTEM images of the TiN/SiO₂/Si, semimetal/SiO₂/Si, and semimetal/n-Ge interfaces have been shown in Figs. 1(e)–1(g), respectively. Here, TiN is deposited by sputtering technique. The interlayer spacing of the semimetallic 1T′-MoTe₂ and T_d-WTe₂ is 0.74 and 0.72 nm, respectively, which are similar to the values reported in the literature.⁴⁰ In Fig. 1(e), metallic encroachment into the underneath SiO₂ layer can be clearly seen as marked by the red arrow. Other HRTEM image marking the presence of TiN in the underneath SiO₂ is shown in supplementary material Fig. S2. On the other hand, the interface between the semimetal and the underneath materials (SiO₂ or Ge) as shown in Figs. 1(f) and 1(g) is sharp and clean. The vdW gap between the semimetallic electrode and the underneath layer is the key reason for the formation of a clean interface.

By knowing the WF of the substrate, the tip WF is calibrated and the WF of the semimetals have been estimated from the surface potential difference between the substrate and the sample. The WF of the gold has been considered as 5.0 eV⁴³ with respect to that the WF of the semimetals has been evaluated. There is a clear trend of increasing WF of these semimetals on the order of T_d-WTe₂, 1T′-MoTe₂, 1T-PtTe₂, and 1T-PtSe₂ as shown in Fig. 3(b).

MOS capacitors having layered semimetals as a top electrode were electrically characterized to analyze the C-V behavior of these devices. All the C–V curves, as shown in Fig. 3(a), are well shaped having minimal stretch out and clearly distinguishable regions of accumulation, depletion, and the inversion with applied gate bias. Well-shaped C–V curves indicate the high interfacial quality of the devices and the uniformity in the WF and, hence, in the flatband voltage. It also indicates that potential distribution across the lateral dimensions of the layered semimetal is uniform after electrically probed by the tip of the probe station. Non-uniform flatband voltage across the gate electrode in a MOS device leads to kink in the C–V curves.¹⁸ MOS capacitors are also used to extract the WF of the semimetallic electrode as discussed in our previous work.⁴² As shown in Fig. 3(a), the flatband voltage of the C–V curves shifts rightward on the order of T_d-WTe₂, 1T′-MoTe₂, 1T-PtTe₂, and 1T-PtSe₂ gate electrode devices suggesting the increasing order of the WF of these semimetals in this order. The WF values obtained from the C–V analysis of the MOS capacitors agree well with the WF estimated from the KPFM measurements and from DFT calculations as shown in Fig. 3(b). The details of the DFT calculations are given in supplementary material Note S1.

Equipped with the WF data as obtained from the KPFM and the MOS capacitor experiments, MS diodes having layered semimetals as a metallic electrode and n-Ge as a semiconducting substrate were characterized. For these devices, the I–V characteristics are measured in both reverse bias (RB) and forward bias (FB) conditions as shown in Fig. 3(c). As a preliminary observation, it is clearly seen that (i) the ON-current density of the diode is of the order of 1 μA/μm², which is comparable to the standard conventional metal/n-Ge diode ON-current.³⁸ (ii) With lower WF semimetal, its Fermi level lies closer to the conduction band of the n-Ge resulting in the reduction of the SBH. The reduced SBH allows increased carrier injection from the semimetal to the n-Ge at negative applied bias voltages. Hence, there is a modulation of the OFF-current density of the semimetal/n-Ge diode by an order of magnitude just by changing the semimetal as shown in Fig. 3(c). This is a consequence of de-pinning of Fermi level at the ultra-clean n-Ge/semimetal interface. The SBHs of the semimetal/n-Ge diodes, as shown in Fig. 3(f), are extracted by analyzing both the FB and RB I–V characteristics.

Further to confirm the accuracy of the extracted SBHs obtained from the reverse bias I–V analysis, we also extracted the SBH from forward bias I–V following the method proposed by Cheung et al.⁴⁶ 

The series resistance (R_s) of the diodes is in the range of 50–130 Ω, originating from the vertical resistance across the layered semimetal, the semimetal/n-Ge interface, and the resistance of the n-Ge substrate along the direction of the current flow. The low value of the series resistance of the diodes signifies that the bulk semimetals do not contribute much to the resistance along the vertical direction. Also, the series resistance obtained from both of the straight line fits shown in Fig. 3(e) are the same, which confirms the accuracy of the parameter extraction. The values of SBH and series resistance calculated from FB and RB current transport analysis are tabulated in Table I.

The WF of the semimetals used in this study ranges from 4.8 to 5.1 eV while the valence band and the conduction band edges of the Ge are at E_v = 4.0 eV and E_c = 4.67 eV, respectively.⁴⁸ For the semimetals used in the present study, the Fermi level lies close to the valence band of the n-Ge and, thus, forming a Schottky diode. Nevertheless, the SBH is decreasing with the WF of the semimetals as marked by an arrow shown in Fig. 3(f). The lowest SBH value obtained in our work (with T_d-WTe₂) is compared with those reported in the literature with graphene¹⁶ and conventional metal⁴⁷ electrodes as shown in Fig. 3(d). Our SBH values are smaller (larger) than those obtained with the conventional metal (bilayer graphene) electrode devices. The SBH with the semimetallic electrode (our work) and with graphene electrode (which has smaller WF ∼4.4 eV compared to that of T_d-WTe₂) lie parallel to the Schottky–Mott limit. On this line, a semimetal having a WF of around 4.0 eV will have its Fermi level aligned with the conduction band of the n-Ge and should yield an even smaller SBH and hence the Ohmic I–V response. This proposal is highlighted in the form of band alignment in Fig. 3(g).

To summarize, the suitability of the co-integration of the layered semimetals with conventional CMOS platform using two most prevalent semiconductors, i.e., Si and Ge, is investigated. In this direction, devices of the form MOS capacitors and MS diodes are fabricated with the layered semimetals as an electrode. As revealed by the HRTEM analysis, these semimetals form a pristine and clean interface with the underneath material SiO₂ and Ge used in the MOS and MS devices, respectively. Before integrating these semimetals into devices, their WFs are estimated using KPFM measurements. The WF values, thus, obtained are further corroborated with the values extracted from MOS capacitors and DFT calculations. The near ideal C–V curves of the MOS devices confirm the uniform potential distribution across the lateral dimensions of these semimetals and their high quality interface with the SiO₂. Furthermore, these semimetals form an excellent interface with the n-Ge as revealed by the large ON-current and successively decreasing value of the SBH with semimetals having smaller WF. Most importantly, these semimetals do not add any unwanted series resistance across the current conduction path in the diodes. These experimental observations suggest that these semimetals can indeed be integrated with conventional CMOS platforms to develop future CMOS based heterogeneous electronics.