The impact of buffer thickness upon the transport-limited buffer trapping effects in carbon-doped power GaN-on-Si devices

GaN-on-Si is an excellent material platform for high-performance power GaN devices,^1–3 in which carbon-doped buffer layers are typical to boost the voltage-blocking performance of the device.^4–6 Carbon atoms can substitute the nitrogen atoms in the lattice as weak p-type dopants, compensating for the background n-type conductivity in unintentionally doped (UID) GaN.⁷ However, the carbon dopants also function as trap states, which can be charged with electrons at high biases or high currents, depleting the carriers in the 2-dimensional electron gas (2DEG) channel.^8–10 Such trapping effects result in current collapse and, therefore, the increase in dynamic on-resistance, deteriorating the energy efficiency and the reliability of GaN-on-Si devices.^11–13 

The buffer-related trapping effects are affected by two processes: (i) the activation/deactivation of the carbon dopants, and (ii) the transport of the carriers within the buffer layers. The former refers to thermal capture/emission of charges from the traps, following the Arrhenius law and featuring an activation energy (⁠ $E A$⁠) of ∼0.9 eV above the valence band.^14,15 The charge transport, on the other hand, is a non-Arrhenius process at high carbon doping concentrations and shows a much lower E_A, which depends on the epitaxy.^9,16 The E_A of thermal effect and transport effect can be extracted from current transients from discharging and charging buffer layers, respectively.^17,18

Recently, it is shown that the charge transport plays an essential role in the trapping effects in carbon-doped GaN-on-Si due to the high dislocation density and the heavy carbon doping.^9,13,18–32 Previous studies including simulation results, experiments, and lumped circuit models^{11–13,17,18} have shown that the dislocations as well as the defect band formed by the heavy carbon doping offer paths for charges to move along the entire epi stacks when the device is at high voltages, leading to redistribution of charges across the buffer and resulting in either elevated^21,26,29 or diminished current collapse.^18,31

In this work, we investigated the transport-limited trapping effects in GaN-on-Si buffer layers along with the impact of T_Buf upon such effects. Behaviors of devices with different T_Buf are statistically and quantitatively compared, and key energy levels and mechanisms of vertical charge transports are revealed. The results show that an increased T_Buf diminishes the electron transport through the defect band formed by carbon doping as well as by direct injection from the Si substrate, thanks to the reduced electric field, which can greatly reduce the current collapse and improve the stability of the device.

Samples in this work were fabricated on commercial GaN-on-Si epitaxies [Fig. 1(a)]. The two wafers share a similar heterostructure, including a 2-nm undoped GaN cap layer, a 20 nm Al_0.25GaN barrier layer, and a 1 nm AlN spacer layer, followed by an undoped GaN channel layer, but are with different T_buf of 4.2 μm (Wafer-A) and 5 μm (Wafer-B). The carbon doping in this work was by auto-doping, with a concentration of 2 × 10¹⁹ cm⁻³. While auto-doping is investigated here, it should be noted that the extrinsic carbon doping is beneficial in addressing the trapping issues.¹⁷ Hall measurements showed a typical sheet resistance of 270 Ω/sq, a typical mobility of 2200 cm²/V s of the 2DEG, and a typical carrier concentration of 1 × 10¹³ cm⁻². High-resolution x-ray diffraction (XRD) revealed full width at half maximum of 586 arc sec in symmetric (002) scan and 790 arc sec in asymmetric (102) scan for Wafer-A, and of 595 and 879 arc sec for Wafer-B, respectively. The samples show similar screw dislocation densities of 6.9 × 10⁸ and 7.1 × 10⁸ cm⁻² for Wafer-A and Wafer-B, respectively, according to the XRD results,^33,34 indicating that they presented a comparable amount of leakage paths as screw dislocations play a more important role on vertical current.^29,31

Two types of devices were fabricated for measurements. Ungated TLM structures were used to monitor the channel conductance, with source-to-drain spacing of 30 μm and width of 100 μm [Fig. 1(a)]. In addition, a large-size test structure was used to extract the vertical leakage current (I_Total) at low/medium voltages, whose diameter was as large as 1 mm for the Ohmic contact. Back-gate measurements were implemented in this work, including double sweeps and current transients. The channel conductivity was monitored with a small drain voltage (V_D) of 0.5 V to minimize surface trapping, and statistical results were determined from at least 18 devices of the same type if not otherwise specified.

The vertical charge transports can lead to several currents within the buffer [Fig. 1(a)]. The first current (I_Dipole) is due to ionization of acceptor-like traps and leads to accumulation of holes at the bottom of the carbon-doped GaN layer as shown in Fig. 1(a), which is similar to the formation of dipoles.^22,35 The trapped states could also be de-ionized by the holes from the UID GaN layer, thanks to the reverse leakage current (I_PN) of the PN junction formed at the interface of the UID GaN/GaN:C layers, which can increase the number of carriers in the 2DEG channel.^21,29,31 I_Defect is the current through the impurity conduction band formed by high-concentration carbon dopants,^27,32,36 and I_Sub is the current resulted from injection of electrons from the substrate at high voltages, both of which result in negative charges trapped in the buffer layers and deplete the 2DEG channel.³¹ 

T_Buf has great the impact upon buffer trapping dynamics (Fig. 2). When V_Sub is –100 V, both samples present negligible hysteresis in I_D [Fig. 2(a)], suggesting little trapping effects and direct capacitive coupling between the 2DEG and the substrate. Here, the ramp rate of V_Sub was 14 V/s. Positive charging occurs when the bias is increased to –400 V [Fig. 2(b)], as revealed by the obvious hysteresis in I_D, which, however, does not degrade the channel conductance when comparing the initial and final current values in the double sweep (ΔI), as illustrated in Fig. 1(b). Wafer-A exhibits a greater hysteresis as compared to Wafer-B, showing that more positive charges are stored when T_Buf is reduced owing to the higher electric field. In addition, the I_D of Wafer-A presents a knee point (V_Sub = –175 V) in the negative sweep, since the accumulation of positive charges within its buffer counteracts partially the depletion from the substrate bias and weakens its modulation.^26,29 The polarity of I_D hysteresis in Wafer-A is completely inverted when V_Sub is increased to –600 V and current collapse is observed, signified by the degradation indicated by the ΔI [Fig. 2(c)]. This shows the stored charges have become negative within Wafer-A, since electrons injected from the substrate are dominant at such high voltages, as shown by the large I_Total within Wafer-A, which partially depletes the channel and reduces the I_D. In contrast, Wafer-B does not present such behavior until V_Sub approaches –800 V [Fig. 2(d)], thanks to its thickened buffer layers, which reduce substrate injection of negative charges and mitigates the current collapse.

The increased T_Buf is highly effective in mitigating the current collapse resulted from substrate injection at high substrate biases. Figures 3(a) and 3(b) present the dependences of A_Hys and ΔI upon V_Sub in both samples, respectively. When the buffer is 4.2 μm-thick as in Wafer-A, the ΔI starts to increase as V_Sub reaches –400 V [Fig. 3(a)], because its large I_Total leads to a net increase in trapped negative charges in the buffer, as revealed by the inversion of dA_Hys/dV_Sub within Wafer-A in Fig. 3(b), which decreases the carrier density in the 2DEG channel. When the V_Sub is beyond –400 V, the A_Hys keeps reducing and even turns negative when V_Sub is beyond –500 V, resulting in monotonically increasing ΔI. In addition, the higher bias results in increasing deviation of ΔI within both samples, which is affected by the nonuniformity of trap states, the leakage path, and lateral charge transports.^20,38 The ΔI of Wafer-A exhibits a large average ΔI of –6% with respect to the initial values as the bias is elevated to –600 V, and the maximum average ΔI is as high as 15% at this voltage. In contrast, the A_Hys keeps increasing until –600 V and remains positive within the voltages investigated [Fig. 3(a)] when the T_Buf is increased to 5 μm in Wafer-B, showing a small ΔI that is almost constant even until V_Sub reaches –600 V. The average ΔI within Wafer-B was only –0.1% at –600 V and –3% at –800 V, which are much smaller than the values within Wafer-A. These results clearly show that the increased T_Buf can reduce the buffer-related current collapse at high biases, by reducing the injection and limiting the vertical transport of negative charges from the substrate, thanks to its enhanced buffer resistance.

In addition, the increased T_Buf is also effective in diminishing current collapse that resulted from I_Defect at medium voltages. Figure 4 shows the dependence of I_D and I_Total vs stress time (t) under various V_Sub from –100 to –400 V, and the inset in Fig. 4(d) shows the dependence of ΔI upon V_Sub. When V_Sub is –100 and –200 V, both samples present increasing I_D as time continues, suggesting deionization of trap states out of I_PN, and enhancing the channel conductance by up to 10% [Figs. 4(a) and 4(b)]. While the I_D in Wafer-B keeps increasing even when V_Sub reaches –400 V, the I_D within Wafer-A decreases by up to –30% and –50% at V_Sub of –300 V and –400 V, respectively. This is because of the I_Defect, which results in stored negative charges in the buffer layer and depletes the channel, leading to the decreased I_D. Such observation is well consistent with the observed negative A_Hys observed in Wafer-A as shown in Figs. 2(c) and 2(d).

The difference between the two wafers in trapping behaviors under low bias are caused by their different I_Total, which is much more prominent within Wafer-A as compared to Wafer-B [Figs. 4(c) and 4(d)]. At biases of –100 and –200 V, both samples present I_Total lower than 0.1 nA at t = 1000 s. The I_Total increases with t within Wafer-A as the bias reaches −300 V, while that in Wafer-B decreases with t, which leads to less trapped negative charges and so diminished current collapse. The increased I_Total within Wafer-A presents the leakage current due to impurity conductance,^27,32,36 as shown by the inset of Fig. 4(c).

At a bias of –100 V [Figs. 5(a) and 5(b)], the deionization of traps within both wafers presents τ_i with an exponential dependence upon the temperature, rather than a logarithmic one, revealing a transport-limited non-Arrhenius process with small average E_A of 66 meV in Wafer-A and of 180 meV in Wafer-B (Fig. 6), which is dominated by the reverse I_PN of the u-GaN/GaN:C PN junction.^26,29,31 As the bias increases to –400 V [Fig. 5(c)], the ionized acceptors result in the diminishing I_D within Wafer-A, and the τ_i again exponentially depends upon the temperature. The E_A in this scenario is increased to 0.3 eV (Fig. 6), which is still much smaller than the E_A of carbon dopants (0.9 eV). This indicates the I_Defect is limited by the transport through the defect band that formed by carbon doping,^16,19 resulting in increased negative charges in the buffer layers and, therefore, the reducing I_D within Wafer-A.

The enhanced buffer thickness is highly effective in diminishing the I_Defect, and, therefore, Wafer-B presents reduced current collapse. As shown in Fig. 5(d), Wafer-B shows an increased I_D vs the temperature when biased at –400 V, which follows a non-Arrhenius behavior and reveals a small average E_A of only 75 meV (Fig. 6). Such a small E_A is similar to the E_A within Wafer-A under –100 V, but much different than the E_A within Wafer-A under –400 V, suggesting the vertical leakage current is still limited by the I_PN rather than I_Defect within Wafer-B despite the high voltage of –400 V. Consequently, the increased bias for Wafer-B can result in an enhanced I_PN and reduced I_Defect, therefore diminishing the current collapse, which is highly consistent with results observed in Fig. 4.

To sum up, Wafer-B presents reduced current collapse since its I_Sub and I_Defect are diminished, thanks to the reduced electric field by the thickened buffer layers. Figures 7(a) and 7(b) show I_D and g_m,Sub vs V_Sub, in which g_m,Sub = d(I_D)/d(V_Sub). Figures 7(c)–7(e) show energy-band schematics of different transport behaviors. Three critical voltages can be observed: V₁, V₂, and V₃, which indicate the voltages when I_PN, I_Defect, and I_Sub start to dominate the trap dynamics, respectively. As the V_Sub ramps from 0 to V₁, ionization of acceptors increases the g_m,Sub. Then the I_PN leads to the deionization of trapped states [Fig. 7(c)], which is transport limited and results in the positive charging of the buffer layers and the decreased g_m,Sub. As V_Sub is beyond V₂, the significant transport-limited I_Defect introduces negative charges and, therefore, additional depletion of the channel, leading to an increased g_m,Sub and the current collapse [Fig. 7(d)]. When the bias is as high as V₃, a symmetrical I_Sub is observed [Fig. 7(e)]. This suggests a non-blocking contact at the substrate, which behaves resistively with Fermi-level pinned near the bulk level.²² In this case, the electrons flow along the conduction band²⁴ as shown in Fig. 7(e), resulting in significant current collapse. Wafer-B with an enhanced T_Buf shows a lagged V₂ and V₃ with decreased I_Total, which clearly shows that it resulted from reduced electric field, thanks to its thickened buffer layers.³⁹ It should be noted that judicious strain engineering can be required for increased buffer thicknesses to diminish the generation of cracks during the epitaxy and the back-end processes.^40–42 

In this work, we investigated the impact of T_Buf upon trapping dynamics and vertical transport mechanisms within GaN-on-Si devices. The results indicate that an increased T_Buf can greatly reduce the current collapse by diminishing the I_Defect through the defect band formed by heavy carbon doping as well as the I_Total due to the substrate injection at high voltages, thanks to the reduced vertical electric field. These results provide an effective path toward high-performance power GaN-on-Si device with minimized current collapse that can be highly beneficial for energy-efficient and eco-friendly power systems.

The authors would like to thank Enkris Semiconductor Inc. for the high-quality GaN-on-Si epitaxies as well as the staff in SUSTech Core Research Facilities (SCRF) for their technical support in device fabrication. This work is supported in part by the National Natural Science Foundation through Grant No. 62104092 and in part by the Natural Science Foundation of Guangdong Province under Grant No. 2021A1515011952.