High performance germanium on silicon photodiodes for back-end-of-line photonic integration

Photodetection in the near-infrared is widely used in optical communication, imaging, and spectroscopy. III–V materials perform well at telecommunication wavelengths (⁠ $1.3 – 1.6 μ$m), but CMOS incompatibility has proven to be a significant hurdle, inspiring research in alternative solutions. In particular, monolithic integration of Ge on Si has been researched extensively.¹ Optimized SiGe graded buffer layers were used to achieve low threading dislocation densities (TDDs),^2,3 but the thick buffer layers had integration difficulties. Thin buffer layers deposited at low temperatures were developed as part of a two-step growth process in UHVCVD, achieving low TDD that was further reduced with cyclic annealing.⁴ High performance photodetectors using this methodology have since been reported,^5–7 and Ge photodetectors are currently included in photonic foundry PDKs.⁸ 

However, the remaining limitations of Ge optoelectronic integration with Si CMOS circuits reduce design flexibility and increase device size. The metal interconnect layers in the back-end-of-line (BEOL) serve as the ideal placement for these photodetectors, but high quality Ge growth on an amorphous substrate and a strict thermal budget of < 450 °C are required.¹ The lack of a semiconductor substrate was addressed with single crystalline Ge growth on SiO₂ at 450 °C using 2D confinement.^9,10 Alternatively, a process may not need to be integrated in the interlayer dielectric (ILD), but it must be compatible with existing metal interconnects and satisfy the required thermal budget. Low temperature deposition methods, such as e-beam evaporation^11–13 and molecular beam epitaxy,¹² have also been attempted, but each technique revealed performance limitations. In this work, high performing Ge photodiodes were grown on a Si substrate at BEOL-compatible temperatures.

Ge was grown epitaxially via low pressure chemical vapor deposition (LP-CVD) and ultra-high vacuum chemical vapor deposition (UHV-CVD) on a p-Si epi (10¹⁵–10¹⁶ cm⁻³)/n-Si substrate (⁠ $2 × 10 18$ cm⁻³) at nominal 400 °C growth and fabricated into remote heterointerface photodetectors, as shown in Fig. 1. Ge mesas with radii of 250 μm–2 mm were defined via chlorine-based RIE-etching. The metal contacts consisting of Ti (20 nm)/TiN (20 nm)/Al (300 nm) were deposited with an E-beam evaporater and patterned using standard lithography and liftoff methods. Devices were passivated with 20 nm Al₂O₃ and predominantly showed a dark current dependence with area as opposed to diode periphery.

Photoresponse measurements were performed using a laser diode pigtailed with a single-mode optical fiber at λ = 1310 nm. A Keithley sourcemeter was used in conjunction with an optical chopper and a bias tee in order to direct the modulated photocurrent to a lock-in amplifier. Measurements were taken at 1 V intervals on separate devices with each error bar representing a 68% confidence interval. Due to the thin Ge absorption layer, internal quantum efficiency (IQE) was used as a performance metric for device quality. Responsivity measurements are also reported to aid in comparison with the literature, despite the lack of adjustment for surface reflection or absorption for a given Ge thickness.

The photodetector designs in Fig. 1 share some characteristics with a uni-traveling carrier (UTC) photodiode structure such as an absorbing p-Ge layer and ballistic electron transport in the depleted collector (p-Si/n-Si).¹⁴ The design selection was motivated by potential for lower leakage current and evaluation of carrier recombination at the Ge/Si interface. In addition, the incorporation of graded boron (B) doping in Fig. 1(b) generates an electric field in Ge, which promotes a drift current in order to reduce recombination at the Ge surface and transit time to the Ge/Si interface. Similar examples of this device structure grown at elevated temperatures have been reported in the literature.^15–17 

Figure 2 illustrates the quantum efficiency of uniform and graded doping devices from Fig. 1. Devices with graded B-doping had higher IQE at λ = 1310 nm by approximately 4%–5% relative to devices with uniform Ge doping. However, the latter achieved a remarkable responsivity of 0.10 A/W and an IQE of 34% at V_r = 5 V without annealing, despite the reliance on carrier diffusion to the Ge/Si interface. The minority carrier lifetime of low-temperature grown Ge was, therefore, sufficiently high to largely overcome diffusion time in the 0.6 μm Ge absorption layer.

The IQE turn-on at V_r = 3–4 V in Fig. 2 marks the range over which the p-Si region approaches full depletion such that the E field may reach the Ge/Si interface. At zero bias, the device structure inherently includes E fields from both the p-Ge/p-Si interface and the p-Si/n-Si junction. The E field at the interface results in an energy barrier that inhibits carrier collection at zero bias, as shown in the energy band diagram of Fig. 3. The inset plot in Fig. 3 shows that a reverse bias of V_r = 5 V is required for the E field from the homojunction in silicon to extend to the interface and fully lower the barrier. The minor increase in IQE between V_r = 5 and 10 V results from slight extension of the depletion zone into the highly doped p-Ge. The higher E field in p-Ge also provides faster drift transport through the defective Ge/Si interface and minimizes carrier recombination.

The possibility of further improving the device performance with low temperature anneals (⁠ $500 – 550 °$ C) was motivated by Hall effect results of undoped Ge epitaxy on SOI, grown via UHV-CVD at low temperatures. The conductivity of Ge was initially p-type, and heat treatments at 450 °C converted the Ge to n-type conductivity. The p to-n-type conversion followed first-order kinetics with 1.7 eV activation energy and was associated with acceptor-like point defect removal.¹⁸ Annealing of the Ge epilayer in photodiodes was projected to improve the device performance by the same mechanism, and the level of IQE improvement could be correlated with the reduction in the point defect density for a given annealing time and temperature.

The Ge-on-Si photodiode with the highest collection efficiency was annealed at 500 °C for 3 h with J_d and IQE shown in Fig. 4. As expected from device design, J_d was suppressed at low voltages and increased to near its final value of 165  $μ$A/cm² at V_r = 5 V. Responsivity improved with annealing from 0.11 A/W at V_r = 5 V as-grown to 0.17 A/W after 500 °C 3 h. Although the theoretical responsivity limit at λ = 1310 nm is 1.06 A/W, the 0.6 μm Ge layer only absorbs 45% of the incident light, reducing the responsivity limit to 0.48 A/W. The surface reflection due to lack of anti-reflection (AR) coating further reduces the maximum possible responsivity to 0.30 A/W. In our design, a perfect AR coating would increase responsivity of as-grown and 500 °C 3 h annealed devices to 0.18 and 0.27 A/W, and complete absorption in the 600 nm Ge epi would further increase responsivity values to 0.40 and 0.60 A/W, respectively.

The impact of 500–550 °C annealing on IQE for Ge-on-Si photodiodes with graded B-doping is shown in Table I. Annealing reduced J_d by ∼100–150  $μ$A/cm² for graded B-doped devices, and photodiodes with uniform doping exhibited a similar trend. The annealing conditions of 500 °C 3 h and 550 °C 1 h increased IQE by ∼19% and were not statistically different from one another. This similarity in IQE improvement is supported by the defect kinetics model, as relatively small acceptor-like point defect fractions under 5% were expected for both annealing conditions relative to as-grown material. Although the 500–550 °C anneals were beyond BEOL-compatibility, the observed device improvements with annealing reinforced some of the findings in prior work, in particular, the conductivity type conversion with annealing.¹⁸ 

A comparison with previous work on Ge-on-Si photodiodes processed in a wide temperature range demonstrates competitive responsivity and dark current density in our low-temperature grown photodiodes. Low-energy plasma-enhanced chemical vapor deposition growths are performed at 450–500 °C followed by 780 °C cyclic annealing resulted in J_d = 41 μA/cm² and 0.4 A/W at λ = 1.55 μm,¹⁹ while UHV-CVD growths on 10 μm thick, optimized relaxed buffers yielded J_d = 150 μA/cm² and 0.13 A/W at λ = 1.3 μm.³ In a different approach, a BEOL-compatible process designed for low-temperature bonding and layer transfer at 300 °C has deposited Ge epitaxy via metal organic chemical vapor deposition and included a furnace anneal in O₂ at 750 °C, yielding a responsivity of 0.29 A/W and J_d = 780 μA/cm² at λ = 1.55 μm.²⁰  Table II provides a performance summary of comparable device structures with process parameters included.

High performance was demonstrated in this work for low-temperature grown Ge-on-Si photodiodes with and without post-growth annealing. Responsivity and dark current density comparable to devices processed at high temperatures were achieved at thermal budget conditions of < 450 °C. As-grown diodes showed a responsivity of 0.11 A/W and J_d = 272 μA/cm² at V_r = 5 V, and annealing conditions of 500 °C 3 h improved such performance to 0.17 A/W and J_d = 165 μA/cm². Relating the observed improvements in IQE with point defect annihilation highlighted the importance of point defects in the Ge material quality and addressed that the threading dislocation density is not the only significant factor in characterization of defects for Ge epitaxy.

We wish to acknowledge the facilities provided by MIT.Nano.