Gate leakage modeling in lateral β-Ga₂O₃ MOSFETs with Al₂O₃ gate dielectric

Monoclinic gallium oxide (β-Ga₂O₃) transistors and rectifiers are promising devices with perspective application in high-power, high frequency,^1,2 and high efficiency conversion of energy.^3,4 β-Ga₂O₃ transistors are mostly based on lateral or vertical MOS structures,^3,5,6 in which the gate insulator usually consists of aluminum oxide (Al₂O₃).^7–10 Currently, the development of gallium oxide technology is mainly driven to the optimization of the breakdown voltage and ON-resistance of the devices, to fully exploit the theoretical limitation given by the high Baliga Figure of Merit.¹¹ A full understanding of the gate leakage in Al₂O₃/β-Ga₂O₃ transistors is still missing in the literature; this is of paramount importance because it can be related to many macroscopic effects, such as excess of power consumption, limitation in the gate swing,¹² an increase in the high-frequency noise in RF transistors.^13–17 Moreover, gate leakage was demonstrated to play a fundamental role for the gate reliability in other wide bandgap transistors, such as GaN MOS/MOSFETs,^16,17 GaN HEMTs with p-GaN or MIS gate,^18–20 and SiC MOSFETs.²¹ 

The goal of this study is to model the static and dynamic behavior of the gate leakage current in β-Ga₂O₃ MOSFETs with Al₂O₃ dielectric. The results indicate that (i) the gate leakage is dominated by Poole–Frenkel (PF) conduction in forward bias at room temperatures and higher, whereas (ii) at cryogenic temperatures in forward bias the dominant process is Fowler–Nordheim (FN) tunneling. In addition, the gate current shows a decrease with thermally activated time constants, associated with the trapping of electrons that inhibit the FN conduction process. Gate leakage dynamic model is also supported by TCAD simulations capable of reproducing the experimental data.

Devices under test consist of β-Ga₂O₃ MOSFETs, processed on homoepitaxial Mg-doped (100) β-Ga₂O₃ wafers. After the epitaxial growth of a 200 nm thin Si-doped β-Ga₂O₃ channel (⁠ $n=2.3× 10 17 c m − 3$⁠) using metal-organic chemical vapor deposition (MOCVD), a 100 nm-gate recess was formed by etching the semiconductor material with BCl₃ reactive ion etching. Then, a 25 nm thick Al₂O₃ dielectric was deposited by thermal atomic layer deposition (ALD) at a temperature of 300 °C using a SENTECH system SI PEALD. A saturation dose of trimethylaluminium and water vapor with a total of 268 cycles were predetermined using a constant N₂-flow as carrier and purge gas to achieve the dielectric properties. Al₂O₃ gate dielectric was preferred with respect to SiO₂ or others because it is currently the most common choice for β-Ga₂O₃ power devices, because of the high dielectric constant³ and good interface quality.^22,23 Both Ohmic and gate contact consist of a Ti/Au metal stack. Detailed information on the hepitaxial growth, processing, and electrical characteristics can be found in the works of Tetzner et al.^7,24 that reports on the same devices considered in this study.

To evaluate the physical processes responsible for conduction, we carried out temperature-dependent characterization between 120 and 350 K. Figure 1(b) reports the I_G–V_G curves collected in this temperature range, whereas Fig. 1(c) shows the extracted I_G–T characteristic for some relevant voltage levels. The measurements were performed with an Agilent 4155C semiconductor parameter analyzer, by first sweeping the devices in negative bias (from 0 to −20 V) and then in positive bias (from 0 to 5 V). The samples were enclosed in a cryogenic probe station that provides temperature control and excellent shielding from electrical noise. The negative bias sweep was proven to not introduce any trapping effect that can impact the forward characteristics.

To avoid possible effect of the electron trapping discussed in Ref. 25, before every measurement the devices were exposed to 15 min of UV illumination, which was proven to completely restore the prior trapping state. A demonstration of the effectiveness of the UV-assisted detrapping is reported in Fig. SM1 in the supplementary material.

Figure 1(b) shows that for high voltages (>3 V) at high temperatures (>350 K), the I_G–V_G becomes flat and slightly decreases during the measurements. By performing the same measurement with different sweep rates (not shown here), we noticed a correlation with the duration of the measurements, so it is possibly related to a dynamic decrease in the gate current. To investigate the process, we analyzed the gate leakage current transient during a constant voltage experiment, at different temperatures and constant $V G=5 V$ [Fig. 1(d)], and constant temperature (⁠ $T=300 K)$ and different voltages [Fig. 1(e)]. The gate current shows a significant decrease over time, with a strongly temperature-enhanced time constant at high temperature compatible with the duration of the I_G–V_G measurements (∼100 s).

As an initial step, we analyzed the DC I_G–V_G characteristics to understand the static conduction model, which may provide information on the physical properties of the dielectric layer.²⁶ 

Given the insufficient accuracy of the experimental setup at the lowest current range, the reverse leakage current was analyzed qualitatively. To improve the signal to noise ratio, we considered the average of the reverse leakage current reported in Fig. 1(b) for each temperature and then extracted a tentative activation energy from the Arrhenius Plot in Fig. 2(a) of 24 meV, by fitting the reasonable experimental data.

The term $E A , 0−β F ≜ E A *$ describes activation energy reduction induced by the electric field by the Poole–Frenkel mechanism (PFM), where $β= q π ε 0 ε r=2.51× 10 − 4 eV (V×c m ) − 1 2$ for aluminum oxide [see Fig. 2(d) for a schematic view of the P–F model and the notation].

By fitting the I_G–T data in Fig. 1(c), we extracted the activation energies that are reported in a Poole–Frenkel plot in Fig. 2(b). Electric field values used in the calculations were extracted from a TCAD simulation of the structure. Effective activation energy $E A *$ extracted from the fit was found to decrease with increasing electric field, as expected from the PF model, and the extracted value for $β$ (i.e., the slope of the Poole–Frenkel plot) is in good agreement with the theoretical value reported above, thus confirming the validity of the model.²⁸ 

The results in Fig. 3(b) indicate that the equations well reproduce the experimental data, with reasonable fitting parameters. The one that deviates most from the ideal value is the PF coefficient $β$ that results ∼1/3 of the value obtained in the DC characterization section. However, the absolute value of the parameter is still reasonable, and the difference can be associated with other effects not considered by the simple model described above.

With respect to the constant component of the current $I T E$ in Eq. (4) (i.e., the residual current after the transient), we found that it is thermally enhanced and can be attributed to a thermionic emission term, due to the potential barrier associated with the depletion region at the β-Ga₂O₃/Al₂O₃ interface. In the case of strong positive bias [Fig. 1(e)], the logarithmic trapping discussed in Ref. 25 induces a small decrease for longer times of the $I T E$ component that cannot be considered constant anymore.

The proposed gate leakage model was then validated by means of TCAD simulations based on the Synopsys Sentaurus framework. The device structure was first implemented following the cross section reported in Fig. 1(a). Doping of the n-type channel was implemented by introducing a shallow donor trap with concentration of $n=2.3× 10 17 c m − 3,$ to guarantee a realistic device physics. Drain and source contacts were implemented as Ohmic, and the gate as Schottky with work function $χ T i=4.33 eV$⁠, to match the one of titanium.³² The simulation was then tuned in terms of fixed oxide charge, contact resistances, and interface states to match the I_D–V_G characteristics of the physical devices in terms of threshold voltage, subthreshold slope, saturation current to guarantee the same electrostatic behavior (Fig. 5, inset). To simulate the gate leakage current, we included in the oxide layer a deep level with activation energy of 0.12 eV coupled by tunneling to the channel to simulate the Poole–Frenkel conduction model. The activation energy was chosen as fitting parameter. Finally, trapping in the oxide was induced by adding a high concentration (⁠ $1× 10 18 c m − 3)$ ideally empty deep level distribution along the oxide region (the activation energy does not influence trapping). Gate current was then simulated in transient mode. To match the time constants of the current transients, we adjusted the cross section and the constant emission rate of the deep levels (that models self-detrapping of electrons from the level by tunneling). The results of the simulations were compared with the experimental gate current transients in Fig. 5. The current transient from 10 ms to 1 s was obtained by exploiting the fast current measurement of the Agilent 4155 that allows sampling times below 1 ms. This mode cannot be used to sample the full transient because of the lower current sensibility and limited memory buffer of the instrument. Simulations are in line with the experimental data, especially in terms of the trapping time constant and value of the initial gate current.

In conclusion, we discussed the gate leakage current model in the static and the dynamic regime of β-Ga₂O₃ lateral MOSFETs. We demonstrated that the gate leakage is dominated by a Poole–Frenkel conduction mechanism at high-temperature/high-bias, whereas at low temperatures and forward bias the gate leakage current can be ascribed to Fowler–Nordheim tunneling. In addition, we modeled the time-dependent drop of the gate leakage transient by considering the trapping of electrons within the gate dielectric. A model based on rate equations was proposed, whose effectiveness has been validated by means of TCAD simulations, that showed excellent agreement with the experimental results.