Nb/a-Si/Nb Josephson junctions for high-density superconducting circuits

For decades, the density of superconducting digital circuits has increased, notably benchmarked by the work at MIT-Lincoln Laboratory, where the existing fabrication process using AlO_x-barrier Nb junctions (Nb/Al-AlO_x/Nb) has reached a junction density of 4.2 $× 10 6$ JJ/cm² for externally shunted junctions and 7.4 $× 10 6$ JJ/cm² for self-shunted junctions.¹ This level of integration has been achieved, together with decreasing wire widths, by increasing $J c$ to 0.6 mA/μm², where the junctions are self-shunted. The minimum JJ critical current (and, therefore, JJ size for a given $J c$⁠) for SFQ circuits is typically set by the thermal noise at the operating temperature of 4 K. The current noise should be a small fraction of the critical current, $I c$⁠. A safe limit and typical choice for stable operation at 4 K is $I c$ = 50 μA.² For $J c$ = 0.6 mA/μm², this minimum current corresponds to a 0.33 μm diameter circular junction, a size which is at least an order of magnitude larger than the limits of advanced lithography processes. Superconductor circuit densities could be improved by increasing $J c$ and making smaller junctions, provided that junctions with such high $J c$ values have the required uniformity and reproducibility. However, higher $J c$ values may be beyond the limits of required junction uniformity for AlO_x barrier junctions because these insulating barriers require a thickness under 1 nm. Demonstrations of junctions with such high current densities and thin barrier thickness have shown increasing variability of the junction properties; for example, outlier junctions with high $I c$ and even “missing” junctions acting as shorts.^3,4 Ultra-thin barriers lead to increased sub-gap conductance, deviating from ideal SIS behavior, dominated by a small percentage of the junction area (less than 10%). Several reasons for this have been postulated, such as a random distribution of point contacts,⁵ distribution of oxygen vacancies leading to localized regions with decreased barrier height,⁶ and thickness variability of the barrier.⁷ 

An alternative to high- $J c$ AlO_x-barrier Nb junctions is amorphous silicon (a-Si) barrier Nb junctions. Previous work on Nb/a-Si/Nb junctions, like those demonstrated in the early 1980s, showed the feasibility of this type of junction for use in digital circuits.⁸ However, the concurrent development of the AlO_x-barrier Nb junctions⁹ and demonstration of their uniformity and junction properties made them the preferred junctions for most applications. However, to obtain further increases in circuit density from today's values, an increase in $J c$ above 1 mA/μm² is required. In this work, we investigate a-Si-barrier Nb junctions as a possible solution to achieve these higher levels of $J c$⁠. Since the barrier height of Si is smaller than that of AlO_x, for the same value of $J c$ the a-Si barrier is about five times thicker than AlO_x. With such thicknesses, the effects of thickness variability and probability of point contacts are greatly reduced, allowing for better uniformity and reproducibility of $I c$ values at high $J c$ for Nb/a-Si/Nb junctions.

The a-Si-barrier Nb junctions are fabricated on 7.62 cm (3 in.) silicon wafers with 150 nm of thermal oxide. A trilayer of Nb/a-Si/Nb is deposited by dc sputtering at room temperature. The base pressure of the deposition chamber is 4.7–7.3 $× 10 − 11$ bar (3.5–5.5 $× 10 − 8$ Torr). The sputtering sources are 7.62 cm in diameter, and their distance to the sample is $≈ 15$ cm. The niobium base and counter electrodes are deposited with a source power of 1000 W and the barrier is deposited with a source power of 100 W. The substrate is rotated during deposition to improve film uniformity across the wafer. Flowing nitrogen gas at the back of the platen holding the substrate is used to keep the temperature of the substrate under 90 °C during deposition. The p-type silicon target has a purity of 99.999%, a thickness of 6.35 mm, and a low resistivity (0.005–0.02 $Ω$ cm) for dc sputtering. The junctions are defined by inductively coupled plasma reactive ion etching (ICP-RIE) in a mixture of SF₆ and C₄F₈. An insulating layer of SiO₂ is deposited by electron cyclotron resonance plasma-enhanced chemical vapor deposition (ECR-PECVD). During the oxide deposition, the wafer is cooled by back-flowing helium gas, keeping the temperature under 100 °C. Vias to the top of the junctions are etched through the insulator layer by ICP-RIE and a wiring layer of Nb is deposited and patterned to complete the circuit. The thicknesses of the different layers for the nonplanarized (and planarized) process are: bottom wiring layer 200 nm, JJ base electrode 240 nm, JJ counter electrode 160 nm, top wiring layer 350 nm (300 nm), insulating layer 280 nm (200 nm), 130 nm for contact pads, and 130 nm for shunt resistors used for some of the test junctions. Chemical–mechanical planarization was used on the highest $J c$ wafers where smaller JJs were needed to avoid high $I c$ values and consequent junction heating and temperature rise during current–voltage (I-V) measurements when in the resistive state. A series of JJ sizes was fabricated on each chip to extract the value of $J c$ from the slope of $I c$ vs junction radius.¹⁰ All measurements were taken at 4 K with the sample immersed in liquid helium, except the data in Fig. 2.

Multiple wafers were processed with different thicknesses for the a-Si barrier to obtain a wide range of $J c$ values. The thickness of the barrier is determined by the duration of the silicon deposition at a fixed sputtering power of 100 W. Precise control is achieved through the computer-controlled opening and closing of a shutter between the source and the substrate. Film uniformity across the wafer is discussed in Ref. 10. The deposition rate is measured using a crystal monitor that can be placed in front of the substrate location and retracted for film deposition. The tooling factor was calculated by use of a profilometer and AFM thickness measurements of patterned $≈ 100$ nm thick Si films.

Figure 1 shows the exponential dependence of $J c$ on the barrier thickness; it contains data from this work together with data from Ref. 8, which was limited to low values of $J c$⁠. The dependence of $J c$ with decreasing thickness (sputter duration) for a-Si barrier junctions follows a constant slope up to very high $J c$ values, in contrast to that of AlO_x junctions in which a steeper dependence of $J c$ on thickness (or oxygen exposure) can be seen for high $J c$⁠.^11,12 This is the regime where the AlO_x junctions start to behave more like weak links instead of tunneling junctions.⁵ 

NIST has developed self-shunted Nb/Nb_xSi_1−x/Nb Josephson junctions (JJs) with Nb-doped a-Si barriers for voltage standards and arbitrary waveform synthesizers, as well as for high-speed, compact superconductor digital, and mixed signal circuits.^10,13–15 However, due to the strong temperature dependence of $J c$ in these junctions, these circuits are sensitive to small (∼0.2 K) temperature fluctuations at their 4 K design operating temperature. Additionally, for potential emerging applications in quantum information, SFQ circuits are being placed at different temperature stages in a cryostat, requiring broader operating temperature ranges for these circuits as well as junctions that are relatively insensitive to temperature variations.^16–18 The Nb/a-Si/Nb JJs studied in this work are superconductor–insulator–superconductor (SIS) junctions with insulating a-Si barriers and, like JJs with AlO_x barriers, have substantially reduced temperature sensitivity approaching that predicted by BCS theory. Figure 2 shows the temperature dependence of $J c$ from 4 to 9 K for JJs with different barrier compositions. We use junctions with 15% Nb doping for voltage standard circuits, 9% for self-shunted JJs in digital SFQ circuits operating at 4 K, and junctions with no Nb doping (a-Si) for SFQ circuits and arbitrary waveform generators operating below 4K down to millikelvin temperatures.^18,19

Normalized I–V characteristics for Nb/a-Si/Nb junctions with different $J c$ are shown in Fig. 3. As $J c$ increases, the most obvious change is the decrease in hysteresis, quantified by the parameter α defined as the ratio of the retrapping current (the value of current in the return branch when the voltage drops back to zero) to the critical current. Maximum hysteresis occurs for α = 0, while α = 1 means no hysteresis. For $J c$ = 2.8 mA/ $μ m 2$⁠, there is still a considerable amount of hysteresis with $α = 0.65$⁠. To achieve junctions with $α > 0.9$ without shunting resistors, desirable for making high junction density circuits, even higher $J c$ will be required.

Even at a $J c$ as high as 2.8 mA/μm², there is no clear evidence in Fig. 3(d) of junction excess current above the gap voltage (⁠ $V g$⁠).²⁰ Excess current is associated with sites in the barrier having higher transmission, such as point defects.^21,22

The two junctions with highest $J c$ show a small decrease in $V g$⁠. Three of the four junctions show a slight negative slope around this region. This “back bending gap behavior” indicates that the junction is heating as the current increases along and above $V g$⁠. To avoid this heating effect, the current could be reduced by using deep sub-micron-sized junctions and thermal conduction to the Si substrate could be improved by removing the thermal oxide.

Normalized I–V curves where $I c$ has been suppressed by a magnetic field applied in the plane of the junctions are shown in Fig. 4(a). The normalized differential conductance, which we refer to as the subgap structure (SGS), for the two junctions is shown in Figs. 4(b) and 4(c); the similarity of these two SGS curves indicates that transport in the 1.47 mA/μm² junction is not dominated by localized regions with high transparency.²¹ The SGS in Fig. 4(c) shows a shallow peak at $0.5 × V g$ for the high $J c$ junction, indicating an increase in conductance processes as well as pure tunneling. Such possible processes include multiple Andreev reflection (MAR),²³ multiple-particle tunneling (MPT),²⁴ and self-coupling (SC),²⁵ as discussed below.

We show in Fig. 5 the modulation in $I c$ for two junctions, one with low $J c$ = 0.018 mA/μm² and one with high $J c$ = 2.8 mA/μm², both in the small junction regime. Both junctions show behavior close to that expected for junctions with uniform current distribution, even in the case of high $J c$⁠, where the thinning of the barrier has not caused irregularities such as regions of high density.

Increasing the density of superconducting circuits would benefit from the flexibility to use higher-temperature processes developed by the semiconductor industry; for example, plasma-enhanced chemical vapor deposition (PECVD) is widely used to deposit high quality SiO₂ insulation layers at deposition temperatures of ∼300 °C. However, the fabrication of superconductive circuits using Nb/Al-AlO_x/Nb junctions is typically limited to processes where the temperature of the junctions does not exceed ∼150 °C.²⁷ For these reasons, Nb/a-Si/Nb junctions were annealed to study changes in their electrical properties and possible compatibility with higher temperature fabrication processes.

For Nb/Al-AlO_x/Nb JJs, it has been reported that the $R N$ increases with annealing temperature (with the corresponding decrease in $I c$⁠) up to a factor of 5 for 2 h at 240 °C and that at higher temperatures the probability of destroying them is high.²⁸ For Nb/a-Si/Nb junctions, the main effect observed from annealing is an increase in the critical current, as described below.

Two annealing regimes were studied as follows: (1) chips were annealed on a hot plate in ambient air and the temperature was ramped up to 200 °C and maintained for 4 h or (2) chips or wafers were annealed in an oven with flowing nitrogen or argon gas and the temperature was ramped to 300 °C, maintained for 1 h, then ramped down to room temperature.

I–V measurements of junctions measured before and after annealing demonstrate an increase in $J c$ in all cases. For samples annealed at 200 °C, the increase is a factor of 5; for 300 °C, the increase shown in Fig. 6 is a factor of 15–19. This factor may depend on the initial value of $J c$ and the specific mechanisms causing the $J c$ increase. Further work is needed to study the reproducibility of targeting $J c$ after annealing.

We observe that the SGS of the unannealed junction with a $J c$ of 1.47 mA/μm² is virtually identical to the 200 °C annealed junction with a final $J c$ of 1.3 mA/μm² as shown in Figs. 7(a) and 7(b), respectively. I–V curves also show very similar values of hysteresis (α) and $I c R N$⁠, as can be seen in Table I. On the other hand, JJs annealed at 300 °C for 1 h have an important difference; and $V g$ is reduced compared to unannealed junctions, as shown in Figs. 8 and 9. Multiple peaks in the SGS in Fig. 7(d) are not seen in unannealed junctions with similar $J c$ [Fig. 7(c)] and are also absent in similarly annealed junctions with lower $J c$ [Figs. 7(a) and 8(c)]. The SGS peak positions of the 3 mA/μm² junction are 0.82 (⁠ $0.36 × V g$⁠), 1.14 (⁠ $0.5 × V g$⁠), and 1.39 mV (⁠ $0.61 × V g$⁠), where $V g$ occurs at 2.27 mV. This low value of $V g$ also reflects obvious heating during the measurement, as evident from the loopback of the trace at $V g$⁠.

Current modulation in a magnetic field was also measured for annealed samples. We see the same behavior as for unannealed junctions even for the highest $J c$= 3 mA/μm² after 300 °C annealing. This can be seen in Fig. 10, indicating uniform current density through the junctions by the agreement of experimental data with the theory from Eq. (1).

Junction capacitances were obtained by the method of resonance in symmetric dc-SQUIDs.²⁹ The SQUID I–V curve shows a resonance step at $V r = Φ 0 / 2 π L C$⁠, where L is the total loop inductance, and C is the capacitance of each of the junctions.

Table I shows the measured values of specific capacitance (⁠ $C ′$⁠) for junctions with different process conditions, together with the amount of hysteresis, quantified by the parameter α described above, and the Stewart-McCumber damping parameter (β_c) obtained from α.³⁰ For annealed samples, the values of $C ′$ are similar to those of unannealed samples with similar $J c$ values, indicating that they end up with a similar thickness in barrier material, which determines the value of both $J c$ and $C ′$⁠, assuming that other properties of the barriers are unchanged.

The similar properties of 200 °C annealed junctions with $J c$ = 1.3 mA/μm² and unannealed junctions with $J c$ = 1.47 mA/μm² suggest that the increase in $J c$ could be caused by a slight decrease in the barrier thickness, although this work has not identified the cause. An increase in the value of $J c$ from the pre-annealed value of 0.32 mA/μm² to a post-200 °C annealed value of 1.3 mA/μm² would correspond to a decrease in barrier thickness of $≈ 0.5$ nm (see Fig. 1).

For junctions annealed at 300 °C (Figs. 8 and 9), the decrease in $V g$ suggests a change in the superconductors comprising the junctions. We speculate that, in addition to the barrier thickness decrease observed with the 200 °C anneal, there might be formation of niobium silicide at the interfaces, further decreasing the barrier thickness. For unannealed junctions, an increase in the value of $J c$ from 0.2 to 3 mA/μm² corresponds to a decrease in barrier thickness of $≈ 0.9$ nm, similar for an increase in $J c$ from 0.007 to 0.13 mA/μm². Since $J c$ depends exponentially on barrier thickness, an annealing process that results in a fixed barrier thickness reduction would increase $J c$ by a constant factor, independent of the pre-anneal $J c$⁠.

An increase in $J c$ for the annealed samples and, in particular, a decrease in $V g$ for 300 °C annealed junctions may indicate that the statistical $I c$ variation of the junctions across a chip could increase significantly, rendering the anneal process unusable for large scale circuits. Figures 11(a)–11(d) show the $I c$ distributions for nominally identical junctions measured on 5 × 5 mm² chips; we measured $≈$ 50 junctions on one chip for each of four cases: unannealed low $J c$⁠, unannealed high $J c$⁠, annealed at 200 °C, and annealed at 300 °C. The distributions show that there is less than a 25% increase in the fitted sigma as a result of the annealing.³¹ 

On the physical process causing SGS, the presence of MAR is characterized by excess current above $V g$⁠, together with peaks in the differential conductance at values $V g / n$⁠, where n is an integer. MAR in non-ideal tunneling junctions is caused by a distribution of barrier pinholes where the transmission coefficient $| T | 2$ approaches unity; this is seen in AlO_x-barrier junctions where the thickness in high- $J c$ JJs is just a monolayer.^5,23 It is less probable that this effect is present in a-Si-barrier junctions, where the thickness of the barrier is $∼ 4$ nm for $J c$ = 1 mA/μm². Based on the factors already mentioned, the presence of a peak in the normalized conductance near $2 3 × V g$ in the 3 mA/μm² junctions, and the possibility that there are regions of the junctions with different superconducting energy gaps due to the formation of silicides after annealing at 300 °C, we believe that it is more probable that MPT is the cause of SGS in these junctions.³² 

For targeting high- $J c$ junctions, it can be an advantage to have an increase in $J c$ after annealing, as a thicker barrier is easier to control and reproduce. To substantiate this will require a study of wafer-to-wafer reproducibility after annealing; the present study does not have a significant quantity of samples.

To maximize the circuit density in SFQ electronics, the elimination of shunt resistors is necessary. Of the junctions presented here, the minimum hysteresis corresponds to those with $J c$ = 3 mA/μm² and damping parameter ∼2–3. We expect that junctions with $J c$ = 10 mA/μm² will be critically damped, not needing shunting resistors. For this $J c$⁠, an $I c$ = 50 μA corresponds to a JJ diameter of 80 nm. The chip-level junction uniformity that we modestly demonstrated may permit good circuit yield at this $J c$⁠.

We have electrically characterized Nb/a-Si/Nb SIS Josephson junctions (JJs) fabricated by dc sputtering over a wide range of critical current densities $J c$ ranging from 0.01 to 3 mA/μm². These junctions exhibit an SIS-like $J c$ temperature dependence that substantially improves their operating temperature range compared to JJs with Nb-doped a-Si barriers. We have annealed these a-Si junctions at both the chip and wafer level and observe a large increase in $J c$ by a factor of $≈ 5$ for our 200 °C annealing process and a factor of 15–19 for our 300 °C process. Electrical data indicate that after annealing, the junction quality is not degraded, there is no excess current, there is uniform current distribution across small junctions, and there is <25% broadening of the $I c$ distributions. The subgap structure (SGS) reveals that the conduction is dominated by tunneling and not a distribution of high transparency micro-shorts. Unlike the Nb/Al-AlO_x/Nb JJs typically used in SFQ digital circuits, these a-Si JJs have several advantages for fabricating high-speed and high-circuit-density superconducting electronics: (1) the barriers are thicker, leading to better process control, (2) the barriers can be annealed to increase the $J c$⁠, leading to easier targeting of barrier thickness for high- $J c$ junctions, (3) the barriers are sputtered and do not require an oxidation step, and (4) the barriers can be etched using the same dry etch process as for the Nb electrodes, which also simplifies the fabrication of vertical stacks of JJs. Furthermore, we have demonstrated an annealing process to increase the fabrication “thermal budget,” i.e., the robustness of these junctions to higher temperature processing, giving them an advantage over AlO_x barriers typically limited to 150 °C processing temperature.

This work was a contribution of the U.S. Government and is not subject to U.S. copyright. A portion of this work was supported by the Office of the Director of National Intelligence (ODNI), Intelligence Advanced Research Projects Activity (IARPA), under Interagency Agreement No. IARPA-200001/D2021-2101310004. The views and conclusions contained herein are those of the authors and should not be interpreted as necessarily representing the official policies or endorsements, either expressed or implied, of the ODNI, IARPA, or the U.S. government.