Stable enhancement-mode operation in GaN transistor based on LiNiO junction tri-gate

GaN high-electron-mobility transistors (HEMTs) offer outstanding properties for the next generation of power electronic devices.¹ However, one of the main criteria to fulfill fail-safe requirement is enhancement-mode (e-mode) operation. Among existing solutions, p-GaN gates are currently the technology mostly adopted commercially for e-mode GaN HEMTs due to their high reliability and stability.² However, to achieve e-mode operation with low on-resistance (R_ON), p-GaN gate technology requires a rather special process, with a thin-barrier epitaxy, selective etching of the p-GaN layer, and sometimes the re-growth of barriers or p-GaN.² While this makes the process costly and complex, it also leads to poorer performance compared to other technologies, such as gate recess.^3–5 An alternative approach to p-GaN or gate recess is gate dielectric engineering: by using charge-trap gate stacks,⁶ or negatively charged dielectrics,⁷ a positive V_TH can be achieved. However, some concerns, including their thermal instability, the requirement for initialization procedures,⁶ and the V_TH instability under gate bias stress,⁶ hinder the adoption of such technologies for power electronics.

Intrinsic p-type transition metal oxides offer another option as gate dielectrics to achieve e-mode operation. In particular, NiO_x is a promising candidate,^8–11 due to its high hole concentration.¹¹ A junction tri-gate structure has been demonstrated based on NiO_x, which presented a high breakdown voltage, positive V_TH shift compared with normal oxide, and voltage blocking capability at very high temperature.¹² This is very challenging to be achieved on normal oxide gate stack materials and, thus, opens the possibility of oxide semiconductors for high-performance GaN power transistors and diodes.¹³ However, among the reported results of NiO_x-based e-mode HEMTs, either gate recess^8,9,11 or high sheet-resistance (R_sh) epitaxy¹⁰ had to be used together with NiO_x to reach positive V_TH. This limits the device on state performance (R_ON and I_ON,max). Moreover, the presence of Ni vacancies in NiO_x results in instability in the long term as well as under high temperature operation, which greatly influences the electronic properties of the NiO_x layer.¹⁴ 

To achieve e-mode operation without degrading the device performance, an alternative approach focuses on tri-gate structures.^15–19 By reducing the tri-gate fin width together with a gate stack engineering, positive V_TH, low R_ON, and high V_BR have been achieved simultaneously.²⁰ In this work, we demonstrate high-quality LiNiO as an alternative material to form heterojunction tri-gate structure to yield stable e-mode operation. Due to the smaller offset between LiNiO and AlGaN [E_v of 1.99 eV instead of 2.53 eV, E_c of 1.26 eV instead of 2.88 eV (Refs. 10 and 21)], a larger rise in the conduction band of GaN, close to the AlGaN/GaN interface, can be achieved compared to NiO_x. This results in a much-reduced carrier density in the 2DEG under the gate and, thus, a larger V_TH shift. High hole concentration LiNiO films have also been reported,^22,23 which offers another way to optimize the device characteristics. LiNiO conformally deposited over tri-gates eases the requirements on the fin width necessary to achieve e-mode operation together with low R_ON,²¹ in addition to excellent reliability.

The LiNiO heterojunction tri-gate HEMTs were fabricated on a GaN-on-Si wafer with a 5 μm-thick buffer and a 25 nm-thick Al_0.25Ga_0.75N barrier (from Enkris Semiconductor Inc.). Such a thick barrier results in an epitaxy with a low sheet resistance (R_sh) of 275 Ω/sq. The device fabrication started with mesa isolation and definition of the tri-gate region by e-beam lithography, followed by inductively coupled plasma (ICP) etching with a depth of 180 nm. Source and drain Ohmic contacts were formed by alloying a Ti/Al/Ti/Ni/Au stack, followed by rapid thermal annealing (RTA) at 780 °C under N₂ atmosphere. A 200 nm-thick SiO₂ was deposited by plasma-enhanced chemical vapor deposition (PECVD) as the etching stop layer (ESL) and liftoff mask for the LiNiO. The gate region opening was done by buffered hydrofluoric acid (BHF). The LiNiO target was fabricated by solid-state sintering of lithium carbonate (Li₂CO₃) and nickel oxide (NiO) with a 25% atomic percentage of lithium (Li_0.25Ni_0.75O). Pulsed-laser-deposition (PLD) was performed by laser ablation with a repetition rate at 5 Hz and an energy density of 400 mJ·cm⁻² with a 248 nm KrF laser. The deposition temperature was 400 °C, and the oxygen partial pressure was 0.1 Torr. Pd/Au was deposited as a gate metal. Ion beam etching (IBE) and BHF etching were used to remove the ESL layer. A 25 nm-thick ALD SiO₂ was deposited as gate dielectric on reference devices on the same chip.

Figures 1(a) and 1(b) show the scanning electron microscope (SEM) images of the LiNiO heterojunction tri-gate device; LiNiO could be precisely patterned in the gate region by an oxide liftoff method. Figure 1(c) shows the energy-dispersive x-ray spectroscopy (EDS) mapping image of a 40 nm-wide fin cross section, revealing a good coverage of the PLD-deposited LiNiO over the tri-gate structure, which is very challenging to achieve by p-GaN regrowth. To extract the band alignment between LiNiO and AlGaN, x-ray photoelectron spectroscopy (XPS) [Fig. 1(d)] was used.²³ Δ E_C of 1.26 eV and Δ E_V of 1.99 eV between LiNiO and AlGaN were determined [Fig. 1(e)], which are smaller than NiO_x/AlGaN,^10,24 and preferred for e-mode operation.²³ 

Figure 2 shows the transfer (a) and output performances (b), revealing a positive V_TH of 0.7 V at I_D = 1 μA/mm (for a device with L_GS = 2 μm, L_G = 0.7 μm, and L_GD = 15 μm). This was achieved on a low R_sh epitaxy and a relatively short L_G, which is more challenging to demonstrate e-mode operation. All device characteristics were normalized by a total width of 20 μm. A near ideal subthreshold swing (SS) of 63 mV/dec was observed, which suggests an excellent gate control of the tri-gate structure and low density of interface traps. A high on/off ratio of 10 (Ref. 9) and peak transconductance (G_m) of 105 mS/mm indicate a small leakage current in off-state and strong gate coupling to the channel. The Ohmic gate (Pd/LiNiO) and junction formed between LiNiO and AlGaN resulted in a gate injection transistor (GIT)-like behavior,²⁵ which is reflected by a second peak in the G_m plot [Fig. 2(a)]. A maximum drain current of 390 mA/mm and R_ON of 8 Ω⋅mm were observed at V_G of 4 V. To evaluate the dynamic performance of LiNiO heterojunction tri-gate devices, a 100 nm-thick passivation layer was added in the drift region before the device process. The passivation process and test procedure are described in Ref. 26. Comparing with SiO₂ gate oxide, the LiNiO device (both passivated with the LPCVD SiN layer in the drift region) presented a significantly lower R_Dyn/R_Static ratio (at V_D = 200 V) [Fig. 2(c)]; this behavior confirms the lower interface trap of LiNiO heterojunction tri-gate devices. In addition to the excellent on-state performance, the devices could hold off-state bias of 1270 V (defined at I_off <10 μA/mm, and floating substrate) due to the well-distributed electric field by the tri-gate structure,^15,16 and hard breakdown did not happen within the measurement range until 1500 V [Fig. 2(d)].

Figure 3(a) shows the measured transfer characteristics of different tri-gate fin widths with SiO₂ and LiNiO. LiNiO devices presented a nearly 1 V positive shift in V_TH compared to SiO₂ counterparts. E-mode operation was achieved with 80 nm-wide fins with LiNiO (defined at I_D = 1 μA/mm), whereas with SiO₂, this was only possible with 30 nm-wide fins. This improvement greatly reduces the R_ON as well as the lithography requirements for defining the tri-gate fins. Figure 3(b) shows the more positive V_TH (defined at 1 μA/mm) for the same fin widths achieved with LiNiO compared to SiO₂. The excellent V_TH thermal stability performance is shown in Fig. 3(c), where the V_TH shifted from 0.6 to 0.28 V at 150 °C, showing that the device could still maintain e-mode operation even at high temperatures.

High-temperature reverse bias (HTRB) test was performed to investigate the current-blocking capability at high temperature. The time-dependent leakage characteristics of devices with different tri-gate fin widths are presented in Fig. 4(a). Both devices with 30 and 40 nm-wide fins could be fully turned off even at 150 °C with higher off-state leakage compared to room temperature, while devices with 60 nm-wide fins could not be fully turned off due to their more negative V_TH. The Weibull plot could be built from the time-to-breakdown distribution of three device sets [Fig. 4(b)]. For a narrower fin, a larger fitted parameter β was observed, which indicates a tighter distribution. The possible reason is that the deeper carrier depletion in small fin width devices ensures better device turn off, which makes the device more immune to process variation-induced punch-through. During the HTRB tests, devices failed with a sudden decrease in I_G, which is different from the I_G rising behavior observed during static breakdown tests [Fig. 2(d)]. The possible failure mechanism during such test could be a localized misfunction of the gate (from either the metal or the oxide), which results in source/drain punch-through under stress. Another aspect of these devices is that the Ohmic gate formed on LiNiO results in a larger gate current at positive V_G, which is beneficial to the on-state reliability, since there is no high electric field region in LiNiO at positive bias.²⁷ To evaluate the gate reliability, we performed step stress test [Fig. 4(c)], as well as positive and negative bias temperature instability (PBTI and NBTI, respectively) tests [Fig. 4(d)]. During the step stress test, the devices failed at a large gate bias of 10.75 V, at which a sudden reduction in gate current is observed. This suggests that the failure during high bias is not from the LiNiO layer but from a possible degradation of the gate metal after the stress. Considering the operation point V_G of 4 V, this yields a large gate bias tolerance. Small ΔV_TH of 20 mV (25 °C) and −100 mV (150 °C), respectively, were observed for negative gate bias, and ΔV_TH of −10 mV (25 °C) and −173 mV (150 °C) was observed for positive gate bias. These small ΔV_TH compared to those from MOSHEMTs^28–41 [shown in gray in Fig. 4(d)] reveal the excellent reliability of the LiNiO as a gate layer.

To evaluate the interface quality between the LiNiO and AlGaN, conductance dispersion measurement was performed on a planar heterojunction diode structure with Pd/LiNiO/AlGaN/GaN.^42,43 Due to the type-II band alignment between LiNiO and AlGaN, the LiNiO/AlGaN interface trap states can be extracted from both the first and second rising edges of the CV plots, although the second rising edge requires a complex correction to account for the gate leakage current.⁴⁴ To avoid this correction, we performed conduction dispersion measurement from the voltage range of the first rising edge in CV [Fig. 5(a)], followed by determining the interface trap density using the expressions in Fig. 5(a).⁴⁵ In Fig. 5(b), the result of fitting shows a much lower interface trap density of LiNiO compared to NiO_x,⁴⁴ as well as other high-quality dielectrics grown on AlGaN, such as Al₂O₃, ZrO₂, and SiN,^45–47 revealing the great interface quality between the epitaxial growth LiNiO and AlGaN.

Table I summarizes the device performance in this work and compares it with other e-mode devices by engineering tri-gate structure and gate stack material. This work demonstrated a high positive V_TH on a low R_sh substrate. A good R_ON and V_BR were shown at the same time.

In conclusion, in this work, we presented LiNiO junction tri-gate resulting in stable e-mode operation with low R_ON, high V_BR, and nearly ideal SS at the same time. The requirement of minimum tri-gate fin width to reach e-mode operation was considerably alleviated, from 36 to 81 nm, compared to SiO₂. Moreover, the great stability, flexibility, and interface quality of this low-temperature oxide show great potential for power applications.

This work was supported in part by the ECSEL Joint Undertaking (JU) under Grant No. 826392. The JU receives support from the European Union's Horizon 2020 Research and Innovation Program and Austria, Belgium, Germany, Italy, Norway, Slovakia, Spain, Sweden, and Switzerland.