In this work, β-Ga2O3 fin field-effect transistors (FinFETs) with metalorganic chemical vapor deposition grown epitaxial Si-doped channel layer on (010) semi-insulating β-Ga2O3 substrates are demonstrated. β-Ga2O3 fin channels with smooth sidewalls are produced by the plasma-free metal-assisted chemical etching (MacEtch) method. A specific on-resistance (Ron,sp) of 6.5 mΩ·cm2 and a 370 V breakdown voltage are achieved. In addition, these MacEtch-formed FinFETs demonstrate DC transfer characteristics with near zero (9.7 mV) hysteresis. The effect of channel orientation on threshold voltage, subthreshold swing, hysteresis, and breakdown voltages is also characterized. The FinFET with channel perpendicular to the  direction is found to exhibit the lowest subthreshold swing and hysteresis.
Beta-Gallium Oxide (β-Ga2O3) has drawn tremendous attention in power-electronics due to its ultra-wide bandgap (4.8 eV),1,2 high breakdown field (8 MV/cm), and reasonable 150 cm2/V-s electron mobility,3 leading to a 1721 Baliga's figure of merit. In addition to the high Baliga's figure of merit that outperforms SiC and GaN,4–6 single crystalline bulk substrate with wide range of controllable n-type doping concentration7,8 is also available for β-Ga2O3. Over the past decade, plenty of high power β-Ga2O3 devices, such as metal– semiconductor field-effect transistors (MESFETs),9 metal–oxide– semiconductor field-effect transistors (MOSFETs),10–13 vertical transistors,14–16 and fin field-effect transistors (FinFETs),17 with a breakdown voltage (Vbr) over 2.6 kV18 and a specific on-resistance (Ron,sp) down to 2 mΩ cm2 have been demonstrated.18 Nonetheless, the reported β-Ga2O3 transistors so far still suffer from low drive current and Ron,sp compared to GaN devices. A solution to this issue is fabricating β-Ga2O3 transistors with high aspect ratio channels. Since Ron,sp is normalized to device area from top-view, increasing channel aspect ratio would create an enhanced drive current but still remains low in device area, leading to a reduced Ron,sp.19 Therefore, the development for transistors with high aspect ratios and smooth sidewalls is crucial for β-Ga2O3.
Although a β-Ga2O3 vertical transistor with an aspect ratio over 9.27 has been fabricated through reactive ion etching (RIE),18 the high-energy ion induced damage and interface traps caused by RIE still degrade the device performance, leading to a limited 30 cm2/V·s effective channel mobility.20 In addition, the ion-induced damages typically result in notable hysteresis (200 mV–2 V) in all β-Ga2O3 transistors utilizing the RIE process.17,18 On the other hand, the plasma-free metal-assisted chemical etch (MacEtch) can produce a wide variety of 3D semiconductor structures with high aspect ratio and damage-free surfaces.21–25 β-Ga2O3 fins with low interface trap density have previously been demonstrated by photo-enhanced hν-MacEtch,26,27 and an almost hysteresis-free CV loop was achieved on the MacEtch-formed β-Ga2O3 MOSCAP structures, making it a promising etching technique for β-Ga2O3 transistor fabrication.
In this work, we demonstrate β-Ga2O3 FinFETs produced by hν-MacEtch. The DC transfer and output characteristics, and breakdown voltage are fully characterized. The effect of channel orientation on threshold voltage (Vth), subthreshold swing (SS), hysteresis, and Vbr is also studied.
Figure 1 presents a schematic illustration of the process flow for β-Ga2O3 FinFET fabrication. First, a ∼2 μm-thick lightly silicon-doped β-Ga2O3 film was grown on a (010) Fe-doped semi-insulating substrate by metalorganic chemical vapor deposition (MOCVD).28,29 The doping concentration is around 4 × 1017 cm−3. Then, channel and source/drain regions were defined through lithography followed by 30 nm Pt deposition by ebeam evaporation (Fig. 1). After a standard liftoff process, the samples were immersed into a MacEtch solution consisting of a mixture of 49% HF and K2S2O8,27 to form fin-shaped channels and source/drain mesas (Fig. 1). Subsequently, the Pt was removed by aqua regia followed by 25 nm/20 nm Ti/Au films deposition with ebeam evaporation for source and drain contact. 20 nm of Al2O3 was then deposited through the atomic layer deposition (ALD) process, followed by 1 min of 490 °C rapid thermal annealing (RTA) with N2 ambient to improve interface quality between Al2O3 and β-Ga2O3.30 After the removal of Al2O3 on top of the source/drain mesa by HF, 25 nm/20 nm Ti/Au gold gate electrodes were then deposited on the high-k layer to form the gate stack. Finally, 1 min of 480 °C RTA under N2 ambient was applied for source/drain Ohmic contact formation.
A trapezoid-like fin shape channel was first formed using the MacEtch process.26 Figures 2(a) and 2(b) show the tilted-view and focused ion beam (FIB) cut cross section SEM images of a fully fabricated β-Ga2O3 FinFET. Note that the source/drain mesa height of 3.57 μm is larger than the thickness of the epitaxial n-type β-Ga2O3 film (2 μm), suggesting the fin channel consists of both the n-Ga2O3 epitaxial layer and the semi-insulating substrate. This divides the structure into two parts: a much wider triangular part at the bottom [highlighted in red, Fig. 2(b)] and a narrow fin on top (highlighted in blue). Due to the nature of the carrier transport process in MacEtch,25,27,31–33 β-Ga2O3 MacEtch is also found to be dependent on the doping concentration.34 Therefore, the sharp transition line on the sidewall is indictive of the interface between the top n-Ga2O3 layer and the semi-insulating substrate. The active n-channel of the device is 142/570 nm in top/bottom width and ∼1.5 μm in height, leading to an aspect ratio of 4.2:1 using the average fin width [Fig. 2(b)]. Moreover, a smooth sidewall morphology can be observed on the MacEtch-formed structures (Fig. S1) compared to the rough sidewall produced by typical RIE processes. Note that the 1.5 μm fin height is smaller than the epitaxial n-Ga2O3 thickness (2 μm), suggesting the top parts of fins might be removed in the MacEtch process due to side etching.
Figure 3(a) shows the DC transfer characteristics of the MacEtch-formed β-Ga2O3 FinFETs with a 1 μm gate length (LG) and 630 nm top fin width (Wfin,top) under Vds = 5 V. At Vgs = 4 V, the drive current reaches 2.7 × 10−5 A/fin or 26.7 mA/mm when normalized to the bottom width of the active fin channels [blue region in Fig. 2(b)]. The on/off ratio is ∼105 with gate leakage current at the 100 pA level, suggesting that a gate stack with good control and low leakage is formed. DC transfer characteristics of β-Ga2O3 FinFETs with different fin widths are shown in Fig. 3(b). With LG = 1 μm and Vds = 10 V, Vth values are found to be highly dependent on the fin dimension, causing the FinFETs to shift from the depletion mode (normally on) to the enhancement mode (normally off) as the fin width decreases. As expected, a more negative gate bias is required to deplete the channel and turn off the device with increasing fin width. The Vth dependence on fin width also provides a general guideline to design transistor operation mode depending on the applications. In addition to Vth, SS is extracted to be 93.6, 84.5, and 89.9 mV/dec. for 550, 330, and 200 nm Wfin,top, respectively. With ,35 where CD, Dit, and Cox are the depletion capacitance, interface trap density, and oxide capacitance, respectively, the upper bond of Dit in the MacEtch-formed β-Ga2O3 FinFETs is estimated to be around 1.4 × 1012 cm−2 eV−1, which is not far from the CV measurement results of MacEtch-formed vertical MOSCAPs.26 This indicates that the MacEtch process does not damage the surface and has created an interface with superior Dit between Al2O3 and β-Ga2O3.
Note that all the transfer characteristics showed almost zero hysteresis [ΔVth between voltage sweeps 1 and 2, as shown in Fig. 3(a)], which is unprecedented for β-Ga2O3 FETs with vertical sidewall structures. The largest hysteresis is only 9.7 mV clockwise, which is dramatically reduced compared to the 120–800 mV hysteresis of previously reported β-Ga2O3 FETs.14,18,36,37 This nearly hysteresis-free characteristic could be attributed to the absence of RIE-induced ion damages and traps due to the MacEtch nature and is consistent with the CV results of MacEtch-formed β-Ga2O3 MOSCAPs.26
Figure 4(a) shows the linear transfer characteristics at Vds = 5 V for the β-Ga2O3 FinFET. The output characteristics with LG = 1 μm and Wfin,top = 630 nm are shown in Fig. 4(b). At Vgs = 2 and Vds = 10 V, a 24.4 mA/mm drain current is achieved. On resistance (Ron) can be extracted from the slope of the low Vds region. With the fin width extracted from the cross section SEM images [blue region in Fig. 2(b)], the Ron is estimated to be around 128.8 Ω mm at Vgs = 2 V. Thus, the Ron,sp is around 6.5 mΩ cm2 when normalized to the distance between source and drain (5 μm). If we consider the source/drain contact transfer length (LT) as 1 μm, the Ron,sp = Ron × gate width (Wg) × (LSD+2LT) can be extracted as 9.1 mΩ cm2. Note that since the carrier concentration at source/drain is only from the intrinsic doping during the MOCVD growth (∼4 × 1017 cm−3), the 1 μm transfer length could be an overestimation. As a result, the 9.1 mΩ cm2 of Ron,sp when considering LT might also be overestimated. On the other hand, the Ron,sp is expected to be further reduced though additional ion implantation to increase source/drain doping concentration, leading to a decreased contact resistivity and parasitic source/drain resistance.
With the asymmetric crystal structure of β-Ga2O3, it has also been reported that the channel orientation affects the β-Ga2O3 transistor characteristics.18 The DC transfer characteristics of β-Ga2O3 FinFETs with ∼750 nm Wfin,top and different channel orientations are shown in Fig. 5(a). At Vds = 10 V and Vov = ∼5 V, the drain currents are ∼2 × 10−5, 2.3 × 10−5, and 1.9 × 10−5 A for θ = 60°, 85°, and 90°, respectively. This shows all the drive current saturates at a similar level and suggests the channel mobility does not vary much with the orientation. Nonetheless, a clear voltage shift of the Id-Vgs curves can be observed as the channel orientation changes. To further analyze this shift, the Vth of β-Ga2O3 FinFETs with similar Wfin,top (∼750 nm) and different channel orientations are extracted and plotted in Fig. 5(b). When θ, the angle between the channel direction and , is 60° [Fig. 5(b)], a −0.9 V Vth is observed. Then, the Vth becomes more negative as the fin rotates away from the  direction and reaches its minimum at −6.9 V when the channel is counterclockwise 90° from  direction. As the angle becomes larger than 90°, the Vth starts to increase again as the channel is more aligned with . This V-shaped Vth distribution has also been reported in (001) β-Ga2O3 vertical transistors18 and could be attributed to two reasons: first, as shown in our previous work,26 the fin sidewalls become more vertical as the fin orientation approaching 90° from . This leads to a wider channel width and, thus, a more negative bias to deplete the channel. Therefore, a most negative Vth at 90° is expected. On the other hand, the interface trap quantity on the sidewalls has also been reported to vary with the fin orientation.26 As a result, this Vth trend might also imply that the interface traps on sidewalls decrease as the channel getting more perpendicular to the  direction, and the sidewalls have the lowest interface trap density and negative interface charges, leading to the lowest Vth. It is also likely that these two factors both contribute to this Vth variation.
To further analyze the impact of these sidewall interface trap densities on the transistor performance, the SS of β-Ga2O3 FinFETs with different channel orientations is also extracted [Fig. 5(b)]. SS decreases as the channel orientation rotates away from  and reaches its minimum value of 87.2 mV/dec. at θ = 90°. Like the Vth, the SS vs fin orientation also shows a V-shaped distribution. The SS can be modeled as ,35 where CD, Dit, and Cox are the depletion capacitance, interface trap density, and oxide capacitance, respectively. Accordingly, the V-shaped distribution of SS suggests that the interface trap density could be the lowest on the MacEtch-formed sidewalls when θ = 90°, consistent with the previous observation on Vth.
In addition to SS, the hysteresis of Id-Vgs curves also reflects the device and interface quality of β-Ga2O3 FinFETs. Thus, we have examined the hysteresis for MacEtch-formed devices with different orientations. As shown in Fig. 6(a), the hysteresis vs θ also demonstrates a similar V-shaped distribution with the minimum hysteresis (24 mV) at θ = 90° [Fig. 6(a)]. It was reported that the interface quality (i.e., Dit) had a direct impact on the hysteresis of the RIE-fabricated β-Ga2O3 FETs.38 Therefore, this V-shape hysteresis might imply that sidewalls have the lowest Dit when the channel is perpendicular to the  direction, in agreement with the previous results on Vth and SS.
Figure 6(b) shows the high-voltage off-state characterization of the β-Ga2O3 FinFETs [the same device as shown in Figs. 3(a) and 4]. A negative Vgs bias is applied to keep the device at off state. The gate and drain current remain low, at the detection limit of the tool, until breakdown at ∼370 V, where a spike in drain and gate current is observed. By assuming a one-dimensional electrical field distribution (E = Vgd/LGD), the electric field under the gate is estimated to be ∼1.4 MV/cm when the breakdown occurs, which is smaller than the theoretical breakdown field of β-Ga2O3.39 However, this simplified one-dimensional distribution is inaccurate for the FinFET structure. The simulated results show that a significantly higher local electrical field occurs at the corner of the fin structure.40 This could cause the breakdown to happen at a lower voltage compared to the theoretical value. As a result, a greater breakdown voltage should be achieved in the future by incorporating field plate structures into the FinFETs.18,37
Figure 7(a) shows the average breakdown voltage of the FinFETs with different channel orientations. The Vbr is within the range of 365–380 V and does not vary much with different θ, suggesting that the interface properties might not play an important role in the breakdown mechanism. Figure 7(b) shows the benchmark chart of reported β-Ga2O3 transistors in the literature. Note that the Ron,sp values plotted are extracted from the slope for the family of curves at the low Vds region under Vov = ∼5 V for all cited works. Then, the Ron,sp is normalized to the area Wg×(LSD + 2 LT) and plotted in Fig. 7(b). For those works not reporting LT, a 1 μm LT is assumed for the calculation (raw data found in the cited work are plotted in Fig. S2 in the supplementary material). We believe this would provide a better reference point for benchmarking, since originally reported Ron,sp in different papers is extracted with quite different Vov (ranging from 3 to 100 V). An alternative version of benchmarking with originally reported Ron,sp is also provided in Fig. S2. Here, the MacEtch-formed β-Ga2O3 FinFET demonstrates a reasonable 370 V breakdown voltage and a 9.1 mΩ cm2 Ron,sp, which is relatively low compared to other reported β-Ga2O3 transistors. With the nearly zero hysteresis and comparable device performance, we believe this work represents a step toward three-dimensional β-Ga2O3-based power electronics with high quality interface.
In summary, β-Ga2O3 FinFETs, produced by MacEtch with channels of good aspect ratios and smooth sidewalls, are demonstrated. The devices show near hysteresis-free Id–Vgs characteristics, presumably because of the absence of ion-induced damage, inherent to the MacEtch process. A 6.5 mΩ cm2 specific on-resistance and a 370 V breakdown voltage are achieved. The effect of channel orientation on Vth, SS, hysteresis, and breakdown voltages is also analyzed. The results suggest the sidewalls possess the lowest interface trap density when the channel is perpendicular to the  direction and best suited for FinFETs.
See the supplementary material for details: Figs. S1 and S2 show the zoomed-in SEM image of the FinFET sidewall and the Ron,sp raw data found in literature before normalization, respectively.
This material is based upon work supported in part by the National Science Foundation under Grant Nos. 1809946 and 1810041.
Conflict of Interest
The authors have no conflicts to disclose.
Hsien-Chih Huang: Conceptualization (equal); Data curation (lead); Formal analysis (equal); Investigation (equal); Methodology (equal); Project administration (equal); Validation (equal); Writing – original draft (equal); Writing – review and editing (equal). Hongping Zhao: Data curation (supporting); Funding acquisition (equal); Supervision (equal); Writing – review and editing (equal). Xiuling Li: Conceptualization (equal); Funding acquisition (equal); Project administration (equal); Supervision (equal); Writing – original draft (equal); Writing – review and editing (equal). Zhongjie Ren: Data curation (supporting). A. F. M. Anhar Uddin Bhuiyan: Data curation (supporting). Zixuan Feng: Data curation (supporting). Zhendong Yang: Data curation (supporting). Xixi Luo: Data curation (supporting). Alex Huang: Supervision (equal). Andrew Green: Resources (equal). Kelson Dean Chabak: Resources (equal); Writing – review and editing (equal).
The data that support the findings of this study are available within the article and its supplementary material.