β-Ga₂O₃ FinFETs with ultra-low hysteresis by plasma-free metal-assisted chemical etching

Beta-Gallium Oxide (β-Ga₂O₃) has drawn tremendous attention in power-electronics due to its ultra-wide bandgap (4.8 eV),^1,2 high breakdown field (8 MV/cm), and reasonable 150 cm²/V-s electron mobility,³ leading to a 1721 Baliga's figure of merit. In addition to the high Baliga's figure of merit that outperforms SiC and GaN,^4–6 single crystalline bulk substrate with wide range of controllable n-type doping concentration^7,8 is also available for β-Ga₂O₃. Over the past decade, plenty of high power β-Ga₂O₃ devices, such as metal– semiconductor field-effect transistors (MESFETs),⁹ metal–oxide– semiconductor field-effect transistors (MOSFETs),^10–13 vertical transistors,^14–16 and fin field-effect transistors (FinFETs),¹⁷ with a breakdown voltage (V_br) over 2.6 kV¹⁸ and a specific on-resistance (R_on,sp) down to 2 mΩ cm² have been demonstrated.¹⁸ Nonetheless, the reported β-Ga₂O₃ transistors so far still suffer from low drive current and R_on,sp compared to GaN devices. A solution to this issue is fabricating β-Ga₂O₃ transistors with high aspect ratio channels. Since R_on,sp is normalized to device area from top-view, increasing channel aspect ratio would create an enhanced drive current but still remains low in device area, leading to a reduced R_on,sp.¹⁹ Therefore, the development for transistors with high aspect ratios and smooth sidewalls is crucial for β-Ga₂O₃.

Although a β-Ga₂O₃ vertical transistor with an aspect ratio over 9.27 has been fabricated through reactive ion etching (RIE),¹⁸ the high-energy ion induced damage and interface traps caused by RIE still degrade the device performance, leading to a limited 30 cm²/V·s effective channel mobility.²⁰ In addition, the ion-induced damages typically result in notable hysteresis (200 mV–2 V) in all β-Ga₂O₃ transistors utilizing the RIE process.^17,18 On the other hand, the plasma-free metal-assisted chemical etch (MacEtch) can produce a wide variety of 3D semiconductor structures with high aspect ratio and damage-free surfaces.^21–25 β-Ga₂O₃ fins with low interface trap density have previously been demonstrated by photo-enhanced hν-MacEtch,^26,27 and an almost hysteresis-free CV loop was achieved on the MacEtch-formed β-Ga₂O₃ MOSCAP structures, making it a promising etching technique for β-Ga₂O₃ transistor fabrication.

In this work, we demonstrate β-Ga₂O₃ FinFETs produced by hν-MacEtch. The DC transfer and output characteristics, and breakdown voltage are fully characterized. The effect of channel orientation on threshold voltage (V_th), subthreshold swing (SS), hysteresis, and V_br is also studied.

Figure 1 presents a schematic illustration of the process flow for β-Ga₂O₃ FinFET fabrication. First, a ∼2 μm-thick lightly silicon-doped β-Ga₂O₃ film was grown on a (010) Fe-doped semi-insulating substrate by metalorganic chemical vapor deposition (MOCVD).^28,29 The doping concentration is around 4 × 10¹⁷ cm⁻³. Then, channel and source/drain regions were defined through lithography followed by 30 nm Pt deposition by ebeam evaporation (Fig. 1). After a standard liftoff process, the samples were immersed into a MacEtch solution consisting of a mixture of 49% HF and K₂S₂O₈,²⁷ to form fin-shaped channels and source/drain mesas (Fig. 1). Subsequently, the Pt was removed by aqua regia followed by 25 nm/20 nm Ti/Au films deposition with ebeam evaporation for source and drain contact. 20 nm of Al₂O₃ was then deposited through the atomic layer deposition (ALD) process, followed by 1 min of 490 °C rapid thermal annealing (RTA) with N₂ ambient to improve interface quality between Al₂O₃ and β-Ga₂O₃.³⁰ After the removal of Al₂O₃ on top of the source/drain mesa by HF, 25 nm/20 nm Ti/Au gold gate electrodes were then deposited on the high-k layer to form the gate stack. Finally, 1 min of 480 °C RTA under N₂ ambient was applied for source/drain Ohmic contact formation.

A trapezoid-like fin shape channel was first formed using the MacEtch process.²⁶ Figures 2(a) and 2(b) show the tilted-view and focused ion beam (FIB) cut cross section SEM images of a fully fabricated β-Ga₂O₃ FinFET. Note that the source/drain mesa height of 3.57 μm is larger than the thickness of the epitaxial n-type β-Ga₂O₃ film (2 μm), suggesting the fin channel consists of both the n-Ga₂O₃ epitaxial layer and the semi-insulating substrate. This divides the structure into two parts: a much wider triangular part at the bottom [highlighted in red, Fig. 2(b)] and a narrow fin on top (highlighted in blue). Due to the nature of the carrier transport process in MacEtch,^{25,27,31–33} β-Ga₂O₃ MacEtch is also found to be dependent on the doping concentration.³⁴ Therefore, the sharp transition line on the sidewall is indictive of the interface between the top n-Ga₂O₃ layer and the semi-insulating substrate. The active n-channel of the device is 142/570 nm in top/bottom width and ∼1.5 μm in height, leading to an aspect ratio of 4.2:1 using the average fin width [Fig. 2(b)]. Moreover, a smooth sidewall morphology can be observed on the MacEtch-formed structures (Fig. S1) compared to the rough sidewall produced by typical RIE processes. Note that the 1.5 μm fin height is smaller than the epitaxial n-Ga₂O₃ thickness (2 μm), suggesting the top parts of fins might be removed in the MacEtch process due to side etching.

Figure 3(a) shows the DC transfer characteristics of the MacEtch-formed β-Ga₂O₃ FinFETs with a 1 μm gate length (L_G) and 630 nm top fin width (W_fin,top) under V_ds = 5 V. At V_gs = 4 V, the drive current reaches 2.7 × 10⁻⁵ A/fin or 26.7 mA/mm when normalized to the bottom width of the active fin channels [blue region in Fig. 2(b)]. The on/off ratio is ∼10⁵ with gate leakage current at the 100 pA level, suggesting that a gate stack with good control and low leakage is formed. DC transfer characteristics of β-Ga₂O₃ FinFETs with different fin widths are shown in Fig. 3(b). With L_G = 1 μm and V_ds = 10 V, V_th values are found to be highly dependent on the fin dimension, causing the FinFETs to shift from the depletion mode (normally on) to the enhancement mode (normally off) as the fin width decreases. As expected, a more negative gate bias is required to deplete the channel and turn off the device with increasing fin width. The V_th dependence on fin width also provides a general guideline to design transistor operation mode depending on the applications. In addition to V_th, SS is extracted to be 93.6, 84.5, and 89.9 mV/dec. for 550, 330, and 200 nm W_fin,top, respectively. With $SS=kTqln10·(1+CD+q·DitCox)$⁠,³⁵ where C_D, D_it, and C_ox are the depletion capacitance, interface trap density, and oxide capacitance, respectively, the upper bond of D_it in the MacEtch-formed β-Ga₂O₃ FinFETs is estimated to be around 1.4 × 10¹² cm⁻² eV⁻¹, which is not far from the CV measurement results of MacEtch-formed vertical MOSCAPs.²⁶ This indicates that the MacEtch process does not damage the surface and has created an interface with superior D_it between Al₂O₃ and β-Ga₂O₃.

Note that all the transfer characteristics showed almost zero hysteresis [ΔV_th between voltage sweeps 1 and 2, as shown in Fig. 3(a)], which is unprecedented for β-Ga₂O₃ FETs with vertical sidewall structures. The largest hysteresis is only 9.7 mV clockwise, which is dramatically reduced compared to the 120–800 mV hysteresis of previously reported β-Ga₂O₃ FETs.^14,18,36,37 This nearly hysteresis-free characteristic could be attributed to the absence of RIE-induced ion damages and traps due to the MacEtch nature and is consistent with the CV results of MacEtch-formed β-Ga₂O₃ MOSCAPs.²⁶ 

Figure 4(a) shows the linear transfer characteristics at V_ds = 5 V for the β-Ga₂O₃ FinFET. The output characteristics with L_G = 1 μm and W_fin,top = 630 nm are shown in Fig. 4(b). At V_gs = 2 and V_ds = 10 V, a 24.4 mA/mm drain current is achieved. On resistance (R_on) can be extracted from the slope of the low V_ds region. With the fin width extracted from the cross section SEM images [blue region in Fig. 2(b)], the R_on is estimated to be around 128.8 Ω mm at V_gs = 2 V. Thus, the R_on,sp is around 6.5 mΩ cm² when normalized to the distance between source and drain (5 μm). If we consider the source/drain contact transfer length (L_T) as 1 μm, the R_on,sp = R_on × gate width (W_g) × (L_SD+2L_T) can be extracted as 9.1 mΩ cm². Note that since the carrier concentration at source/drain is only from the intrinsic doping during the MOCVD growth (∼4 × 10¹⁷ cm⁻³), the 1 μm transfer length could be an overestimation. As a result, the 9.1 mΩ cm² of R_on,sp when considering L_T might also be overestimated. On the other hand, the R_on,sp is expected to be further reduced though additional ion implantation to increase source/drain doping concentration, leading to a decreased contact resistivity and parasitic source/drain resistance.

With the asymmetric crystal structure of β-Ga₂O₃, it has also been reported that the channel orientation affects the β-Ga₂O₃ transistor characteristics.¹⁸ The DC transfer characteristics of β-Ga₂O₃ FinFETs with ∼750 nm W_fin,top and different channel orientations are shown in Fig. 5(a). At V_ds = 10 V and V_ov = ∼5 V, the drain currents are ∼2 × 10⁻⁵, 2.3 × 10⁻⁵, and 1.9 × 10⁻⁵ A for θ = 60°, 85°, and 90°, respectively. This shows all the drive current saturates at a similar level and suggests the channel mobility does not vary much with the orientation. Nonetheless, a clear voltage shift of the I_d-V_gs curves can be observed as the channel orientation changes. To further analyze this shift, the V_th of β-Ga₂O₃ FinFETs with similar W_fin,top (∼750 nm) and different channel orientations are extracted and plotted in Fig. 5(b). When θ, the angle between the channel direction and [102], is 60° [Fig. 5(b)], a −0.9 V V_th is observed. Then, the V_th becomes more negative as the fin rotates away from the [102] direction and reaches its minimum at −6.9 V when the channel is counterclockwise 90° from [102] direction. As the angle becomes larger than 90°, the V_th starts to increase again as the channel is more aligned with [102]. This V-shaped V_th distribution has also been reported in (001) β-Ga₂O₃ vertical transistors¹⁸ and could be attributed to two reasons: first, as shown in our previous work,²⁶ the fin sidewalls become more vertical as the fin orientation approaching 90° from [102]. This leads to a wider channel width and, thus, a more negative bias to deplete the channel. Therefore, a most negative V_th at 90° is expected. On the other hand, the interface trap quantity on the sidewalls has also been reported to vary with the fin orientation.²⁶ As a result, this V_th trend might also imply that the interface traps on sidewalls decrease as the channel getting more perpendicular to the [102] direction, and the sidewalls have the lowest interface trap density and negative interface charges, leading to the lowest V_th. It is also likely that these two factors both contribute to this V_th variation.

To further analyze the impact of these sidewall interface trap densities on the transistor performance, the SS of β-Ga₂O₃ FinFETs with different channel orientations is also extracted [Fig. 5(b)]. SS decreases as the channel orientation rotates away from [102] and reaches its minimum value of 87.2 mV/dec. at θ = 90°. Like the V_th, the SS vs fin orientation also shows a V-shaped distribution. The SS can be modeled as $SS=kTqln10·(1+CD+q·DitCox)$⁠,³⁵ where C_D, D_it, and C_ox are the depletion capacitance, interface trap density, and oxide capacitance, respectively. Accordingly, the V-shaped distribution of SS suggests that the interface trap density could be the lowest on the MacEtch-formed sidewalls when θ = 90°, consistent with the previous observation on V_th.

In addition to SS, the hysteresis of I_d-V_gs curves also reflects the device and interface quality of β-Ga₂O₃ FinFETs. Thus, we have examined the hysteresis for MacEtch-formed devices with different orientations. As shown in Fig. 6(a), the hysteresis vs θ also demonstrates a similar V-shaped distribution with the minimum hysteresis (24 mV) at θ = 90° [Fig. 6(a)]. It was reported that the interface quality (i.e., D_it) had a direct impact on the hysteresis of the RIE-fabricated β-Ga₂O₃ FETs.³⁸ Therefore, this V-shape hysteresis might imply that sidewalls have the lowest D_it when the channel is perpendicular to the [102] direction, in agreement with the previous results on V_th and SS.

Figure 6(b) shows the high-voltage off-state characterization of the β-Ga₂O₃ FinFETs [the same device as shown in Figs. 3(a) and 4]. A negative V_gs bias is applied to keep the device at off state. The gate and drain current remain low, at the detection limit of the tool, until breakdown at ∼370 V, where a spike in drain and gate current is observed. By assuming a one-dimensional electrical field distribution (E = V_gd/L_GD), the electric field under the gate is estimated to be ∼1.4 MV/cm when the breakdown occurs, which is smaller than the theoretical breakdown field of β-Ga₂O₃.³⁹ However, this simplified one-dimensional distribution is inaccurate for the FinFET structure. The simulated results show that a significantly higher local electrical field occurs at the corner of the fin structure.⁴⁰ This could cause the breakdown to happen at a lower voltage compared to the theoretical value. As a result, a greater breakdown voltage should be achieved in the future by incorporating field plate structures into the FinFETs.^18,37

Figure 7(a) shows the average breakdown voltage of the FinFETs with different channel orientations. The V_br is within the range of 365–380 V and does not vary much with different θ, suggesting that the interface properties might not play an important role in the breakdown mechanism. Figure 7(b) shows the benchmark chart of reported β-Ga₂O₃ transistors in the literature. Note that the R_on,sp values plotted are extracted from the slope for the family of curves at the low V_ds region under V_ov = ∼5 V for all cited works. Then, the R_on,sp is normalized to the area W_g×(L_SD + 2 L_T) and plotted in Fig. 7(b). For those works not reporting L_T, a 1 μm L_T is assumed for the calculation (raw data found in the cited work are plotted in Fig. S2 in the supplementary material). We believe this would provide a better reference point for benchmarking, since originally reported R_on,sp in different papers is extracted with quite different V_ov (ranging from 3 to 100 V). An alternative version of benchmarking with originally reported R_on,sp is also provided in Fig. S2. Here, the MacEtch-formed β-Ga₂O₃ FinFET demonstrates a reasonable 370 V breakdown voltage and a 9.1 mΩ cm² R_on,sp, which is relatively low compared to other reported β-Ga₂O₃ transistors. With the nearly zero hysteresis and comparable device performance, we believe this work represents a step toward three-dimensional β-Ga₂O₃-based power electronics with high quality interface.

In summary, β-Ga₂O₃ FinFETs, produced by MacEtch with channels of good aspect ratios and smooth sidewalls, are demonstrated. The devices show near hysteresis-free I_d–V_gs characteristics, presumably because of the absence of ion-induced damage, inherent to the MacEtch process. A 6.5 mΩ cm² specific on-resistance and a 370 V breakdown voltage are achieved. The effect of channel orientation on V_th, SS, hysteresis, and breakdown voltages is also analyzed. The results suggest the sidewalls possess the lowest interface trap density when the channel is perpendicular to the [102] direction and best suited for FinFETs.

See the supplementary material for details: Figs. S1 and S2 show the zoomed-in SEM image of the FinFET sidewall and the R_on,sp raw data found in literature before normalization, respectively.

This material is based upon work supported in part by the National Science Foundation under Grant Nos. 1809946 and 1810041.