This work reports the quantification of rise in channel temperature due to self-heating in two-terminal SrSnO3 thin film devices under electrical bias. Using pulsed current–voltage (I–V) measurements, thermal resistances of the thin films were determined by extracting the relationship between the channel temperature and the dissipated power. For a 26-nm-thick n-doped SrSnO3 channel with an area of 200 μm2, a thermal resistance of 260.1 ± 24.5 K mm/W was obtained. For a modest dissipated power of 0.5 W/mm, the channel temperature rose to ∼176 °C, a value which increases further at higher power levels. Electro-thermal simulations were performed which showed close agreement between the simulated and experimental I–V characteristics both in the absence and presence of self-heating. The work presented is critical for the development of perovskite-based high-power electronic devices.

Perovskite oxides have recently garnered tremendous interest within the electronic device community due to their diverse properties spanning thermoelectricity,1 superconductivity,2 ferroelectricity,3 ferromagnetism,4 piezoelectricity,5 photoconductivity,6 and gas sensitivity.7 Stannate perovskite oxides are shown to have light carrier effective masses due to the presence of a dispersive conduction band arising from Sn-5s states and have minimal interaction between electrons and phonons.8–10 This results in high mobility values,8,11,12 which, in combination with other desirable properties such as wide bandgap,13 the ability to form diverse heterostructures,14,15 ease of ferroelectric integration,16 and both p- and n-type dopability,17 has increased the interest in realizing high-performance devices using the stannate perovskites. Among the stannates, BaSnO3 (BSO) and SrSnO3 (SSO) are the two most widely studied materials for electronic devices. Both BSO and SSO have shown promising results in the form of high transconductance metal–semiconductor field effect transistors (MESFETs),18,19 radio frequency (RF) FETs,20 heterostructure metal–oxide–semiconductor FETs (MOSFETs),14,21 deep-ultraviolet-transparent thin-film transistors,22 and thermally stable p–n junctions.17 For high-power applications, SSO has several advantages over BSO due to its larger bandgap of 4.1 eV compared to BSO (3.1 eV) making SSO fall into the category of ultra-wide bandgap (UWBG) materials.10 Hence, SSO based devices can potentially have higher breakdown voltage, transparency out to shorter wavelengths, and perform better in extreme environments.13 Furthermore, SSO is also more closely lattice matched with many substrates23 used commonly for growing molecular beam epitaxy (MBE) films, and this property can lead to a variety of heterostructure devices with better interfaces and reduced defects. Improved interfaces can lead to devices with lower thermal boundary resistances and formation of heterostructure devices with minimal interfacial defects.24 

Despite this promise, the performance of devices based upon SSO for high-power applications could be limited due to self-heating effects owing to its relatively low thermal conductivity value of 4 W/m K.25 Similar limitations have been observed in other UWBG materials. For instance, Singh et al.26 showed that intensified self-heating and elevated channel temperatures due to low thermal conductivity of β-Ga2O3 can reduce the RF performance of MOSFETs. The reduction in performance is mainly due to degradation in the mobility of the semiconductor at elevated temperatures. This rise in channel temperature can be as high as a few hundreds of degrees and can cause numerous additional problems such as reduced breakdown voltage, increased leakage, and even mechanical failure due to thermal stresses. Therefore, for SSO, it is of utmost importance to determine the rise in channel temperature under electrical bias such that appropriate methods can be developed to minimize self-heating. Quantification of rise in channel temperature can also prove useful in determining the time constants associated with heat-induced reliability issues. For instance, in complementary metal–oxide–semiconductor (CMOS) circuits, excessive self-heating is known to accelerate the probability of metallization failure (calculated in terms of time-to-failure) due to electromigration and decrease the time-to-breakdown of gate oxides.27 

Several attempts have been made to determine the channel temperature of devices made from other thermally resistive wide bandgap semiconductors28,29 using optical techniques such as Raman spectroscopy and infrared thermography. However, optical techniques have limitations in terms of channel geometry and dimensions due to the limited spot size of the incident beam. The incident beam from the light source can also penetrate into the substrate and can cause internal reflections within the transparent layers, thereby preventing accurate measurement of the surface temperature. Modeling and simulation attempts have been performed to determine the self-heating-induced rise in channel temperature;30 however, such results are laden with several assumptions about boundary conditions and material parameters. These parameters have high dependence on thermal stress, channel temperatures, and heat distribution which are not yet studied properly for SSO.

In this work, we use an all-electrical method based on pulsed current–voltage (I–V) measurements to determine the rise in channel temperature of two-terminal devices fabricated on SSO thin films. So far, no experimental results on the rise in channel temperature as a result of bias-induced current flow have been reported in the literature. Thermal resistances of these thin-film SSO devices were then determined by understanding the relationship between the dissipated power and the channel temperature. It was found that for a moderate amount (0.5 W/mm) of dissipated power that the channel temperature can reach up to 176 °C, and this rise in temperature can increase further with an increase in dissipated power. Electro-thermal simulations using Synopsys SentaurusTM Technology Computer Aided Design (TCAD) were further performed to simulate I–V curves under the influence of self-heating effects which displayed consistent behavior with the experimental results. A heat map (spatial temperature distribution) of the SSO channel under bias was also simulated. This study is crucial for understanding how self-heating can affect the electrical transport in ultra-wide bandgap SSO which can prove pivotal in development of high-power devices with improved thermal management. Moreover, the results presented in this work are an initial step toward the understanding of thermal effects in high-mobility perovskite oxide devices. We note that two-terminal devices were purposefully used for this study to simplify the self-heating experiment. For instance, MESFETs have gate metal on the channel that can act as an additional heat sink which can complicate the analysis. Furthermore, in FETs, heating can be asymmetric between source and drain due to the non-uniform field distribution. While analysis on these more complex FET structures will ultimately be needed, initial studies using the simpler two-terminal device structure are a necessary step in understanding the self-heating behavior.

The samples used for this analysis were grown by hybrid MBE31,32 on insulating GdScO3 (GSO) substrates. The film stack consisted of 26-nm-thick neodymium-doped SSO with a carrier concentration of 2 × 1019 cm−3 on top of an 11-nm-thick undoped SSO layer. Photolithography was used to pattern mesa isolated regions which were formed by using Ar plasma-based ion-milling. Photolithography was again used to pattern resist openings for contact deposition. Contacts were formed by electron-beam evaporation of Ti (75 nm)/Au (100 nm) followed by an acetone liftoff procedure. The as-fabricated two-terminal transfer length method (TLM) structures (Fig. S1) were then subject to rapid thermal annealing in an Ar/H2 environment for 5 min at 300 °C to minimize the contact resistance.33 The contact spacing was 4 μm and the device width was 50 μm. Figure 1 contains the schematic of the fabricated device used for studying self-heating effects. We note that the two-terminal device was one component of a larger TLM test structure fabricated at the same time as a device run.19 Several other two-terminal devices were also fabricated using different film thicknesses and channel dimensions, and the complete information for these devices is provided in Table S1 of the supplementary material.

FIG. 1.

Infographic describing the experimental process flow of the all-electrical method used to determine self-heating-induced rise in channel temperature of thin-film SSO devices. For both calibration and measurement steps, pulse width and duty cycle of 400 ns and 0.04% were used, respectively. In the calibration step, chuck temperature (= channel temperature) is varied, while in the measurement step chuck temperature is kept constant.

FIG. 1.

Infographic describing the experimental process flow of the all-electrical method used to determine self-heating-induced rise in channel temperature of thin-film SSO devices. For both calibration and measurement steps, pulse width and duty cycle of 400 ns and 0.04% were used, respectively. In the calibration step, chuck temperature (= channel temperature) is varied, while in the measurement step chuck temperature is kept constant.

Close modal

Pulsed I–V characterization of two-terminal devices was performed using a Keysight B1530A waveform generator/fast measurement unit (WGFMU). Measuring I–V characteristics using sub-microsecond pulses is essential for devices that are prone to self-heating, as narrow pulses with small duty cycles ensure that the bias on the device is applied for minimal time, thus ensuring the channel temperature does not increase. Figure S2 shows the effect of increase in pulse width on the I–V characteristics of a thick-SSO-channel device. With the increase in the pulse width from 200 ns to 100 μs, the peak current drops down from 89.8 to 55.5 A/mm. This drop at large pulse widths is caused by Joule heating which lowers mobility and decreases the overall current. In all self-heating measurements reported here, a pulse width of 400 ns was used. While this pulse width can lead to some degree of self-heating at high current levels, the results from Fig. S2 show that, at current levels below ∼50 A/mm, no significant self-heating occurs.

To determine the thermal resistance of the device, an all-electrical method34 (Fig. 1) was used consisting of two steps: (i) a calibration step and (ii) a measurement step. The purpose of the calibration step is to collect temperature-dependent pulsed I–V data without self-heating effects. This is accomplished by minimizing the pulse width (400 ns) and duty cycle (0.04%) and also by maintaining the quiescent voltage, VQ, which is the voltage applied between pulses, at zero. The quiescent power dissipation in the channel, PQ, can then be estimated by calculating the product of VQ and the quiescent current, IQ. Since VQ = 0, PQ= VQ× IQ = 0 as well, thus ensuring the temperature of the channel is unaffected by self-heating. The channel temperature, Tchannel (in °C) when PQ = 0, can then be assumed to be the same as that of the chuck. To ensure that the thermal resistances present between the chuck/substrate or between the substrate/SSO layer do not cause the channel surface temperature to be different from chuck temperature, before performing I–V measurements, the sample was kept at one particular temperature for 30–45 min.

Figure 2(a) shows the temperature-dependent pulsed I–V characteristics for PQ = 0 at different chuck temperatures. The figure clearly shows that with increasing chuck temperature, the current drops. This drop in current is due to reduced electron mobility at higher temperature, which is a consequence of direct heat conduction from the chuck to the channel. From the pulsed I–V data, the on-resistance, Ron, is extracted from the slope of the linear region of the pulsed I–V curve, along with the maximum current, Imax, for different channel temperatures as depicted in Fig. 2(b). By performing a linear fit, the following equations relating channel temperature with Ron and Imax were determined from the calibration step:

Ron(Ωmm)=(0.0315 ± 0.0019)Tchannel+25.69 ± 0.17,
(1)
ImaxmA/mm=0.2208 ± 0.0189Tchannel+194.42 ± 1.70.
(2)
FIG. 2.

Results for calibration (a) and (b) and measurement (c) and (d) steps. (a) Temperature-dependent pulsed I–V characteristics performed at quiescent voltage, VQ of 0 V. Inset shows schematic of pulses used for this step. (b) Ron and Imax values obtained from (a) plotted for different values of channel temperature. Here, since dissipated power, PQ = 0, channel temperature = chuck temperature. (c) Pulsed I–V characteristics performed for different quiescent voltages at a fixed chuck temperature of 27 °C. Inset shows schematic of pulses used for this step. (d) Ron and Imax values obtained from (c) plotted for different values of dissipated power. We note that the voltage on the x-axis of (a) and (c) is the voltage applied between contact pads 1 and 2 in Fig. 1. The current, resistance, and power values shown in all plots are normalized to the width (50 μm) of the channel.

FIG. 2.

Results for calibration (a) and (b) and measurement (c) and (d) steps. (a) Temperature-dependent pulsed I–V characteristics performed at quiescent voltage, VQ of 0 V. Inset shows schematic of pulses used for this step. (b) Ron and Imax values obtained from (a) plotted for different values of channel temperature. Here, since dissipated power, PQ = 0, channel temperature = chuck temperature. (c) Pulsed I–V characteristics performed for different quiescent voltages at a fixed chuck temperature of 27 °C. Inset shows schematic of pulses used for this step. (d) Ron and Imax values obtained from (c) plotted for different values of dissipated power. We note that the voltage on the x-axis of (a) and (c) is the voltage applied between contact pads 1 and 2 in Fig. 1. The current, resistance, and power values shown in all plots are normalized to the width (50 μm) of the channel.

Close modal

A contact resistance of ∼4 Ω mm was determined using TLM test structures. The metal–semiconductor contact does have a temperature dependence as shown in Ref. 33. However, this is unlikely to affect the validity of our analysis, since the calibration step does not require any particular temperature-dependent effect to be dominant, only that the device displays a consistent change in behavior with temperature. This is a major advantage of the all-electrical method as it allows the measurement of channel temperature with ease without the need of evaluating the different physical phenomena of current degradation/enhancement. For instance, it was shown in Ref. 34 that the presence of other current degrading effects, such as charge trapping, do not affect the thermal resistance values obtained from the all-electrical method.

The purpose of the measurement step is to incorporate self-heating in the device by using a non-zero value of VQ, for pulsed I–V characteristics, while keeping the chuck temperature constant. A constant chuck temperature ensured that the temperature rise in the channel was mainly because of self-heating. Figure 2(c) shows the pulsed I–V characteristics of the device by varying VQ from 0 to 5 V, at a constant chuck temperature of 27 °C. With increasing VQ, the power dissipation increases, resulting in self-heating, with a corresponding drop in current due to lower mobility. We also note that the time periods associated with the different scattering mechanisms that lead to self-heating are orders of magnitude smaller than time period separating the pulses used in this study. Thus, after each pulse, there is enough time for the heat to distribute uniformly. To prevent degradation from excessive heating, VQ was restricted to 5 V. Once again, from the pulsed I–V curves, Ron and Imax were recorded in Fig. 2(d) for different dissipated power values. By performing a linear fit, the following equations relating power dissipation with Ron and Imax were determined from the measurement step:

Ron(Ωmm)=(8.02 ± 0.14)P+26.24 ± 0.39,
(3)
Imax(mA/mm)=(58.58 ± 1.33)P+187.37 ± 0.49.
(4)

In Fig. 2(d), at higher power, the curves deviate slightly from their linear behavior. This could be due to the dependence of thermal conductivity on channel temperature. Similar observations were seen in other thermally resistive semiconductors such as GaN,34 AlGaN/GaN,35 and Ga2O3.28 

Finally, by combining Eqs. (1)–(4), two sets of relationships between channel temperature and power can be obtained from either the Ron and Imax values:

Tchannel(°C)=(255.008 ± 20.215)P+17.55 ± 19.08,
(5)
Tchannel(°C)=(265.272 ± 28.786)P+31.90 ± 7.14,
(6)

where Eq. (5) was obtained by solving Eqs. (1) and (3), and Eq. (6) was obtained by solving Eqs. (2) and (4).

Figure 3 shows the Tchannel vs P plot that results from Eqs. (5) and (6). The mean of slopes of Eqs. (5) and (6) gives the average thermal resistance of the SSO device, which is 260.1 ± 24.5 Kmm/W. The thermal resistance value of SSO obtained from this method is actually an effective value which includes the thermal resistance of the doped SSO layer and the boundary resistance present between the undoped SSO layer and the GSO substrate. The results clearly show that both the methods (Ron and Imax) capture the effects of the change in channel current with self-heating. While Ron mainly captures the change in low-field mobility with temperature, Imax captures the loss of current at high fields due to increased scattering. From the different devices we tested (Figs. S3–S6), it is clear that for some devices the Ron criterion provided the best fit, while on others, Imax produced the lowest error. For this reason, we have reported the results for both metrics as a further check as to the accuracy of our results.

FIG. 3.

Extracted channel temperature vs dissipated power obtained by plotting Eqs. (5) and (6). The slope of the plot gives the average thermal resistance of the film. The power value shown on the x-axis is normalized to the width (50 μm) of the channel.

FIG. 3.

Extracted channel temperature vs dissipated power obtained by plotting Eqs. (5) and (6). The slope of the plot gives the average thermal resistance of the film. The power value shown on the x-axis is normalized to the width (50 μm) of the channel.

Close modal

Several other devices with different channel dimensions and thicknesses were also fabricated and analyzed for this self-heating study. The calibration step and measurement step plots similar to Fig. 2 and Tchannel vs P plots for these devices are presented in the supplementary material (Figs. S3–S6). The all-electrical method functioned for all of these devices and the experimental results matched well with the simulated values (as discussed in Table S1), providing evidence that this method is robust for samples with different physical dimensions.

To provide further understanding of the experimental results, electro-thermal TCAD simulations were performed to understand the self-heating effects within the device and cross-validate the rise in channel temperature for a given input power. Sentaurus Structure Editor was used to design the physical structure of the device. The lateral dimensions and film thicknesses were kept the same as those of the actual experimental device, except the substrate thickness in the simulation was limited to a few micrometers rather than the actual value of 0.5 mm used in the experiment, in order to reduce simulation run time. It was ensured that this reduced substrate thickness did not show any different results than the simulation results obtained using the actual substrate thickness. Furthermore, simulations were performed where it was ensured that increasing the thickness of the substrate from the current value of 30 μm did not affect the simulation results, as there was large dissipation of heat via the contacts. The electrical transport was calculated using DC analysis and the initial temperature for all the surfaces (and bulk) was set to room temperature. To calculate self-heating, the lattice temperature under electrical bias was determined and thermal boundary conditions in the form of surface resistances were defined for each surface. The thermal conductivity of SSO used in the simulations was 4 W/m K which is based on the value found in Ref. 25 for a 65-nm-thick Ba1−xSrxSnO3 film with x =1 grown using pulsed laser deposition (PLD). Given that the difference in thermal conductivity observed for films grown using PLD and MBE for other perovskite films is minimal,36 and since there are limited data available for thermal conductivity values of SSO, we used a value of 4 W/m K as the thermal conductivity value of our SSO thin films in our simulations. A thermodynamic model was used to calculate the non-uniform lattice temperature distribution, where the model used a modified diffusion current equation to incorporate the temperature gradient term with the underlying assumption that the lattice temperature is in equilibrium with that of carrier temperature. Partial vacuum was kept as a medium around the physical structure of the device except the bottom surface. Since, the medium did not include particle movement, convection mechanisms of heat dissipation could be safely neglected. More information on the thermodynamic model and thermal equations can be found in Ref. 37. We note that while some discrepancy exists between the shape of the simulated and experimental I–V curves due to the lack of availability of consistent values of various thermal and transport parameters for SSO in the literature, the similar reduction in the current between the self-heating and non-self-heating conditions between simulation and experiment provides good evidence that the thermal conductivity value in the simulation is reasonable. However, additional experimental and theoretical studies are needed to more accurately determine the thermal parameters in SSO.

Figure 4 shows the temperature distribution (along different cross sections) in the channel and body of the as-fabricated device at an input power of 0.27 W/mm. As expected, the rise in temperature occurs mainly in the channel region where the current flows. The cross-sectional view also shows that the high thermal resistance of the substrate results in a high temperature build up at the surface of the channel. The maximum temperature rise occurs at the center of the channel. Across the width of the channel, the gradient is minimal due the absence of heat sinks. However, across the channel length, the contacts on either end help to dissipate heat due to the low thermal resistance offered by the contact pads. In the simulation, the thermal interface resistance (also a boundary condition) of Ti/SSO contact was defined to be 1 × 10−8 m2 K/W, which was based on Pt/Si contact thermal resistance found in Ref. 38. Figure S7 shows the total heat generated in the device structure where it is evident that the proportion of heat generation in the contacts is minimal compared to the channel. Hence, the geometry of the substrate and the thermal boundary conditions on the sides and the bottom were not critically important.39–41 Heat from the contacts is mainly removed via the probe needles which have a significant contact area with the pads resulting in good heat transfer. The rise in temperature of the channel in the simulation is in agreement with the Tchannel vs P plot shown in Fig. 3, demonstrating the accurate dependence of rise in channel temperature with respect to the change in dissipated power.

FIG. 4.

Thermal simulations performed for the SSO thin film device using Sentaurus TCAD. (a) Spatial temperature distribution in the device bulk at dissipated power of 0.27 W/mm. (b) Cross section showing temperature distribution in the x–y plane. (c) and (d) Temperature vs position curve (c) along and (d) across the top surface of the x–z plane.

FIG. 4.

Thermal simulations performed for the SSO thin film device using Sentaurus TCAD. (a) Spatial temperature distribution in the device bulk at dissipated power of 0.27 W/mm. (b) Cross section showing temperature distribution in the x–y plane. (c) and (d) Temperature vs position curve (c) along and (d) across the top surface of the x–z plane.

Close modal

To further demonstrate the accuracy of the TCAD simulations, I–V curves were simulated with and without self-heating and then compared with the experimental results. A list of the simulation parameters is provided in Table S2. Figure 5(a) shows a good overlap between the simulated and experimental curves when self-heating was not present in the device. When self-heating was turned on (by using the thermodynamic model in the TCAD simulation input deck), we observe the fall in overall current and the rise in Ron of the device. As shown in Fig. 5(b), once again, the simulated curve with self-heating shows close overlap with the experimental data. The simulated I–V plots also show close agreement with the experimental data for a thick-SSO-channel device as shown in Fig. S8. Table S1 provides a summary of the experimental and simulated results for all the different devices used for the self-heating study. The rise in channel temperature for a fixed dissipated power from experimental and simulated results have a close agreement with each other for all the devices having different channel dimensions. These results further show that as the channel area is reduced, the thermal resistance also decreases, as shown in Fig. S9. Narrow devices dissipate heat along all the three dimensions (length, width, and depth) of the channel thus resulting in more heat dissipation compared to wider devices which can dissipate heat essentially only along the length and depth of the channel. In narrower devices, along the width of the devices, a temperature gradient exists which is non-existent in wider devices, thus resulting in a higher thermal resistance for wider devices.

FIG. 5.

Comparison of experimental (black squares) and simulated (red circles) I–V characteristics in the (a) absence and (b) presence of self-heating. The experimental curve shown in (a) is the same as the I–V curve shown for 27 °C in Fig. 2(a). The experimental current values shown in both plots are normalized to the width (50 μm) of the channel.

FIG. 5.

Comparison of experimental (black squares) and simulated (red circles) I–V characteristics in the (a) absence and (b) presence of self-heating. The experimental curve shown in (a) is the same as the I–V curve shown for 27 °C in Fig. 2(a). The experimental current values shown in both plots are normalized to the width (50 μm) of the channel.

Close modal

In conclusion, we have quantified self-heating effects in SSO, an emerging high-mobility, ultra-wide-gap perovskite oxide semiconductor. Using a two-step pulsed I–V technique with short sub-microsecond pulse widths, the thermal resistance of SSO thin films grown by hybrid MBE were determined. A thin-film device of 26-nm channel thickness and a channel surface area of 200 μm2 was characterized using this technique, which showed thermal resistance of 260.1 ± 24.5 K-mm/W and rise in channel temperature up to 176 °C at a dissipated power of 0.5 W/mm. TCAD simulations were used to cross-validate these experimental results, where electro-thermal simulations showed that the rise in channel temperature vs dissipated power was in close agreement with the experimental values. Given the tremendous potential of SSO for realizing multi-functional high-power electronics, these results are extremely important for understanding thermal effects in this emerging class of perovskites and for developing potential mitigation strategies to minimize performance degradation at high power levels.

See the supplementary material for sample information, pulse width dependence of I–V characteristics, self-heating characterization plots for additional devices, TCAD simulation parameters, total heat generation in a thin SSO sample, electro-thermal simulation for thick SSO sample, and area dependence of thermal resistance of thin SSO samples.

The work was primarily supported by the Air Force Office of Scientific Research (AFOSR) through Award No. FA9550-19-1-0245. T.K.T. acknowledges the support from the AFOSR through Award No. FA9550-21-1-0025. This work was supported partially by the National Science Foundation (NSF) through Award No. DMR-1741801. C.N.S. and U.S. were supported by NSF under Award No. ECCS-2019749 and by the II-VI Foundation Block Gift Program. Portions of this work were carried out at the Minnesota Nano Center, which receive support from NSF through the National Nanotechnology Coordinated Infrastructure (NNCI) under Award No. ECCS-2025124. Parts of this work also were carried out at the Characterization Facility, University of Minnesota, which receives partial support from NSF through the MRSEC program under Award No. DMR-2011401.

The authors have no conflicts to disclose.

Prafful Golani: Conceptualization (lead); Data curation (lead); Formal analysis (lead); Investigation (lead); Methodology (lead); Resources (equal); Writing – original draft (lead); Writing – review & editing (equal). Chinmoy Nath Saha: Data curation (supporting); Methodology (supporting); Writing – review & editing (supporting). Prakash P. Sundaram: Conceptualization (equal). Fengdeng Liu: Data curation (supporting); Resources (equal); Writing – review & editing (supporting). Tristan Truttmann: Data curation (supporting); Resources (equal); Writing – review & editing (supporting). V. R. Saran Kumar Chaganti: Data curation (supporting); Writing – review & editing (supporting). Bharat Jalan: Funding acquisition (equal); Resources (equal); Writing – original draft (equal); Writing – review & editing (equal). Uttam Singisetti: Data curation (supporting); Funding acquisition (supporting); Writing – review & editing (supporting). Steven J. Koester: Conceptualization (lead); Formal analysis (equal); Funding acquisition (lead); Investigation (equal); Methodology (equal); Project administration (equal); Resources (equal); Supervision (lead); Validation (equal); Visualization (equal); Writing – original draft (lead); Writing – review & editing (lead).

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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Supplementary Material