In this Letter, we experimentally investigate the impact of gate geometry on forward operation of Schottky-gate p-GaN high electron mobility transistors (HEMTs). In particular, we analyze devices with changing gate-metal/p-GaN junction area and p-GaN/AlGaN/GaN heterostructure area in the linear regime. These devices exhibit unique threshold voltage and subthreshold swing scaling dependence with gate geometry that is in contrast with classic field-effect transistors. On the other hand, peak transconductance and ON resistance are found to scale classically. We find that these results arise from the fact that with a Schottky contact to the p-GaN layer, under steady-state conditions, the p-GaN layer voltage is set by current continuity across the gate stack. Furthermore, a detailed scaling study of the gate current reveals that current flow across the p-GaN/AlGaN/GaN heterostructure is not uniform—instead, it preferentially flows through the ungated portion of the p-GaN layer. Our study concludes that in Schottky-type p-GaN gate HEMTs, the respective areas of two junctions constitute an additional design degree of freedom to fine-tune device performance.

In recent years, there has been growing focus on enhancement-mode GaN high electron mobility transistors (HEMTs) for power electronic applications. Among several possible designs, inserting a p-doped GaN layer in the gate stack of an AlGaN/GaN HEMT has been found to be particularly promising. p-GaN HEMTs, as they are commonly known, are rapidly attracting commercial interest for power management applications due to simpler circuit design and inherently safe operation that stems from their positive threshold voltage, while preserving the efficiency and high performance associated with the AlGaN/GaN heterostructure.1–4 

In p-GaN HEMTs, the gate metal/p-GaN junction can either be designed to be an Ohmic contact or a Schottky junction depending on material choices and processing conditions. In the case of an Ohmic gate contact, in what is known as a gate injection transistor (GIT), the gate voltage needs to be kept within a narrow range or large gate leakage current flows with undesirable consequences.3 On the other hand, a Schottky junction acts as a reverse biased diode when the device is turned on, substantially limiting the gate leakage current. Therefore, growing emphasis is being placed on Schottky-gated p-GaN transistors for power applications.

In a Schottky-type p-GaN HEMT, the gate stack consists of two diodes in a back-to-back configuration: the metal-gate/p-GaN Schottky junction and the p-GaN/AlGaN/GaN heterostructure, which acts as a p–i–n diode.5–7 In consequence, the p-GaN layer is electrically floating leading to complex and hard to model gate operation. In this transistor structure, a design degree of freedom is the relative area of the two junctions in the gate stack. It has been found that to limit leakage through the p-GaN sidewall as well as to improve gate reliability, a portion of the p-GaN layer must be left uncontacted by the gate metal.8–11 However, the broader impact of changing the relative areas of the two junctions on device operation is not well understood. Addressing this void is the goal of this work.

In this Letter, we study p-GaN HEMTs with different gate geometries. We find unusual dependences of device figures of merit—threshold voltage and subthreshold swing—on gate geometry. These dependences are consistent with gate electrostatics, which are determined by a current continuity requirement across the gate stack rather than by a capacitive divider. An additional factor in the impact of gate geometry is an anomalous scaling of the gate current with the length of the uncontacted portion of the p-GaN layer. Our results should be instrumental in developing a deeper understanding of p-GaN HEMT device physics, reliability, and the construction of device models for circuit design.

A schematic cross section of the studied devices is shown in Fig. 1(a), and an energy band diagram at VGS = 0 V across the intrinsic gate stack is depicted in Fig. 1(b). These devices are pre-production prototype p-GaN-gated HEMTs grown on a Si substrate. Devices with different gate dimensions are studied. The source to p-GaN edge distance, LS, the drain to p-GaN edge distance, LD, and the width of the device, W, are identical across all devices. The length of the gate-metal/p-GaN junction, LSBD, and the length of the p-GaN/AlGaN junction, LPIN, are varied across devices, where LPIN is always greater than LSBD. We define the length of the uncontacted portion of the p-GaN layer, Loffset = LPIN − LSBD. This offset is split evenly on either side of the gate metal. Devices with LSBD from 0.7 to 10 μm and Loffset from 0.4 to 1.9 μm in 0.3 μm steps are studied. These devices represent an area ratio between the two junctions from nearly 1 to 3.7.

FIG. 1.

(a) Schematic cross section of devices studied here. All dimensions are fixed across devices except LSBD, LPIN, and therefore, Loffset = LPIN-LSBD. (b) Band diagram at VGS = 0 V across the gate stack.

FIG. 1.

(a) Schematic cross section of devices studied here. All dimensions are fixed across devices except LSBD, LPIN, and therefore, Loffset = LPIN-LSBD. (b) Band diagram at VGS = 0 V across the gate stack.

Close modal

The drain current, ID, from linear-regime transfer sweeps (VDS = 50 mV) for devices with the same LSBD = 0.7 μm but changing LPIN is shown in Fig. 2(a). There is a clear positive shift in the threshold voltage, Vt, as LPIN increases. For a uniform definition across devices with widely different gate dimensions, we define Vt as the value of VGS for which the product of ID and the channel length, LPIN, are constant and equal to 10−8 A × mm. This corresponds to a channel density on the order of 109 cm−2. Figure 2(b) shows Vt defined this way as a function of LPIN with LSBD as a parameter. A remarkable geometrical dependence is observed whereby for a constant LSBD, Vt rapidly shifts positive as LPIN increases. The change of Vt with LPIN is fairly similar across devices with different LSBD. This is all unlike ideal metal-oxide-semiconductor field-effect transistors (MOSFET), where in the absence of short channel effects, Vt should be largely independent of LPIN. This puzzling gate geometry dependence is also shown as a function of the ratio of the two junctions in Fig. 2(c) and Loffset in Fig. 2(d) and discussed in detail below.

FIG. 2.

(a) Transfer sweep with VDS= 50 mV for devices with LSBD = 0.7 μm and different values of LPIN. As LPIN increases, the curves shift positive. (b) Vt extracted at ID × LPIN = 10–8 A × mm for all devices studied vs LPIN. (c) Vt in (b) plotted instead vs LPIN/LSBD. No universal ratio dependence arises. (d) Vt vs offset length, Loffset.

FIG. 2.

(a) Transfer sweep with VDS= 50 mV for devices with LSBD = 0.7 μm and different values of LPIN. As LPIN increases, the curves shift positive. (b) Vt extracted at ID × LPIN = 10–8 A × mm for all devices studied vs LPIN. (c) Vt in (b) plotted instead vs LPIN/LSBD. No universal ratio dependence arises. (d) Vt vs offset length, Loffset.

Close modal

Figure 3(a) shows the subthreshold swing (SS) at the same bias point of Vt for all devices. In an ideal MOSFET without short-channel effects, SS is independent of the gate geometry. In contrast to this, in our devices, we also find a pronounced geometrical dependence. For constant LSBD, SS decreases quickly as LPIN increases. This dependence is, however, not monotonous: the value of SS depends not only on LPIN but also on LSBD, something that is not expected. This is all inconsistent with normal FET behavior.

FIG. 3.

(a) Subthreshold swing (SS) vs LPIN at Vt for all devices. (b) Peak transconductance (gm,peak) in the linear regime for all devices. (c) ON-resistance (Ron) defined at VGS = 7 V and VDS  0.1 V. Extracted RSD = 12.4 Ω.

FIG. 3.

(a) Subthreshold swing (SS) vs LPIN at Vt for all devices. (b) Peak transconductance (gm,peak) in the linear regime for all devices. (c) ON-resistance (Ron) defined at VGS = 7 V and VDS  0.1 V. Extracted RSD = 12.4 Ω.

Close modal

These observations around threshold are in interesting contrast with the electrical characteristics for the same devices in the ON regime, that is, above threshold. Figures 3(b) and 3(c) show the evolution of the linear regime peak transconductance, gm,peak, and ON-resistance, Ron, respectively, for all transistors. These data reveal classic transistor scaling behavior, where gm,peak goes as 1/LPIN and Ron is linear on LPIN, just as expected.12 

Our study of gate geometry scaling of transistor electrical characteristics reveals an interesting behavior. While the linear-regime peak transconductance and ON-resistance, extracted above threshold, follow classical transistor scaling, the threshold and subthreshold figures of merit feature geometrical dependences with no clear analogues to conventional FETs. What is behind this strange geometrical dependence?

The floating p-GaN node in the back-to-back diode configuration of the gate and an unexpected non-uniform gate current density distribution across the PIN barrier are responsible for the behavior that we observe.

In steady state, the potential at the p-GaN node is established by the need to maintain current continuity across the PIN and SBD junctions.13,14 Under the assumption that the p-GaN layer is thick enough to support a quasi-neutral region between the two barriers, the applied gate-to-channel voltage must be dropped across the SBD and the PIN barriers such that the current flow across the diodes, ISBD, and IPIN, respectively, is equal [Fig. 1(b)]

VGS=VSBD+VPIN,
(1)
IG=ISBD=IPIN.
(2)

Furthermore, the channel density, n2DEG, is controlled by the voltage drop across the p-GaN/AlGaN/GaN heterostructure, VPIN.15,16 An important conclusion of this is that at a constant n2DEG, or ID × LPIN, VPIN is the same across all devices.

This realization explains the Vt dependence on LPIN at fixed LSBD of Fig. 2(b). For constant ID × LPIN and, therefore, constant VPIN, a longer LPIN implies larger IPIN and, therefore, larger ISBD. Since LSBD is fixed and the SBD is reverse biased, this demands a larger VSBD and all together a larger VGS, consistent with experiments.

A consequence of this hypothesis is that for uniform current density across the p-GaN/AlGaN/GaN heterostructure, Vt should depend on the ratio of the two areas, LPIN/LSBD. This is because at constant VPIN, the junction area ratio would determine the required current density across the metal/p-GaN Schottky junction and, therefore, VSBD. Yet, Fig. 2(c) shows no universal trend between Vt and the device LPIN/LSBD ratio. This suggests that the LPIN scaling of IG = IPIN does not follow a simple linear law.

Toward understanding the scaling of IPIN, we examine the IG-VGS characteristics of all devices. Figure 4(a) plots these data for devices with LSBD = 0.7 μm. IG exhibits an unusual geometrical dependence: at a constant LSBD, IG decreases with increasing LPIN, contrary to what one would expect. This apparent anomalous geometrical scaling disappears if we examine IG vs ID × LPIN, as shown in Fig. 4(b). We see here that at a constant ID × LPIN, and therefore, VPIN, IG increases as LPIN increases. This is what is expected. This result further suggests that IG is not set by a p-GaN/passivation sidewall leakage current since this current component should decrease as LPIN increases. Yet, when we extract IG for all devices at a value of ID×LPIN = 10−8 A × mm (corresponding to our choice of Vt), an unusual set of dependencies emerges, as illustrated in Fig. 4(c).

FIG. 4.

(a) IG measured during transfer sweep. (b) IG vs ID × LPIN for LSBD= 0.7 μm. (c) IG at constant ID × LPIN= 10–8 A × mm. (d) Logarithmic slope of IG with respect to ID × LPIN at Vt.

FIG. 4.

(a) IG measured during transfer sweep. (b) IG vs ID × LPIN for LSBD= 0.7 μm. (c) IG at constant ID × LPIN= 10–8 A × mm. (d) Logarithmic slope of IG with respect to ID × LPIN at Vt.

Close modal

Ideal scaling behavior for IG at constant ID × LPIN should be a linear increase with LPIN. This is exactly what is observed in Fig. 4(c) for each value of LSBD. However, IG under the same conditions should not change with LSBD, unlike what we observe. For example, at LPIN = 2.5 μm, devices with LSBD = 0.7 and 2 μm differ in IG by a factor of 4. In fact, the dominant dependence of IG in Fig. 4(c) is on Loffset. For any given LSBD, as Loffset increases, IG increases very quickly.

IG then can be understood as consisting of two components: one that scales roughly linearly with LSBD (green dotted line) and a much larger one that increases with Loffset (brown dotted lines). This can only be interpreted as one component flowing through the contacted (intrinsic) portion of the gate of length LSBD and another much larger component flowing through the uncontacted offset region of the gate. This is a surprising result with a possible origin that is discussed below. With this two-component IPIN, it now becomes clear why Vt does not follow simple junction area ratio scaling. With the IG through the offset region of the gate being much larger than that flowing through the intrinsic portion of the gate, it is the offset current that largely dictates the current density flowing through the Schottky junction and, therefore, VSBD and Vt. The dominant impact of Loffset on Vt is clearly observed in Fig. 2(d).

We now turn our attention to the scaling of the subthreshold swing of Fig. 3(a). Understanding the physics of SS in a device where gate current continuity sets the gate electrostatics requires that we focus on the change of IG as VGS changes. For this, we return to Fig. 4(b) where we plot IG vs ID × LPIN. An observation in this figure is that not only IG but also the slope of IG vs ID × LPIN depend on LPIN: it decreases as LPIN increases. This is more clearly seen for all devices in Fig. 4(d) that plots the unitless slope of log IG vs log (ID × LPIN) at Vt. Here, we clearly see that for a given LSBD, this slope decreases quickly as LPIN increases.

With this observation, we can now understand the gate geometry dependence of SS in Fig. 3(a). SS describes the change in the gate voltage required to produce a certain change in the drain current. As noted above, in the absence of short-channel effects, SS in a MOSFET is independent of lateral gate geometry. This is because the vertical MOS electrostatics are set by a gate oxide/substrate capacitive divider. In our devices with a back-to-back diode configuration in the gate, under quasi-static conditions, the gate electrostatics are instead determined by gate current continuity. As a result, SS is determined by the sum of the change in the voltages across the two junctions that are required to accommodate the IG change necessary to induce a given change in the channel current. As observed in Fig. 4(d), at constant VPIN, longer LPIN devices have smaller relative increase to IG with gradual increase in VPIN. Following gate current continuity, the smaller relative IG change then results in a smaller VSBD change. Thus, longer LPIN devices result in smaller VGS change for gradual increase in VPIN, resulting in a smaller subthreshold swing. This is consistent with the observations in Fig. 3(a). In fact, there is a remarkable mapping among the data sets graphed in Figs. 3(a) and 4(d).

We have explained the unusual gate geometry scaling properties of our Schottky-gate p-GaN HEMTs around threshold in terms of current continuity. A question to be examined is why the device characteristics in the ON regime, Ron and gm,peak, appear to follow ideal MOSFET behavior [Figs. 3(b) and 3(c)]. The difference here is that in an ideal FET in the absence of short-channel effects, Vt and SS are independent of gate geometry while gm,peak and Ron both exhibit inverse-linear and linear, respectively, dependences on the gate length, or LPIN in this case. In the context of this dominant LPIN dependence, an additional LSBD dependence that might emerge from the gate current continuity arguments above is bound to be comparatively minor and easily masked by other factors such as device to device variability.

Our research shows that the role of IG is critical in understanding the gate geometry scaling of our p-GaN HEMTs. As Fig. 4(c) reveals, IG flows preferentially through the uncontacted portion of the PIN barrier. The origin of this is not completely understood, but a possible explanation relies on incomplete Mg activation in this region. During fabrication, Mg dopants are activated through a thermal annealing step that relies on the dissociation of the Mg–H complex.17–19 At this point in the process, the offset is covered by a dielectric while the intrinsic region remains uncovered [Fig. 5(a)]. Dielectric capping of the offset region might prevent H from escaping and in this way hamper Mg activation or further encourage formation of the Mg–H complexes.20 This should result in a lower doping level in the capped region and vulnerability to defect related issues. SIMS measurements in the gate stack further show that Mg is present in the AlGaN barrier. Incomplete Mg activation could then impact the band structure and the leakage current over the barrier in the offset vs intrinsic region of the gate.15,18,21

FIG. 5.

(a) Schematic of the Mg activation process. In the offset regions of the p-GaN layer, incomplete Mg activation is expected. (b) p-GaN TLM resistance vs % dielectric coverage during annealing.

FIG. 5.

(a) Schematic of the Mg activation process. In the offset regions of the p-GaN layer, incomplete Mg activation is expected. (b) p-GaN TLM resistance vs % dielectric coverage during annealing.

Close modal

Toward verifying this hypothesis, we have electrically characterized Schottky-gate/p-GaN transmission-line model (TLM) test structures with various fractions of passivation capping during the Mg activation anneal. These measurements reveal that the greater the p-GaN layer fraction covered during the annealing process, the higher the p-GaN lateral resistance [Fig. 5(b)]. Since the layer resistance is roughly inversely proportional to the hole density, the higher resistance indicates a lower acceptor activation in p-GaN.

Our research reveals a rich gate geometry dependence of the electrical characteristics of Schottky-gate p-GaN HEMTs. We show that the unique scaling behavior of the threshold voltage and the subthreshold swing that we observe arise from the back-to-back diode nature of the gate stack that leaves the p-GaN layer largely floating. Under quasi-static conditions, the voltage drop across the PIN and SBD junctions is set by the need to provide gate current continuity across both junctions. An additional element of relevance to the geometrical dependences observed here is the preferential flow of the gate current across the PIN barrier in the offset or uncontacted portion of the gate. Our study concludes that the lengths of the PIN and SBD junctions provide another degree of freedom for device engineers to design for desired characteristics, further highlighting the benefits of p-GaN gated enhancement-mode technology.

The authors have no conflicts to disclose.

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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