Optimization of LPCVD phosphorous-doped SiGe thin films for CMOS-compatible thermoelectric applications Open Access

Thermoelectric materials are widely used as sensors¹ or energy harvesters² [Seebeck effect: thermopiles or thermoelectric generators (TEGs)] or for heating and cooling, respectively [Peltier effect: thermoelectric coolers (TECs)].^3,4 The dimensionless thermoelectric figure of merit (ZT-value) is defined by

Here, σ describes the electrical conductivity (⁠$ρ=1/σ$ is the specific resistivity), α is the Seebeck coefficient, κ is the thermal conductivity, and T is the absolute temperature. The product $PF=α2σ$ is called power factor (PF) and characterizes the electronic transport properties. As can be seen from Eq. (1), high ZT-values can be achieved for large Seebeck coefficients and low specific resistivity values.⁵ 

The progress in developing thermoelectric materials over the past 30 years is strongly related to the concept of Hicks and Dresselhaus using low dimensionality for increasing α and σ, as well as decreasing κ.^6–8 Since the 1990s, this concept has been expanded in terms of defects, critical phenomena, anharmonicity, and spin degree of freedom to maximize the ZT value for several materials.⁹ Materials such as PbTe,¹⁰ Heusler alloys,¹¹ or SnSe¹² recently showed the highest values at high temperatures but have the disadvantage that none of them are complementary metal–oxide–semiconductor (CMOS)-compatible.

Silicon germanium (SiGe) is continuously subjected to this thermoelectric optimization route and a well-known material in the semiconductor industry, where it is used as the source/drain or channel material in CMOS (complementary metal–oxide–semiconductor) devices.^13,14 Low pressure chemical vapor deposition (LPCVD) SiGe films are also used in solar cells and as the absorption material for bolometer or thermopiles.^15–17 The well-established LPCVD (low pressure chemical vapor deposition) technique is commercially used for SiGe thin film depositions in CMOS facilities^18,19 and is characterized by the advantages of the high thickness and resistivity uniformity, constant doping profile due to in situ doping, and cost reduction made possible by the use of vertical batch furnaces.^20,21 As a CMOS-compatible material, SiGe can be integrated into microelectronics manufacturing lines for thermoelectric approaches in industrial mass production. However, the ZT value improvement has been reported mostly for nanostructured SiGe, such as nanocomposites^22,23 and nanowires,²⁴ because the small structures lead to the reduction in lattice thermal conductivity justified by boundary scattering.

Figure 1 shows the comparison of different nanostructures with phosphorous-doped or undoped SiGe and illustrates the resulting increase in ZT values at 300 K. Each approach shows a clear increase in the ZT value due to nanostructuring compared to the respective bulk reference value (blue bar). Another possibility for optimization is modulation doping, where the separation of the charge carriers from ionized dopants reduces their scattering and, thus, increases the charge carrier mobility.²⁵ The transfer of nanoscale approaches into CMOS environments is a challenge in uniformity control and integration. However, optimizing the so-called power factor (⁠$PF=α2σ$⁠) by varying the doping concentration is another route to improve the thermoelectric performance.²⁶ 

In this work, we investigate the influence of gas flow parameters on the material and thermoelectric properties of phosphorous-doped SiGe thin films with different compositions. We show that by varying the process gas flows, in addition to the stoichiometry, α and σ change over a large range as a result of doping variation.²⁶ Finally, we discuss different CMOS-compatible thermoelectric application scenarios like infrared sensors, Peltier cooling, or energy harvesting.

All samples were deposited on 300 mm Si wafers with 100 nm thermally grown silicon oxide, which acts as an insulation layer. In situ doped SiGe films were grown using the LPCVD technique in a vertical batch reactor A412 (ASM). Silane (SiH₄), germane (GeH₄) as well as phosphine (PH₃) in helium (He) for doping were used as gaseous deposition sources. All 300 mm wafer samples received a rapid thermal annealing (RTA) for charge carriers activation and damage repair after deposition (Helios XP Mattson system).²⁷ 

Spectroscopic ellipsometry FX100 (KLA Tencor) was used for determining the thickness with an relative uncertainty of 1% and uniformity of the whole 300 mm wafers. To analyze the crystallographic phase composition, we employed grazing incidence x-ray diffraction (GI-XRD) and used the Bruker Discover D8 tool with Cu K_α source at a grazing angle of 0.5. The measured data were identified by standard reference patterns supplied by the International Center for Diffraction Data (ICDD). The stoichiometry of all samples is analyzed by x-ray photoelectron spectroscopy (XPS) using PHI Quantes Scanning Microprobe (Physical Electronics GmbH, MN, USA) apparatus with Al K_α radiation. For quantification, the relative sensitivity factors (RSFs) of each element were used. These RSFs (based on the standard sensitivity factor developed by Wagner) are obtained from the MultiPak software developed by Physical Electronics (PHI) and already corrected for the x-ray source angle for geometric asymmetry effects and the transmission function of the spectrometer.²⁸ The Si, Ge, and P concentrations were calculated using the areas under the elemental peaks after Shirley background subtraction and using the extracted RSFs of each element. The root mean square (RMS) roughness of all samples was determined by means of atomic force microscopy (AFM) with a Cypher, AsylumResearch, Oxford Instruments tool and was analyzed with the Gwyddion software.

Both the Seebeck coefficient α and the sheet resistance $R◻$ were measured with an home-built measurement setup. A LabVIEW programmed software automatically controlled measurement and recording of the thermovoltages at individually defined temperature set points. The average temperatures were set automatically to 40 °C at a constant temperature difference $ΔT$ of 5 K. The Seebeck coefficients were calculated by means of the inversion method to eliminate the offset voltage influence.²⁹ To increase statistical accuracy, each sample was measured three times, and the mean value was formed. The estimated uncertainty for α is 10% and for the resistivity 7%.

Unless otherwise described, specimen pieces were broken from the half-radius area of the wafer for the following investigations. Table I gives an overview of all varied relative gas flow process parameters and the corresponding influences on the stoichiometry, thickness uniformity and RMS roughness of the samples.

The deposition of phosphorous-doped SiGe layers is influenced by various adsorption and desorption processes on the substrate surface during pyrolysis of the gaseous precursors SiH₄, GeH₄, and PH₃. For samples #1–6, only the PH₃ flow was changed, while for samples #7–9 only the SiH₄ and GeH₄ flow was changed. The decrease in the PH₃ flow of samples #1–6 minimizes the absolute P concentration only for samples #1–3, while the Si concentration increases. In contrast, the Ge content remains relatively constant. By reducing the GeH₄ flow, not only the Ge but also the P concentration is reduced as could be observed for samples #7 and 8. On the other hand, in sample #9, the reduction in the SiH₄ flow not only increases the Ge concentration but also significantly increases the P incorporation. The larger the GeH₄ flow and resulting Ge concentration, the better the P is incorporated. It is assumed that a high phosphine concentration leads to the adsorption of PH₃ on silicon surfaces and, after the desorption of hydrogen, a formation of P₂ dimers takes place on the substrate surface, which prevents the adsorption of further hydrides and favors the incorporation of P. Significantly lower PH₃ flows (samples #3–6) increase the relative GeH₄ content and prevent the formation of P₂ dimers. There is a uniform incorporation of P in SiGe, whereby the phosphine concentration no longer has a significant effect on the absolute P concentration.³⁰ However, the electrical conductivity of samples 3–6 drops significantly [cf. Fig. 7(a)], which indicates a reduction in the active charge carrier concentration.

The thickness uniformity represents the coefficient of variation in %. A high uniformity value implies a high inhomogeneity in the layer thickness across the 300 mm wafer. The highest inhomogeneity can be seen for sample #1 with the highest PH₃ flow and sample #9 with the lowest SiH₄ flow. Figure 2 illustrates the very good thickness uniformity of sample #1. Only sample #9 shows a significant increase in RMS while the small thickness uniformity of sample #1 does not affect its RMS value.

Figure 3 shows the deposition rates depending on the film thickness of all samples from Table I. The deposition rate increases with decreasing PH₃ flow and shows the typical flattening of the curve for CVD processes when thicker layers are reached.^21,30 With higher PH₃ flow, the PH₃ partial pressure rises in the reactor and leads to a gas phase decomposition of PH₃ and what limits the SiH₄ adsorption and prevents the monatomic encapsulation of P in the crystal lattice.³⁰ A decrease in the GeH₄ flow also causes a decrease in the deposition rate (samples #7 and 8).

Figure 4 shows the x-ray diffraction patterns and due to clear and distinct reflexes confirming the good crystallinity of all samples. The intensity peaks refer to the lattice planes (111), (220), (311), (400), (331), and (422) as expected for SiGe.^20,31 The hkl-values indicate the corresponding sample pattern and represent a cubic crystal system with the space group Fd-3m. The vertical black line at a 2Θ angle of 28.2 shows a drift of the reflex pattern from samples #7–8 (Si₉₀Ge₅P₅-black line, Si₅₇Ge₁₃P₃₀-pink line) in the direction of larger 2Θ angles, while samples #1 and 2 (Si₆₀Ge₁₂P₂₈-dark blue line, Si₆₈Ge₁₀P₂₂-orange line) shift slightly toward smaller 2Θ values. In the case of either a very large or very small P concentration, a drift can be seen in the reflex pattern. The shift in sample 9 and sample 8 can presumably be attributed to the significant change in the gas flow parameters, which in addition to the change in the stoichiometric ratios also leads to a change in the film strees.^32,33

From the TEM images in Fig. 5, we can see a polycrystalline structure with small grain sizes that are in the AFM grain size range of 40–210 nm. Figure 5(b) shows smaller grain sizes compared to the AFM data, which is known from other work.²² Surface topography measurements of all samples are performed by AFM, where selection is depicted in Fig. 6. The samples exhibit small grain structures ranging in the nanometer range with a roughened surface. In particular, sample #9 [Fig. 6(c)] shows a clearly different structure in comparison to the others, which is confirmed by the high RMS value caused by the variation of gas flow. Due to the insufficient thickness uniformity and high roughness, the processes of samples #1 and 9 are not sufficient for industrial applicability. A grain size distribution of all samples between 40 and 210 nm was determined on the basis of 30 manual measured grains. In contrast, the remaining samples show a homogeneously structured surface such as sample #3 (Si₇₂Ge₁₀P₁₈). Also the determined RMS roughness (cf. Table I) in combination with the good uniformity proves the beneficial applicability for CMOS devices.

Figure 7 shows the measured Seebeck coefficient α, electrical conductivity σ, and calculated power factor PF of all nine samples dependent on the applied mean temperature (T_av) of 40 °C. The cross marked data points represent the Seebeck coefficient data, and the circle marked graphs the electrical conductivity. It can be seen from samples #1–6 that α increases and σ decreases with a decreasing PH₃ flow. Interestingly, in samples #3–6, the P concentration is constant despite a strong reduction in PH₃ flow. From this, it has to be concluded that the decreasing conductivity σ for these samples is caused by a decrease in the active charge carrier concentration. Sample #3 (Si₇₂Ge₁₀P₁₈) with a medium PH₃ flow as well as #8 (Si₉₀Ge₅P₅) with the lowest Ge and P concentrations show the greatest PF. In the case of sample #3, this can be explained by the opposite trend of α and σ or reciprocal ρ, which inevitably reach a maximum in the product of PF. A decrease in the Ge content in sample #8 leads to an increase in the conductivity and, finally, to the enhancement of PF. Otherwise, it is well known³⁴ that the higher Ge content inhibits the P activation and leads to the decrease in σ and decrease in PF sample #9.

In our investigations, we also looked to see if there is a correlation between thermoelectric properties (Fig. 7) and roughness RMS or thickness uniformity (Table I). However, the measurement results did not reveal any significant relationship. To evaluate the potential of our phosphorous-doped SiGe thin films, we have compared the power factor PF with results from previously published results in Table II. These devices were also intended for the usage in thermoelectric generators (TEGs) or infrared sensors. As can be seen from Table II, the highest PF achieved in this work is about twice the size as previous results. It is also worth mentioning that, compared to silicon, SiGe provides a higher efficiency, e.g., in TEGs, through material optimization in the particular CMOS processes.³⁶ 

In this work, we investigate the influence of gas flow process parameters on phosphorous-doped SiGe thin films fabricated under CMOS-compatible conditions in a LPCVD batch reactor. The results show that by optimizing the doping concentration, a maximization of the thermoelectric performance could be achieved. Furthermore, it could be observed that by reducing the GeH₄ flow, the Ge concentration is minimized and the resistance decreases. The fully optimized process with an optimal composition of Si₇₂Ge₁₀P₁₈ reached a power factor PF of 0.52 mW/m K². This value is about twice the size of previously reported results. This proves the promising potential of the used CMOS-compatible fabrication technology for applications on the industrial 300 mm wafer level.

This research was funded by the German Bundesministerium für Wirtschaft (BMWI) and by the State of Saxony in the frame of the Important Project of Common European Interest (IPCEI).