Double injection function InGaZnO transistor—computational analysis of the patterned doping method

Metal oxide semiconductors are part of the next generation of electronic devices.^1–3 One can find metal oxide electronic components in TVs,¹ laptops, mobile phones, and wearable electronics, and recently metal-oxide TFT was suggested as a candidate for flexible CPUs.⁴ Also, the low operation voltage of 1 V has been demonstrated.⁵ As in conventional electronics, size reduction is expected to provide enhanced performance. However, one cannot adopt the solutions developed for the silicon industry and alternative approaches are being developed.^6–9 The Schottky contact TFT architecture, known as the source gated transistor (SGT), has been around for at least 20 years^10–12 and has gained renewed interest. This renewed interest is mainly due to works like Shannon et al.¹³ that brought the context of Schottky contacts to short channel (lateral) transistors, keeping the output conductance low. A comprehensive study of source gated transistors and device optimization guidelines can be found in Ref. 12 and from a somewhat different perspective also in Ref. 14. In short [Fig. 1(a)], the Schottky contact creates a depletion (light blue) below the source, and due to edge effects, this depletion is pronounced at the edge of the source that faces the drain. This extended depletion creates a pinch-off that limits the current supplied for a given gate bias. Thus, the device enters saturation due to the current limit at the source. The comparison between standard and SGT InGaZnO-based transistors¹⁵ is also helpful in completing the picture. As nicely demonstrated in Ref. 15, when the SGT is used to overcome short channel effects, there is a penalty in the ON current.

In a recent publication,⁸ we fabricated self-aligned InGaZnO (IGZO) based source controlled TFTs (SCT-TFT) to demonstrate that the penalty in ON current could be circumvented. The concept was to separate the two functions of the source, i.e., of charge injection and depletion [Fig. 1(b)]. We termed this structure “double injection function transistor” (DIFT) and demonstrated its realization using two contact metals [Fig. 1(b)]. The depleting metal is only at the edge facing the drain, while the rest of the source is Ohmic. Namely, to realize DIFT, we used a double work function (DWF) source electrode, where for the IGZO TFTs, we used molybdenum and platinum as Ohmic and Schottky contacts, respectively.⁸ In this different design, the source is not gating the transistor but is only controlling the physical path of the current while screening the effect of the drain bias (field).

This paper investigates the possibility of creating an Ohmic contact through high doping.¹⁶ Although defect control as well as doping is currently still challenging for metal oxides,¹⁷ we believe that it will be part of the device-engineer tool-box just as it has become so for other technologies. We do not presume to suggest an optimum device architecture but rather show that double doping works well as the double work function and take the opportunity to describe its unique operation principle. We are aware that most literature reports are concerned with channel lengths well above a micrometer and that the shortest ones are about L = 360 nm.¹⁵ To test against the toughest conditions in terms of short channel effects, we use L = 200 nm.⁸ 

Figure 1(c) describes schematically the double dope structure where the source metal would form a Schottky contact, and the Ohmic part is established by doping the semiconductor underneath. The light blue rectangle below the edge of the source is the part that was left undoped and, hence, is depleted [similarly to the DWF case in Fig. 1(b)]. Figure 1(d) shows simulation results of such a transistor. Figure 1(d) shows the conduction band energy across the semiconductor layer (V_GS = 15 V). The semiconductor-gate oxide interface is taken as y = 0, and the source–semiconductor interface is, thus, at y = 40 nm. For the energy scale, the work function of the source is used as the reference value (0 eV). The light-blue line, in Fig. 1(d), is a cut at the middle of the depleted region under the source, and the high barrier depletion is seen to extend across the film. The orange line is taken within the doped region. The high doping confines the depletion close to the source interface, allowing for tunneling injection.

To compare the three device architectures shown in Fig. 1, we use the same material's parameters (IGZO) as in our previous paper⁸ and use the same device simulator (i.e., Sentaurus by Synopsis). This, industry standard, simulator solves the drift-diffusion and Poisson equations while ensuring the required boundary conditions. The material's model includes the subgap exponential tail states as well as the Gaussian distribution of oxygen vacancies (Fig. 2 in Ref. 8) Namely, all parameters of materials and interfaces were experimentally verified so as to reproduce a range of IGZO TFT structures.⁸ The gate oxide is 100 nm SiO₂, the channel length is 200 nm, and the semiconductor (IGZO) thickness is 30 nm. The Schottky barrier is 0.75 eV, and the assumed intentional doping is 5 × 10¹⁸ cm⁻³. Note that using the experimentally verified data for IGZO from Ref. 8 implies that the undoped layer is unintentionally doped at ∼10¹⁷ cm⁻³ (oxygen vacancies). Figure 2 shows the computed transfer characteristics, where Figs. 2(a)–2(c) correspond to the structures depicted in Figs. 1(a)–1(c), respectively.

Figures 2(a) and 2(b) present results for a source gated transistor (SGT) and a source controlled (SCT) double injection function transistor (DIFT), respectively. Following our recent report,⁸ the DIFT is implemented using DWF with the length of the Schottky contact being Ls = 200 nm. In Fig. 2(a), we observe the significant advantage of SGT exhibiting saturation at low drain bias and the insensitivity of the saturation point to the gate bias.¹² Comparing to Fig. 2(b), we note the SGT penalty in the ON current, which is several orders of magnitude in the present example. The ability of the DWF-DIFT to retain the high current is a result of spatially separating the charge injection from the source gating.⁸ Figure 2(b) shows that the saturation is not complete or that the curve is not entirely flat. The use of L = 200 nm (≪1μm) makes this task extra difficult and requires fine control of the transistor structure. Such fine control is discussed in Ref. 8, and another example will be discussed in the context of Fig. 4 below.

Figure 2(c) shows the results obtained for the device where the Ohmic part of the source is created by inserting n-type doping at a density of 5 × 10¹⁸ cm⁻³. The length of the undoped (Schottky) region is the same as in Fig. 2(b) (Ls = 200 nm). Since the Ohmic injection is formed through tunneling, one must enable tunneling injection in the Sentaurus device simulator. We note that the results for the DDF-DIFT [Fig. 2(c)] are very similar to those obtained for the DWF-DIFT [Fig. 2(b)]. The effect of the non-ideal contact is more evident close to V_D = 0, and the maximum current is slightly lower. However, overall, the DDF-DIFT approach seems to work just as well as the DWF-DIFT. Figure 2(d) shows the output characteristics for devices with varying semiconductor film thickness (d) and at V_G = 15 V. For thinner films, the depletion at the gate-oxide interface is more pronounced, thus limiting the current to a lower value. The way the curves overlap nicely demonstrates that the device enters saturation due to the current limit at the source. The dashed line is the current of the 20 nm semiconductor film thickness device normalized to the 40 nm thick one. We note that the more substantial current limitation results in a more pronounced saturation.

Having established that the double doping is a valid approach, we describe the mechanisms governing its operation. Figures 3(a) and 3(b) present the current and electric field distributions for V_GS = 15 and V_DS = 2.5 V. X and Y directions are marked on Fig. 3(a), and one should note that the x-y dimensions are not to scale. Figure 3(a) shows the current density distribution with the red being high (10³ A cm⁻²) and the blue being low (1 A cm⁻²) current. The left side (x < 0) is the doped region where, in addition to a thin depletion at the top, the entire film carries current. Approaching the interface with the unintentionally doped layer (at x = 0), we notice current crowding close to the insulator interface. In the Schottky region, the current is restricted to the insulator interface. Figure 3(b) shows the lateral component of the electric field with the colors varying on a log scale (blue implies a high field). The Schottky part of the contact acts as a shield¹⁸ causing the electric field to diminish toward the doped region rapidly. Close to x = 0, the electric field being below 1 V/cm implies that the field has reversed its direction. (We will return to this in the context of Fig. 4.)

To better understand the physical scenario at the transition from doped to undoped region, we plot in Fig. 3(c) vertical line cuts at the vicinity of this interface. The orange line is 20 nm into the doped region [according to Fig. 3(a) this is x = −20 nm). We note the gate-induced charge accumulation at the gate-oxide interface on the left side [pink line, Fig. 3(c)]. In the “bulk” (10–30 nm above the oxide), the electron density reflects the doping density (5 × 10¹⁸ cm⁻³). Close to the source, we note the deep depletion that in Fig. 1(d) modified the conduction band to enable tunneling injection. Moving into the Schottky region, we note that the charge distribution shrinks toward the gate-oxide interface. Only 20 nm into the unintentionally doped layer (cyan line), the charge is confined to a ∼5 nm at the gate oxide interface. In terms of energy level diagram, the orange and cyan lines (x = −20, +20 nm) in Fig. 3(c) correspond to the same line colors in Fig. 1(d) [not that in Fig. 1(d) d = 40 and in Fig. 3(c) it is d = 30 nm].

Figure 4(a) shows the transfer characteristics of transistors having film thicknesses of d = 20, d = 30, and d = 40 nm. The transfer characteristics exhibit three regimes, and we use the light blue (d = 40 nm) curve to highlight them. For V_GS < −2 V, we note a steep rise of the current, which is the signature of subthreshold slope in MOS transistors. (For ideal semiconductors, this would be ∼60 mV/decade.) In standard MOS-FET, the change in slope at about −2 V would mark the charging of the channel (i.e., threshold). However, for the DDF-DIF transistor, the slope variation at about V_GS = −2 V marks the point where the current becomes limited by the source contact. The dark blue part denotes the transition period, and at about V_GS = +3 V, we note an upward slope change. To understand this transition range (−2 to +3 V), we examine Fig. 4(b). Figure 4(b) shows the charge density distribution along a cut taken 10 nm into the doped region [x = −10 nm, see Fig. 3(a) for orientation] and for gate bias between zero and five volts. Up to V_GS = +2 V, the area next to the insulator is in depletion. Only from V_GS = +3 V, we can observe charge accumulation at the insulator interface. Namely, the slope change at about V_GS = +3 V marks the transition from depletion to accumulation and is similar to the threshold for charging the insulator interface under the source. With the aid of the inset of Fig. 4(b), which shows the normalized relevant output characteristics, we find that for the DDF-DIF transistor, the threshold for charging under the source is the point where the transistor starts to exhibit the saturation phenomenon.

Finally, we show that the spatial separation of the charge injection and depletion functions allows the structure's design in more than one way. In Fig. 4(c), we examine the interplay between film thickness (d) and the length of the Schottky region (Ls). For this illustration, we also chose to reduce the oxide thickness to be similar to the semiconductor film thickness. We do that to make the change in the semiconductor film thickness also significant in affecting the distance between the gate and source electrodes. Examining the blue, green, and red curves, we note that for Ls = 100 nm, the device does not reach saturation, while for Ls = 200 nm, we already observe significant saturation. The figure also shows that lengthening the Schottky region, from Ls = 200  to Ls = 300 nm, has a similar effect to reducing the film thickness from d = 30 to d = 20 nm (i.e., the current is slightly reduced, and the curves flatten). Remembering that the Schottky part acts as a spatial filter (barrier) induced by the Schottky contact (Fig. 3), then bringing the depleting-contact closer to the oxide interface has an effect similar to making the depleted region longer. Varying the doping level is another parameter that can be controlled where lower doping will make the current saturate at a lower value (not shown).

In Fig. 4(d), we use the simulations of different transistor parameters [Fig. 4(c)] to link the screening of the drain-induced electric field and the saturation phenomena. Figure 4(d) shows the electric field component in the x-direction (i.e., parallel to the film and close to the insulator interface) as a function of the distance from the interface between the doped and undoped regions. The results are for Schottky lengths of Ls = 100 nm (blue), Ls = 200 nm (green), and Ls = 300 nm (red). The solid lines are for d = 30 nm, and the dashed is for d = 20 nm. The negative peak of each curve is a result of the electric field enhancement at metallic edges, and thus, it marks the position of the edge of the electrode. Comparing the different curves, we note that the blue (Ls = 100 nm) does not show a decay to zero before reaching x = 0. This is in line with the device with Ls = 100 nm not reaching saturation in Fig. 4(c). The inset to Fig. 4(d) is a zoom on the region close to x = 0. We note again that the effect of enhancing Ls to 300 nm is similar to decreasing d to 20 nm.

To conclude, we have presented the double doped function structure, which separates the charge injection function from the charge depletion using patterned doping. We find that such a realization of the DIFT is similar to that of the double work function method studied and experimentally demonstrated in Ref. 8, for InGaZnO based TFTs. With the aid of the detailed semiconductor device simulations, employing IGZO parameters,⁸ we analyzed the operation principle of this transistor structure. The part facing the drain (Schottky part) is responsible for screening the drain-induced electric field to minimize the current that is being pulled by the drain from the doped region. The injection (doped) region, which is “behind” the Schottky region, is responsible for building up an accumulation of high charge density to ensure that the current limit (device saturation) has a relatively high value, which is not limited by the shielding Schottky-contact. We found that separating the injection and depletion (screening) functions could allow a systematic design and optimization of such a structure.

We acknowledge support by the Technion Ollendorff Minerva Center and the Russell Berrie Nanotechnology Institute at the Technion–Israel Institute of Technology.