SnO/β-Ga₂O₃ heterojunction field-effect transistors and vertical p–n diodes

Wide bandgap semiconductors are important materials for high-power device applications. Among them, thermodynamically stable monoclinic β-Ga₂O₃ is promising for cost-effective high-performance devices. The combination of ultra-wide bandgap of 4.5–4.8 eV and the still rather high electron mobility of ∼200 cm²/V s leads to a high breakdown strength of ∼8 MV/cm and low on-resistance, respectively.^1–3 These parameters make the Baliga's Figure of Merit of β-Ga₂O₃ superior to other competing wide bandgap materials, such as SiC or GaN. Several reports have demonstrated the successful realization of unipolar Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs),^4–15 Metal-Semiconductor Field-Effect Transistors (MESFETs),^16,17 or Modulation-doped Field-Effect Transistors (MODFETs)^18–20 showing breakdown voltages up to 8.03 kV¹⁵ and a record average breakdown strength of 5.5 MV/cm.²⁰ Similarly, unipolar Schottky barrier diodes based on β-Ga₂O₃ have shown promising performances^21–23 with breakdown voltages of more than 3 kV²⁴ and a maximum breakdown strength of 5.45 MV/cm.²⁵ However, all these values are still well below the expected theoretical limit of β-Ga₂O₃. In this regard, one major obstacle is the lack of p-type β-Ga₂O₃, which could significantly improve the overall performance by a more optimized trade-off between the on-resistance and the breakdown voltage. A possible solution to overcome this issue is the realization of p–n heterojunctions by integrating n-type β-Ga₂O₃ with other p-type semiconductors. Recently, various reports have demonstrated the high potential of Ga₂O₃-based electronic devices in combination with p-type metal oxides, such as Cu₂O,²⁶ ZnCo₂O_4,²⁷ SnO,²⁸ or NiO.^29–31 For example, p-type NiO allowed the fabrication of heterojunction field-effect transistors (HJ-FETs) and diodes with a power figure of merit (PFOM) of 0.39 and 1.38 GW/cm², respectively, on (010)-oriented β-Ga₂O₃³² emphasizing the tremendous potential of this approach. In addition, a vertical p–n heterojunction diode with a rectification ratio of 2 × 10⁸ at ±1 V and an ideality factor of 1.16 has recently been demonstrated based on p-type SnO on (-201)-oriented β-Ga₂O₃.²⁸ 

In this Letter, we are using the concept of the latter p–n heterojunction to extend our previously demonstrated lateral MOSFETs for power electronic applications based on (100)-oriented β-Ga₂O₃ to SnO/β-Ga₂O₃ HJ-FETs with the same orientation. Although no consensus on an optimum surface orientation of β-Ga₂O₃ for lateral devices has been reached so far, the lowest surface-energy cleavage plane (100) provides certain advantages.³³ In particular, smooth, defect-free films can be epitaxially grown on it without faceting—albeit on offcut substrates to prevent twinning.³³ Smooth films and resulting interfaces reduce surface- and interface roughness scattering, being beneficial for the channel mobility of the device. The surface orientation of β-Ga₂O₃ has been further shown to have an impact on the properties of Schottky or Ohmic contacts² and could consequently influence the pn-heterojunction too. Thus, in a first step, we evaluate the SnO/β-Ga₂O₃ pn-heterojunction in vertical diodes on (100)-oriented β-Ga₂O₃ substrates. Their characteristics are found to be similar to those of previously demonstrated SnO-based heterojunction diodes on (−201)-oriented Ga₂O₃ with similar net donor concentration,²⁸ allowing us to apply the related heterojunction in a lateral HJ-FET. Although the p-type metal oxide SnO possesses a relatively small fundamental bandgap of ∼0.7 eV, we are able to demonstrate a high breakdown strength up to 1.9 MV/cm of the non-field-plated HJ-FET. The advantage of the approach presented herein is that SnO layers with favorable hole transport properties are derived from plasma-assisted molecular beam epitaxy (PAMBE),³⁴ which provides the possibility for the in situ growth of the complete SnO/β-Ga₂O₃ heterojunction structure. (In comparison, the PAMBE growth of NiO yielded highly resistive layers.³⁵) In situ growth allows the formation of a high-quality interface with lowest impurity concentration, which is crucial for the realization of power transistors featuring low dispersion properties.

Following the approach of Ref. 28, vertical p–n heterojunction diodes were fabricated on unintentionally Si-doped n-type, nominally oriented (100) β-Ga₂O₃ substrates with n ∼ 3 × 10¹⁷ cm⁻³ and mobility 118 cm²/V s prepared from Czochralski growth.^36,37 In the PAMBE growth of SnO, Sn was evaporated from a shuttered single filament effusion cell operated at 1175 °C and activated oxygen was provided by passing 0.18  sccm of O₂ through a radio frequency plasma source run at 200 W. The substrate temperature during growth measured by a thermocouple between substrate and heating filament was kept at 350 °C. Further details of the optimized growth parameters have been reported elsewhere.³⁴ X-ray diffraction and Raman spectroscopy are used to structurally investigate the SnO grown layer. Figure S1(a) in the supplementary material shows the result of a symmetric out-of-plane 2Θ-ω diffraction using Cu K_α radiation for deposited SnO on (100) β-Ga₂O₃ and on a reference yttria-stabilized zirconia (YSZ) (100) substrate. The deposited films show a predominant SnO (001) phase with slight peaks indicating a secondary Sn₃O₄ phase, whose presence is corroborated by the Raman spectra shown in Fig. S2 in the supplementary material. The presence of this secondary phase points out the challenges in precisely controlling growth conditions to achieve stoichiometric films in the metastable SnO phase, but has negligible influence on their p-type transport properties.³⁴ In situ thickness measurements on the reference sample using laser reflectometry indicate a total film thickness of 150 nm. Hall measurements in the van der Pauw geometry of the reference SnO layer at room temperature (RT) show a sheet resistance of 37 kΩ/sq with a hole density of 7.2 × 10¹⁸ cm⁻³ (assuming a Hall scattering factor of 1.8) as well as a Hall mobility of 1.5 cm²/V s. In the following, we assume the same hole density in the SnO layer on the Ga₂O₃(100) substrate. For the fabrication of the vertical p–n heterojunction diodes, Ohmic square-shaped Ti/Au (20 nm/100 nm) top contacts were defined on the grown SnO layer using photolithography, electron beam evaporation, and liftoff processing. Next, mesa etching of the SnO layer was carried out to isolate the top contacts using lithographically defined resist masks with an inductively coupled plasma inside a reactive ion etching system (ICP-RIE). Further details of this process, including preparation of the backside Ohmic contact on the Ga₂O₃ wafer before SnO growth, have been described elsewhere.²⁸ 

The HJ-FET fabrication was carried out on a Mg-doped semi-insulating (100) β-Ga₂O₃ substrate prepared from Czochralski growth^36–38 with a miscut angle of 4°, which was homoepitaxially coated with a 200 nm thick Si-doped β-Ga₂O₃ layer by metal–organic chemical vapor deposition. The details of the optimal growth parameters used to grow the films were previously reported elsewhere.^39–41 The layers featured a charge carrier concentration, mobility, and sheet resistance of 8.1 × 10¹⁷ cm⁻³, 100 cm²/V s, and 5  kΩ/sq, respectively, as extracted from Hall measurements. After that, a 50 nm gate recess was etched into the epitaxial layer using BCl₃-based ICP-RIE leaving a 150 nm channel beneath the gate. Inter-device isolation was then carried out by a multiple energy nitrogen implantation. This was followed by the evaporation of the Ti/Au (20 nm/130 nm) Ohmic contacts and subsequent patterning using liftoff processing. The Ohmic contacts were annealed at 470 °C for 1 min. in nitrogen atmosphere resulting in a contact resistance of 1.5 Ω mm for each contact. Then, a 150 nm passivation layer of SiN_x was deposited by plasma-enhanced chemical vapor deposition followed by the opening of the gate trench using SF₆-based plasma etching. Subsequently, 150 nm of SnO was deposited on the whole wafer using PAMBE in the growth run described above that was also used for the diodes and the reference layer. After SnO growth, the Ti/Au (20 nm/130 nm) gate metal was evaporated and patterned by liftoff processing. An additional lithography step was carried out leaving photoresist only atop the gate metallization for protection which allowed the subtractive etching of the SnO layer outside of the gate region by BCl₃-based plasma etching. Then, the devices were again passivated with 500 nm of SiN_x, which was subsequently patterned for reinforcement and interconnection of the device electrodes. A final passivation was carried out by spin-coating a 2.5 μm thick BCB (Cyclotene 4022–35) layer atop, which was structured using photo-lithographic processes and hard-cured at 250 °C for 45 min. in nitrogen atmosphere. All lateral structuring was done by i-line stepper lithography. The transistors featured a fixed gate-to-source distance L_GS of 1 μm as well as a gate length L_G and width W of 700 nm and 250 μm, respectively. A two-dimensional schematic of the device structure is shown in Fig. 1(a). The geometries were verified by transmission electron microscopy (TEM) analysis. Figure 1(b) shows the TEM cross section of the gate topology including the SnO/β-Ga₂O₃ heterojunction of a fully processed HJ-FET. The cross section analysis reveals a slightly larger gate length of about 1 μm due to a prolonged over-etching of the SiN_x trench. Hence, the gate-to-source distance is reduced to approximately 0.8 μm. In addition, a slight misalignment of 280 nm of the Ti/Au gate metallization layer toward the source electrode is visible, which is due to the fact that the alignment precision is significantly reduced when processing wafer sizes smaller than 2 in. Nevertheless, the SiN_x gate trench is still fully covered with the gate metal, which is the essential aspect for the actual device functionality. Furthermore, two metal spikes above the gate metal can be seen, which were formed during the SnO etching. Here, the protective resist coated prior to the etching did not fully cover the gate metal leading to sputtering and redeposition of non-protected Au on the sidewalls of the photoresist, which remains after subsequent liftoff. A self-aligned etching process using a thicker gate metal as the etch mask for etching the SnO layer outside of the gate regions without any additional resist could overcome this issue. Such a process is in development currently. Also, a discontinuity of the SnO film is visible at the gate edge toward the drain side, which might be related to shading effects caused by the SiN_x trench sidewalls during MBE growth. We assume that the realization of slanted SiN_x sidewalls during the gate trench formation as demonstrated previously could enhance the film coverage and prevent void formation.

Typical current–voltage characteristics of the fabricated p–n heterojunction diode device as shown in Fig. 2(a) were obtained using a Keithley 4200 semiconductor analyzer system with the voltage applied to a 80 × 80 μm² contact pad on the SnO and the grounded backside Ohmic contact of the Ga₂O₃ substrate. The fabricated device shows a rectification ratio of 3 × 10⁸ at ±2 V. The red dashed line shows the modeled heterojunction I–V diode characteristics using the Shockley equation,

where I_s is the saturation current, n is the ideality factor, k_B is the Boltzmann constant, q is the elementary charge, V is the applied voltage, T is the temperature, R_p is the parallel resistance, and R_s is the series resistance. An ideality factor of 1.2 is extracted from the diode characteristic. The inset of Fig. 2(a) shows the breakdown behavior of the device with a breakdown voltage of −50 V. A turn-on voltage of ∼1 V was obtained for the device by a linear fit of the forward bias as shown in Fig. S3. From the series resistance determined by the fit, a differential specific on-resistance of 3.6 mΩ cm² was extracted. Figure 2(b) shows the obtained RT capacitance–voltage (C–V) measurements at 100 kHz as well as the C⁻²–V plot. The capacitance of a p–n heterojunction diode is given by

where N_A and N_D are the acceptor and donor concentrations in the SnO and β-Ga₂O₃ layers, respectively; and ε_p, ε_n, and ε₀ are the relative dielectric constants of SnO, β-Ga₂O₃, and the permittivity of vacuum, respectively. A₀, q, and k_B are the area of the junction, electronic charge, and Boltzmann constant, respectively. The dielectric constants ε_p and ε_n of 18.8 for SnO⁴² and 10.2 for Ga₂O₃⁴³ were used for further calculations. The built-in potential V_bi obtained from the linear extrapolation of C⁻² to 0 is 1.2 V, which closely agrees with the obtained turn-on voltage of the device. Assuming that the depletion layer mainly develops within the β-Ga₂O₃ layer due to the significantly higher N_A of SnO compared to N_D of β-Ga₂O₃,²⁸ we estimate the net doping density in β-Ga₂O₃ based on the slope of C⁻²–V as (5.0 ± 0.3)×10¹⁷ cm⁻³. For the breakdown voltage of −50 V, a depletion layer width w_D of 336 nm is calculated, corresponding to an estimated maximum breakdown electric field E_m of 2.9 MV/cm for this SnO/(100)-β-Ga₂O₃ diode. Besides the p-type transport properties of the SnO layer, also the diode properties are robust in slightly off-stoichiometric films as demonstrated in this study. We also obtained SnO films on β-Ga₂O₃(100) and YSZ(100) without any secondary phases as shown in the x-ray diffraction scans and Raman spectra in Figs. S1(b) and S2 of the supplementary material, respectively. In Fig. S4 of the supplementary material, we show that the I–V characteristics for this reported heterojunction are comparable to that of the SnO/β-Ga₂O₃(100) heterojunction fabricated with stoichiometric SnO. All these reported diode characteristics are also similar to our previously demonstrated SnO-based heterojunction diodes on (−201)-oriented Ga₂O₃ with similar net donor concentration,²⁸ hence suggesting no major influence of the Ga₂O₃ surface orientation on the diode and HJ-FET properties. An estimated band alignment diagram for the fabricated p–n heterojunction with a type I band offset is shown in Fig. S5 of the supplementary material, which was calculated with Silvaco Atlas by implementing all relevant material parameters for SnO and β-Ga₂O₃.

Representative output and transfer curves for a SnO/β-Ga₂O₃ HJ-FET with a gate-to-drain distance L_GD of 4 μm are presented in Fig. 3. The device shows an on-resistance (R_ON) of 50 Ω·mm, which was extracted at low V_DS and a maximum drain current of 100 mA/mm at a gate voltage of 0 V. The specific on-resistance R_on,sp is calculated by taking the transfer length L_T for both Ohmic contacts in addition to the source-to-drain distance L_SD into account with R_on,sp = R_on × (L_SD + 2L_T) yielding a value of 3.15 mΩ cm². The transfer curve indicates stable switching properties of the device with an on/off-current ratio of 10⁶. Compared to our previous report on (100) β-Ga₂O₃ MOSFET devices based on Al₂O₃ gate oxide with the same device dimensions,¹¹ we observe a slightly higher off leakage current in the range of 10⁻⁸ A/mm, which is typical for junction field-effect transistors due to the limited reverse current of the pn-diode at the gate. This pn-diode is also the root cause for the significant increase in the gate current in the forward direction at a gate voltage above ∼2 V, which is shown in Fig. S6 of the supplementary material. Nevertheless, the HJ-FET has in turn a much higher threshold voltage of −8 V than the MOSFETs (-14 V) even though the HJ-FET features a three times higher doping concentration of the n-type channel and a gate recess only half as deep. This suggests that such structures could possibly be used to realize normally off devices by further layer optimization and adjustment as achieved in the p-GaN gate technology.⁴⁴ The field-effect mobility (μ_FE) of the JFET device was calculated as 39 cm²/V s by using the following equation:⁴⁵ 

where g_max is the maximum transconductance and L, W, and d are the length, width, and thickness of the channel, respectively. However, it has to be noted that we take a thickness of 200 nm for the calculation into account but one quarter of the transistor channel has a lower thickness of 150 nm due to the recess in the gate region. This means that the calculated field-effect mobility is slightly underestimated. This value is lower than the measured hall mobility of 100 cm²/V s, which can be attributed to nonidealities in the transistor, such as interface scattering or traps at the heterojunction.⁴⁶ This also correlates with the fact that the transfer curve shows a slight anti-clockwise hysteresis and a subthreshold swing of 180 mV/dec indicating an increased trap density in the heterojunction interface. It is expected that the in situ growth of both semiconductor layers in one growth run without breaking the vacuum could lead to high quality interface layers reducing both hysteresis and subthreshold swing as well as improves the field-effect mobility.

Furthermore, a three-terminal off-state breakdown measurement of the SnO/β-Ga₂O₃ HJ-FET was carried out at RT and in ambient air. The gate and drain leakage currents measured at V_G = −12 V are presented in Fig. 4 showing a soft breakdown at 750 V, which is followed by the catastrophic breakdown of the device at 870 V. The soft breakdown is most likely caused by the presence of defects and/or impurities within the active region of the transistor, which leads to the formation of a conduction path between source and drain under high electric fields. Thus, the average breakdown field yields a value of approximately 1.9 MV/cm, which is consistent with our previously achieved results based on β-Ga₂O₃ MOSFET devices.^11,47 The exact origin of this catastrophic breakdown is currently unknown, but investigations are ongoing whether the SnO layer is the root cause. By combining the breakdown voltage V_Br with the already calculated specific on-resistance R_on,sp of 3.15 mΩ cm² a PFOM $VBr2Ron,sp$ of 178 MW/cm² is obtained. Figure 5 presents a performance benchmark of the SnO/β-Ga₂O₃ HJ-FET against some state-of-the-art β-Ga₂O₃-based lateral power transistor devices. It should be noted that V_Br of our HJ-FETs was measured in ambient air in contrast to the recently reported NiO_x/β-Ga₂O₃ HJ-FET devices³² measured in Fluorinert, which might have a significant impact on the measurement results.¹⁵ Although the performance level of the SnO/β-Ga₂O₃ HJ-FET is lower than that of NiO/β-Ga₂O₃ HJ-FET, we believe that an optimization of the heterojunction interface quality by either in situ growth of the semiconductor layers or certain pretreatments prior to SnO deposition will significantly reduce interface traps. This in turn will enhance the field-effect mobility and, therefore, reduce the on-resistance. At the same time, optimizations in the device design, such as slanted SiN_x sidewalls of the gate trench as well as field-plates, will improve the field-distribution inside the device and, thus, enhance breakdown properties. Both approaches are expected to push the performance level closer toward the theoretical limit of β-Ga₂O₃.

In conclusion, we have demonstrated the feasibility of using p-type SnO in combination with (100)-oriented n-type β-Ga₂O₃ for the fabrication of vertical heterojunction diodes and lateral field-effect transistors. Both devices showed reliable switching properties with on/off current ratios >10⁶. The HJ-FET device performance was characterized with an average breakdown strength of 1.9 MV/cm as well as a high PFOM of 178 MW/cm². It is expected that further improvement can be achieved by a more optimized in situ layer growth of the heterostructure, which reduces interface trap sites.

See the supplementary material for XRD out of plane symmetric scan of SnO(001)/β-Ga₂O₃ heterojunctions and reference SnO layers, room temperature bulk sensitive Raman spectra of the SnO layers, linear I–V characteristics of the heterojunction showing the turn-on voltage, estimated band diagram of the SnO(001)/β-Ga₂O₃ heterojunction at thermal equilibrium, and the transfer curve of a SnO(001)/β-Ga₂O₃ HJ-FET at gate voltages above +2 V.

The authors would like to thank the cleanroom staff at Ferdinand-Braun-Institut and Paul-Drude-Institut for technological support of this investigation. This work was performed in the framework of GraFOx, a Leibniz-ScienceCampus partially funded by the Leibniz association. Furthermore, this work was funded by the Federal Ministry of Education and Research in Germany within the frame of the joint research project OXIKON, Funding No. 03VP03711, as well as within the Research Project GoNext, Funding No. 16ES1084K.