Cryogenic operation of complementary metal oxide semiconductor (CMOS) silicon transistors is crucial for quantum information science, but it brings deviations from standard transistor operation. Here, we report on sharp current jumps and stable hysteretic loops in the drain current as a function of gate voltage VG for both n- and p-type commercial-foundry 180-nm-process CMOS transistors when operated at voltages exceeding 1.3 V at cryogenic temperatures. The physical mechanism responsible for the device bistability is impact ionization charging of the transistor body, which leads to effective back-gating of the inversion channel. This mechanism is verified by independent measurements of the body potential. The hysteretic loops, which have a >107 ratio of high to low drain current states at the same VG, can be used for a compact capacitorless single-transistor memory at cryogenic temperatures with long retention times.

There is currently a great interest in cryogenic operation of complementary metal oxide semiconductor (CMOS) circuits for quantum information science and quantum computing — where CMOS devices are expected to provide the control and readout circuitry for solid-state sensors and qubits operated at ultra-low dilution refrigerator temperatures.1,2 These applications require operating CMOS transistors either in the sub-100 mK regime or near 4.2 K, depending on the design architecture. Since the required circuits are typically relatively small, for reasons of cost and foundry availability, they are often designed in legacy bulk sub-0.25 μm technologies. As a result, several groups have studied submicrometer CMOS transistor operation at cryogenic temperatures,3,4 investigating such figures of merit as the subthreshold slope (SS), which becomes sharper, and the current drive ION, which becomes higher due to improved mobility. These studies have also noted deviations from standard transistor curves, such as current jumps and hysteresis caused by physical phenomena like incomplete dopant activation or impact ionization (II) currents. Much of the focus has been on developing cryogenic models compatible with simulation software that could accurately capture the changes caused by new physical mechanisms at low temperatures.3–5 However, these deviations from standard characteristics can also confer potentially useful device functionality.

In this Letter, we report on bistability and hysteretic loops that appear in the current-voltage characteristics ID(VG) of foundry-fabricated, 180-nm-process CMOS transistors operated at low temperatures T < 30 K. These effects appear when the transistors are operated at drain voltages VD sufficient to initiate impact ionization (II) at the drain (all terminal voltages are referred to the grounded source). The hysteretic loop can be magnified by leaving the substrate contact floating or connected to an ultra-high input impedance electrometer, which makes it possible to measure the body potential VB during the ID(VG) sweep. Once VB is created by the small nanoampere-scale II current, it persists when VG is scanned back to zero, resulting in a stable, repeatable hysteretic loop. This behavior can be used for a one-transistor (1 T) capacitorless memory with a long retention time (on the scale of minutes at T ≅ 3 K).

While the exact process parameters for the foundry-made CMOS are not available, the transistors were made in a single-poly twin-well process with an SiO2-based gate dielectric. The transistors were wire-bonded, and their electrical properties were characterized in a variable-temperature cryostat capable of base T ≅ 3 K (as measured by using a calibrated resistor mounted in place of the sample). The I(VD,VG,VB) characteristics were measured using the source-measure units (SMUs) of a commercial parameter analyzer. However, when measuring VB in the floating substrate configuration, an electrometer with >1014 Ω input impedance was used, to avoid providing a current path to ground. A schematic diagram of the NMOS transistor is shown in Fig. 1(a), including the choice of substrate connections; the corresponding PMOS would have the substrate and contact doping polarities reversed. The II current, which becomes significant when the inversion channel has formed (VG > VT) and VD is large enough to accelerate carriers to sufficient energy for electron-hole pair creation, is also illustrated. In the case of the NMOS transistors, the II-created electrons would flow to the drain and contribute to ID, but the holes charge up the body, eventually flowing to ground via either the body contact, leading to a measurable IB if the body contact is monitored with a parameter analyzer SMU, or the forward-biased source-body np junction, if the body contact is floating or connected to the high-impedance electrometer.

FIG. 1.

(a) Schematic diagram of the transistor and measurement set-up. The substrate contact is either a low-impedance signal measurement unit (SMU) that captures the body current IB or an ultra-high input impedance electrometer that measures the body potential VB; (b) NMOS ID(VG) characteristics at VB = 0 for VD = 0.1 and 1 V (T = 300 K) and VD = 1 V (T = 77 and ≅3 K). The dashed line shows ID(VG) at VD = 1 V and T ≅ 3 K, but for VB = 0.5 V; (c) subthreshold slope (SS) vs T extracted from the 5–500 pA ID range. The device size is LG/W = 1.44/10 μm.

FIG. 1.

(a) Schematic diagram of the transistor and measurement set-up. The substrate contact is either a low-impedance signal measurement unit (SMU) that captures the body current IB or an ultra-high input impedance electrometer that measures the body potential VB; (b) NMOS ID(VG) characteristics at VB = 0 for VD = 0.1 and 1 V (T = 300 K) and VD = 1 V (T = 77 and ≅3 K). The dashed line shows ID(VG) at VD = 1 V and T ≅ 3 K, but for VB = 0.5 V; (c) subthreshold slope (SS) vs T extracted from the 5–500 pA ID range. The device size is LG/W = 1.44/10 μm.

Close modal

The ID(VG) characteristics of a long-channel NMOS with a gate length LG = 1.44 μm and width W = 10 μm measured at T = 300 K (VD = 0.1 and 1 V), 77, and 3 K (VD = 1 V only) with the substrate grounded (VB = 0) are shown in Fig. 1(b). At room temperature, the transistor characteristics are standard, with the SS ≅ 80 mV. As T is lowered, the switching becomes sharper, ID increases slightly for the same gate overdrive because of higher mobility, and VT shifts to higher values. The decrease in the SS slows below T ≅ 40 K, as illustrated in the evolution of the SS extracted from the 5 to 500 pA range of ID in Fig. 1(c). As seen in other studies of low-T CMOS, the SS ceases to be proportional to kT at cryogenic temperatures because of surface state and band-tailing effects.3,4,6,7 In our case, the SS saturates at ≅13 mV/decade, which is typical for SiO2-based gate dielectric CMOS and actually somewhat steeper than what has been seen in more modern high-k dielectric/metal gate nodes.8 Finally, as expected for an NMOS transistor, a positive VB = 0.5 V shifts VT to lower values, as shown by the dashed line in Fig. 1(b), which corresponds to the ID(VG) of the same transistor at T ≅ 3 K and VD = 1 V. The VB-lowered VT increases ID by orders of magnitude in the subthreshold regime for a given VG < VT.

Standard ID(VG) characteristics for the same device at higher VD = 1.3, 1.5, and 1.7 V, measured with the substrate grounded through the parameter analyzer SMU, are shown in Fig. 2(a). Once VD exceeds 1.3 V, the transfer curve exhibits sharp current jumps and a bistable characteristic when VG is swept up to 1.8 V (the prescribed maximum power supply voltage for this technology) and then down. The physical explanation of this effect dates back three decades.9–11 At low T, the resistance of the p-well becomes large due to carrier freeze out. The II-created holes produce a significant positive body potential VB (note that VB is limited to ∼1 V by the turn-on of the forward-biased source-body junction). This VB, in turn, lowers the VT of the transistor, leading to an increase in ID, analogous to a directly applied VB, as illustrated in Fig. 1(b). In turn, the increase in ID leads to more II and a higher VB. The resulting positive feedback produces an extremely sharp current jump slightly above the ID turn-on threshold at ≅0.46 V. When the VG is swept down from a high value, the body is already charged, so the ID does not drop until the lower VB-influenced threshold is reached. The simultaneously measured IB traces corresponding to the ID(VG) sweeps at constant VD are shown in Fig. 2(b). The II-hole current is tiny relative to ID, peaking at ≈5 nA for the VD = 1.7 V sweep, but, due to the very high body resistance RB at cryogenic T, it creates a large substrate voltage VB. It should be emphasized that RB depends not only on the temperature but also on the current and the details of the substrate doping, and it is, therefore, very challenging to model accurately.4,12

FIG. 2.

(a) NMOS ID(VG) for VD = 1.3, 1.5, and 1.7 V at T ≅ 3 K and VB = 0, showing current jumps and hysteresis developing for VD > 1.3 V; (b) corresponding IB for VD = 1.3, 1.5, and 1.7 V, measured by using the SMU substrate contact. Note that even at VD = 1.7 V, impact ionization IB remains < 10 nA.

FIG. 2.

(a) NMOS ID(VG) for VD = 1.3, 1.5, and 1.7 V at T ≅ 3 K and VB = 0, showing current jumps and hysteresis developing for VD > 1.3 V; (b) corresponding IB for VD = 1.3, 1.5, and 1.7 V, measured by using the SMU substrate contact. Note that even at VD = 1.7 V, impact ionization IB remains < 10 nA.

Close modal

A larger and better-controlled hysteretic loop is obtained either by leaving the substrate contact floating or attaching it to an electrometer with ultra-high (>1014 Ω) input impedance — these two measurement schemes produce identical characteristics, but the latter makes it possible to measure VB independently. The ID(VG) characteristics for VD = 1.2, 1.4, and 1.7 V are shown in Fig. 3(a), measured at a slow scan rate of ≈0.1 V/minute to probe steady-state behavior. For the two higher values of VD, we observe sharp current jumps and hysteretic loops > 0.2 V wide, with the ratio of the high-state current to the low-current states exceeding 107 at VG = 0.3 V, near the middle of the bistable loop. The corresponding VB(VG) traces, measured with the electrometer, are shown in Fig. 3(b). At VD = 1.2 V, we find that VB remains low throughout. But as soon as VD exceeds the II threshold, we observe a sharp jump in VB to ≅1.07 V at the same VG value (≅0.48 V) that produces the current jump in Fig. 3(a). The subsequent behavior of VB, as determined by the evacuation of II-induced hole charge via the source-body np junction, is shown in Fig. 3(b). Using the VD = 1.7 V curve as an example, we see that VB decays slightly, down to 0.91 V, as VG is increased to the maximum value of 1.8 V, consistent with somewhat reduced II current due to electron mobility reduction at high vertical fields at large VG.13 When the VG is swept back, VB goes through the same 1.07 V value at VG = 0.48 V and increases slightly to 1.17 V at VG = 0.15 V and then drops – but not to zero. Rather, VB remains at ≅0.75 V as VG returns to zero, and this memory effect is quite persistent in time. Figure 3(c) shows the time evolution of the body voltage VB, charged by scanning VG up to 0.8 V and back down to zero at VD = 1.7 V, and then measured for 105 s at VD = 1.7 and VG = 0. The evolution of VB is well described by an exponential decay with a time constant on the order of 13 min over the first 5000 s (the time constant is ≈795 s, with R2 = 0.999) down to a very slowly decreasing VB ≅ 0.25 V background—the longer-term evolution of VB out to 5 × 104 s is shown in the inset. The decay of VB is not strongly dependent on VD: a similar VB retention measurement at VD = 0.1 V yielded a slightly shorter time constant of ≈755 s, which is reasonable since the drain-body junction is also forward-biased at low VD, providing an additional channel for discharging VB. As a result, while a memory utilizing this effect cannot be truly termed nonvolatile, on the scale of the anticipated duration of quantum computation a memory that keeps its state for minutes would not require refreshing. We also note that gate leakage IG would provide another path to discharging VB, but it was negligible in all of our devices at cryogenic temperatures. To fully discharge VB, it suffices to momentarily ground the substrate contact, which was done immediately prior to the start of each measurement to obtain the ID(VG) curves in Fig. 3(a) and the corresponding VB(VG) curves in Fig. 3(b) for different constant VD values.

FIG. 3.

(a) NMOS ID(VG) for VD = 1.2, 1.4, and 1.7 V at T ≅ 3 K with substrate connected to the electrometer (no IB due to >1014 Ω input impedance); (b) corresponding VB(VG) showing the complex evolution of the body potential, note that for large VD, VB remains finite as VG is swept down to zero; (c) evolution of VB after the body is charged, with the device maintained at VG = 0 and VD = 1.7 V, at T ≅ 3 K. The decay of VB is exponential with a time constant of 795 s. Inset shows the longer-term behavior of VB out to 5 × 104 s.

FIG. 3.

(a) NMOS ID(VG) for VD = 1.2, 1.4, and 1.7 V at T ≅ 3 K with substrate connected to the electrometer (no IB due to >1014 Ω input impedance); (b) corresponding VB(VG) showing the complex evolution of the body potential, note that for large VD, VB remains finite as VG is swept down to zero; (c) evolution of VB after the body is charged, with the device maintained at VG = 0 and VD = 1.7 V, at T ≅ 3 K. The decay of VB is exponential with a time constant of 795 s. Inset shows the longer-term behavior of VB out to 5 × 104 s.

Close modal

The data in Fig. 3 confirm that this bulk CMOS transistor is suitable as a capacitorless 1 T memory at cryogenic temperatures. It is quite similar to capacitorless 1T-DRAM-like memories fabricated in silicon-on-insulator devices for room-temperature operation, where the body potential was used to store the two memory states, and the resulting VT shift was used to readout the memory.14–16 The key difference is that here the memory is based on a standard bulk CMOS transistor, and the retention time is very long, on the order of minutes at T ≅ 3 K, because the leakage of the source-body junction for VB < 0.8 V is small.

Figure 4 shows analogous bistability in a PMOS transistor fabricated in the same technology with LG = 0.18 μm and W = 10 μm, measured with the body contact attached to the electrometer: the ID(VG) characteristics are shown in Fig. 4 for VD = –1.4, –1.6, and –1.7 V at T ≅ 3 K. Evidently, bistable behavior can be obtained from both transistor polarities. In the PMOS case, the hysteretic loop begins to develop for |VD| > 1.5 V, since a slightly larger drain voltage is needed to produce a II current due to the lower mobility of holes. The measurement at VD = –1.6 V shows a gradual charging of the body, as confirmed by the VB(VG) trace shown in the inset. When VD = –1.7 V (even more negative), the switching becomes abrupt, and the hysteretic loop resembles the NMOS results in Fig. 3. The magnitude of the drain voltage VD required to produce a measurable II current in the PMOS transistor is somewhat higher, but the operating mechanism is essentially identical. Note that the device in Fig. 4 has the smallest LG = 0.18 μm available in this technology, so the full range of LG in both transistor polarities can be employed for the capacitorless DRAM based on our effect.

FIG. 4.

PMOS ID(VG) characteristics of an LG/W = 0.18/10 μm device at T = 3 K, showing similar hysteretic curves at VD = –1.4, –1.6, and –1.7 V. At VD = –1.6 V, the body potential charges up gradually, as shown in the inset, whereas at VD = –1.7 V, the current and VB switch sharply, as in the NMOS device of Fig. 3.

FIG. 4.

PMOS ID(VG) characteristics of an LG/W = 0.18/10 μm device at T = 3 K, showing similar hysteretic curves at VD = –1.4, –1.6, and –1.7 V. At VD = –1.6 V, the body potential charges up gradually, as shown in the inset, whereas at VD = –1.7 V, the current and VB switch sharply, as in the NMOS device of Fig. 3.

Close modal

The capacitorless single-transistor DRAM15–17 was intended to compete with a standard DRAM as a general-purpose compact volatile memory, but the continued success in scaling the standard DRAM capacitor precluded the capacitorless DRAM's widespread adoption. The cryogenic bulk capacitor-less memory presented here is intended for a niche application: due to the long retention times demonstrated in Fig. 3 and its fabrication in a standard bulk CMOS process, it can be used to provide nonvolatile memory for silicon control circuitry intended for quantum computation or sensing at cryogenic temperatures fabricated in the same process as the digital logic. At the same time, digital CMOS transistors operated as on/off switches would not be greatly affected by this bistable behavior, as the effect of VB on ION or IOFF is relatively slight.

In conclusion, we have demonstrated bistable behavior at cryogenic temperatures in bulk CMOS transistors fabricated in a 180 nm foundry process. The physical basis for this behavior is the charging of the local body potential by small impact ionization currents that appear at modest drain voltages (<1.8 V). The body potential can be as large as ≈1 V; it produces a current ratio of >107 between the high- and low-current states, and its retention time at cryogenic temperatures is sufficiently long, to provide memory capability without refreshing on the time scales predicted for quantum computation. These features make it promising for a compact, cryogenic memory that is effectively nonvolatile if low temperature is maintained.

This work was supported by the National Science Foundation (award QII-TACS-1936221). A. Zaslavsky gratefully acknowledges sabbatical support from Federal Award No. 70NANB18H160 (Brown/NIST PREP Gaithersburg program), while A. Madhavan acknowledges support under the Cooperative Research Agreement Award No. 70NANB14H209 through the University of Maryland.

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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