Simulations of hybrid charge-sensing single-electron-transistors and CMOS circuits

Single-electron transistors (SETs) have been intensively investigated owing to their advantages of low-power operation, which is desirable for application to logic and memory elements.^1,2 Since the Tucker's proposal,³ many approaches have been developed to replace the elements in complementary metal–oxide–semiconductor (CMOS) circuits.^4–9 SETs were also investigated after they were directly embedded in CMOS circuits.^8–10 Currently, conventional Si transistors are much smaller than SETs. SETs have attracted attention as charge sensors,^11–13 which have been used for the readouts of silicon qubits^14–16 or as current standards.^17–19 

The SET consists of a small metallic island or a degenerated semiconductor island surrounded by a source and drain via tunneling junctions with low capacitances. The SET yields periodic outputs referred to as Coulomb oscillations, which vary as a function of the gate voltage, and the oscillation period corresponds to the change in the number of electrons in the island. The maximum signal change in a SET is the difference between the peak and the trough of the Coulomb oscillation. The SET current is sensitive to electric potential variations on the SET island.¹¹ The standard readout process of a spin qubit [spin in localized states, such as a single impurity or quantum dot (QD)] is a spin-to-charge conversion, and the change in charge of the localized state is detected by the SET current.^14,15,20,21

There are many methods for the detection of charges, such as the use of radio frequency SETs (rf-SETs)^15,20,21 and the direct measurement of the SET by a single GaAs amplifier.^22,23 Inokawa et al. showed that a Coulomb oscillation is effectively outputted by directly connecting the SET to an MOS field-effect transistor. They experimentally demonstrated multiple-valued logic by SETs operating at 27 K. The effectiveness of the series coupling of the SET with MOS transistors was also experimentally investigated by Uchida et al.¹⁰ Scalable SET sensing systems require scalable circuits. However, previous SET sensors^14–19 did not explicitly consider the array of SETs as part of CMOS circuits.

In this study, we theoretically consider a scalable detection circuit based on the implementation of many SETs in CMOS circuits. Our basic concept of the amplification of the SET signals consists of two stages, as shown in Fig. 1. The first amplification stage of the process is conducted by direct connection of the SET to p-channel MOS (pMOS) transistors. In the second stage, we introduce a reference and a target SET and amplify the difference between two SETs using standard amplifier circuits, such as the differential amplifier (DA) circuits and the static random-access memory (SRAM) cells.

For smooth connection to the digital circuits, the output of the sensing circuit should be a digital signal (either a “0” or a “1”). For this purpose, it is better to compare the relative output of the target SET with that of the reference SET. In our application of the SRAM cell, the relative voltage difference between the target SET and the reference SET is found to be quickly latched to 0 or 1. This is in contrast to the measurements in Refs. 14–16, wherein the results were obtained after the analysis of a series of time-dependent SET currents. Our CMOS circuits are assumed to be close to the SETs. In addition, the target and the reference SETs are chosen by switching on the wordline transistors between the pairs of SETs and amplifiers. Then, the circuit using the pairs of SETs becomes more compact than the amplifying circuit of a single SET. Accordingly, our proposal is suitable for an array of sensing SETs.

In this study, we implement the current characteristics of the orthodox theory of the SET²⁴ into the SPICE (Simulation Program with Integrated Circuit Emphasis) circuit simulator based on the BSIM4 (Berkeley short-channel transistor model, level = 54) by using the standard modeling language of the Verilog-A. We considered two types of SETs: one of which is operated at low (4.2 K) and the other is operated at high temperatures (243 K). At low temperatures (LT), such as 4.2 K, the threshold voltage of the MOS transistors becomes higher because of the incomplete ionizations. Many studies regarding cryo-CMOS^25–28 have been conducted to determine the model parameters at low temperatures. However, the general compact model is not available for such low temperature. In addition, the basic CMOS operations are basically the same as that at room temperature (RT). Thus, we applied the CMOS parameters that are available in the conventional SPICE models to the CMOS parts for both types of the SETs. In the following, circuit calculations are mainly conducted at T = 243 K, which is in the range of the conventional models.

We consider CMOSs with gate lengths of L = 90 nm and L = 65 nm, whose drain voltages $VD$ are 1.2 and 1.0 V, respectively. We also consider the effects of small variations in the SETs and CMOS transistors. The purpose of the comparison of pairs of SETs is to detect the changes in the Coulomb oscillations of the target SET. Thus, given that the voltage difference between the peak and trough currents of the Coulomb oscillations can be distinguished, we will be able to detect the changes of the target SET even if there are variations in the devices.

Herein, we consider four SETs, as listed in Table I. The LT-SETt (target) and LT-SETr (reference) are operated at 4.2 K, and RT-SETt and RT-SETr can operate at 243 K. The parameters of the LT-SETt (RT-SETt) exhibit 10% variations compared with those of the LT-SETt (RT-SETr). The calculated current–voltage characteristics (⁠$ID$–$VD$⁠) are listed in the supplementary material. The charging energy is given by $Ec≡e2/[2(Cup+Cdn+Cg)]$⁠, where $Cup$ and $Cdn$ are the capacitances of the upper and under tunneling barrier of the left and right SETs, respectively, and $Cg$ is the gate capacitance (Fig. 1). The magnitude between the peak and trough currents is on the order of pA, and its voltage change estimated by pA × 25.9 k $Ω=$ 25.9 μV is very small (25.9 kΩ is a quantum resistance¹). On the other hand, the variations in the threshold voltage $Vth$ of conventional CMOSs are generally on the order of millivolts. Therefore, we need to amplify the SET outputs before connecting the SETs to conventional CMOS circuits.

We start from the first amplification stage in which the SET is directly connected to the CMOS transistors, as shown in Fig. 2(a). By a series connection, the low SET current value increases with CMOS.⁸ Figure 2(b) shows that the amplification of the SET signal becomes prominent at $VGp≳0.9$ V. The distortions of the waveforms compared with the original Coulomb oscillations originate from the nonlinearity of the $ID$–$VD$ characteristics of the pMOS transistors. We analyze the amplification mechanism based on the standard long-channel model.²⁹ The $ID$–$VD$ of CMOS transistors depend on the triode region $|VDS|<|VGS−Vth|$ or the saturation region $|VDS|>|VGS−Vth|$⁠. At present, amplification is observed in $|VDS|=|Vout−VD|≈$ 1.05 V $> |VGS|=|VGp−VD|=0.15$ V (saturation region). The SET current $ISET$ under large source–drain voltage is approximately described by $ISET∝VSET$ (see the supplementary material). More explicitly, we assume that $ISET≈VSET/RD$⁠. Thus, we can write the $ID$–$VD$ characteristics in the saturation region; furthermore, the SET given by

where $βp≡μpCoxWL$ and $λ(<1)$ are the channel length modulation coefficients (L, W, $Cox$⁠, and μ_p are the length, width, gate capacitance, and mobility of the pMOS, respectively). The solution of these equations is given by

where $ID0≡12βp(VGp−VD−Vthp)2$⁠. Because $ID0RD<VD$⁠, the SET output is enhanced by $1+λVD1+λID0RD>1$⁠. Note that λ is conspicuous in both the L = 90 nm and L = 65 nm pMOS transistors (see the supplementary material), and we can see that the output voltage oscillates around ∼10 mV in Fig. 2(b).

The second-stage amplification is conducted using standard amplifier circuits. Figure 3 shows the results obtained from a basic DA circuit. Note that the gate voltages $VG1$ and $VG2$ represent the shifted electrical potential $VSET$ by the additional sensing QD in Fig. 1. Conventional DAs amplify two inputs with opposite phases. In the case of SETs, two different phases of Coulomb oscillations are input. We consider that the two SET signals possessing different current peaks mimic the two input signals of the conventional DA with different phases. In Fig. 3(b), we show the results for the output voltage difference of $Vout2−Vout1$ for a fixed $VG1=0$⁠. The voltage difference $Vout2−Vout1$ increases by approximately 50 mV for L = 90 nm (the results for L = 65 nm are shown in the supplementary material) and can be detected by conventional CMOS amplifier circuits (the following circuits after $Vout2$ and $Vout1$ are not shown). This enhancement of the Coulomb oscillations is the result of the two-stage amplification of SET signals.

The magnitude of the enhancement of the Coulomb oscillation in Fig. 3(b) changes depending on the threshold voltage variations of the eight MOS transistors. In Fig. 3(c), we provide the distribution of the difference in the peak and trough of $Vout2−Vout1$ obtained through over 300 Monte Carlo simulations of the threshold variations with LT-SETt and LT-SETr at $VG1=0$ and $VG2=0.2$ V. The number of small amplitudes of $|Vout2−Vout1|$ (<5 meV) is nine out of 300 samples. Small amplitudes of $Vout2−Vout1$ can be avoided by applying different voltages such as $VGpi$ and WL_i on each part of the DA.

We now consider the application of the standard SRAM cell containing six MOS transistors³⁰ to detect a pair of SETs, as shown in Fig. 4(a). Figure 4(b) shows the simulation results of the time-dependent SRAM cell outputs $Vout1$ and $Vout2$ of the two LT-SETts. We can see that $Vout1<Vout2$ for $VG2=0.1$ V, but $Vout1>Vout2$ for 0.15 V $≤VG2≤0.4$ V for L = 90 nm devices. This implies that the shift in the electric potential of the sensing QD from $VG2=0.1$ V to $VG2=0.15$ V changes the electric potential of the target SET island, resulting in a change in the relative magnitude between $Vout1$ and $Vout2$⁠. Figure 4(c) replots $Vout2−Vout1$ in Fig. 4(b) as a function of $VG2$ with the results for $L=$ 65 nm at time $10−8$ s. Thus, we can detect the change in the target SET represented by $VG2$ by measuring the relative outputs of the SRAM cell. Herein, the initial voltage at the SRAM cell input is set to $VD/2$⁠, and stray capacitances of 0.2 pF are included at the input nodes of the SRAM cell (figures not shown). As the stray capacitance increases, the time to split increases.

In general, SRAM cells undergo initial threshold voltage $Vth$ variations,³¹ and we have to consider these variations in the MOS transistors as well as the two SETs. Here, we extend the SRAM cell circuit to a dynamic random-access memory (DRAM)-like structure^32,33 in Fig. 5(a), where it is considered that the equalizer circuit mitigates the voltage difference of the wordlines between the two SETs. Figures 5(b) and 5(c) show two types of readouts for the two types of SETs. The equalizer signal EQ (EQualizer) is activated at 1 ns and stopped after 2 ns. The SAN (Sense-Amplifier N-Fet Control) and SAP (Sense-Amplifier P-Fet Control) signals are activated after the equalizer at t = 6 ns and t = 8.5 ns. The wordlines WL₁ and WL₂ (WL = WL₁ = WL₂) are activated at 4 ns. We can see that the change in the gate voltage $VG2$⁠, which corresponds to the existence of the charge sensor QD, causes the outputs $Vout1$ and $Vout2$ to change from $Vout1>Vout2$ to $Vout1<Vout2$⁠.

In a realistic situation, it is possible that the temperature changes. Therefore, we also calculated the temperature dependence of the amplifier response. It is desirable that the relative magnitude of $Vout1$ to $Vout2$ does not change even when the operating temperature changes. The temperature dependencies of the characteristics of the DA (Fig. 3) and DRAM (Fig. 5) are robust against temperature changes as long as the temperature change is sufficiently small on the order of several tens of degrees (see the supplementary material).

Considering that there are variations in SETs and MOS transistors, we may have to check and record the basic characteristics of each device at the first calibration stage of the chip. The I–V characteristics of each SET should be clarified before using the charge-sensing SET. This information is stored in the extra SRAM or other memories and becomes the overhead of the system. An effective method for determining the optimal biases automatically is a future issue. It is possible that the applied voltages destroy the SET charge states. However, herein, we neglected the effects of the backaction from the CMOS circuits. Hence, the assessment of the backaction remains a future issue.

In conclusion, we proposed two-stage amplification circuits for SETs. Based on serial connections with MOS transistors and a comparison with the reference SET, we numerically show that the readout of the charge-sensing SET is greatly enhanced. We also considered the effects of variations in the MOS transistors and SETs and show that as long as the variations are small, the two SETs can be compared effectively.

See the supplementary material for the complete derivation process of the equations.

We are grateful to T. Mori and H. Fuketa for the fruitful discussions. We are also grateful to Y. Yamamoto for his technical support in using SmartSpice. This work was partly supported by MEXT Quantum Leap Flagship Program (MEXT Q-LEAP; Grant No. JPMXS0118069228), Japan.