Fabrication and characterization of a self-aligned gate stack for electronics applications

One of the critical issues for the fabrication of high-performance silicon transistors is the alignment between the edge of the gate stack and the edge of the underlying doped source-drain regions of the silicon channel. Too much overlap results in a large fringe capacitance and a reduction in device speed while too much underlap can result in too large of an access or series resistance.^1,2 Achieving an optimized alignment within an integrated high-k/metal gate stack can require complicated integration schemes such as the replacement metal gate technique.³ The processing and integration becomes even more challenging for gate all around (GAA) transistors with either lateral⁴ or vertical silicon nanowires,⁵ where numerous process steps are required to align the gate stack over the channel.

The overall objective of this work is to develop a process that aligns a metal–oxide–semiconductor (MOS) gate stack to the underlying channel based only on its compositional doping pattern, largely irrespective of the geometry. As a first step to achieving this objective, we combine a new hybrid bottom-up patterning technique with area-selective atomic layer deposition (AS-ALD) to deposit hafnium dioxide (HfO₂) and platinum (Pt) thin films based on the local carrier concentration of a Si wafer to fabricate a high quality planar MOS capacitor. The availability of self-aligned device structures, such as MOS capacitors, would be valuable for a variety of emerging device applications, like vertical nanowire transistors monolithically integrated into the back end of line (BEOL)⁶ and flexible electronics requiring lower temperature processes and alternative patterning techniques that are more scalable than conventional photolithography.⁷ This work demonstrates a patterning and deposition technique that could be further developed to fabricate devices for such applications.

Atomic layer deposition (ALD) allows for the area-selective and low temperature deposition of thin films intimately aligned with compositional patterns of the underlying substrate, largely irrespective of the geometry. The most common techniques for area-selective ALD (AS-ALD) involve the use of self-assembled monolayers (SAMs)^8–15 or other polymeric materials^16–21 to mask the surface by preventing ALD precursors from chemisorbing. These techniques often require photolithography to pattern the surface modification layer^13,16–18 or use surfaces patterned with different materials^8,12,21,22 to apply the masking material selectively based on the underlying substrate. For example, a SAM can be assembled only on silicon dioxide (SiO₂) regions of a patterned silicon wafer, leaving hydrogen-terminated silicon exposed.⁸ This allows for deposition of self-aligned features based on the underlying substrate but requires the underlying materials (silicon and SiO₂) to have significantly different properties.

There are a number of challenges associated with the AS-ALD of a high-performance MOS gate stack. For BEOL and flexible electronics, one needs low temperatures and AS-ALD is well suited in this regard.²³ However, a high-performance gate stack needs high-quality materials and low defect density interfaces. While there has been some electrical characterization of AS-ALD films in the literaure,^11,12,19,24 there have been relatively few AS-ALD studies for such applications. In many cases, a self-aligned gate stack also requires selective deposition on chemically similar materials with only variation in dopant concentration designating the pattern (e.g., source/channel/drain), which is currently difficult to achieve with AS-ALD.

In this work, we combine a new hybrid bottom-up patterning technique with AS-ALD to deposit hafnium dioxide (HfO₂) and platinum (Pt) thin films based on the local carrier concentration of a Si wafer. The patterning technique is a derivative of selective co-axial lithography via etching of surfaces (SCALES),²⁵ which was originally demonstrated on cylindrical nanowires (hence co-axial) but is equally amenable to planar substrates. The SCALES technique begins with the blanket growth of a polymer brush, followed by its selective removal based on differences in the etch rate of the underlying substrate. This work uses a poly(methyl methacrylate) (PMMA) brush chemically bonded to the silicon surface, as an alternative to the more commonly used spin-coated PMMA, which allows for selective removal based on the underlying Si carrier concentration by leveraging the selective etch properties of KOH.²⁶ KOH diffuses through PMMA, removing a few layers of lightly doped Si, which also removes PMMA from these regions. PMMA remains on the heavily doped Si, serving as a mask. There are many masking materials, from SAMs to polymers, that are likely useful depending on the situation. Here, we study the model polymer PMMA to demonstrate key process steps, but we expect a variety of derivative methods will work as well. Using the SCALES patterning technique with PMMA in combination with AS-ALD, we fabricate a self-aligned gate stack with promising capacitance–voltage characteristics.

Si(100) with doping levels of ∼10¹⁸ cm⁻³ (lightly doped) and ∼10²⁰ cm⁻³ (heavily doped) is used as the substrate to mimic a typical MOSFET structure. A lightly boron-doped Si(100) wafer is patterned with a 500 nm-thick SiO₂ mask before being doped with boron via solid state diffusion (2 h at 1050 °C, B₂O₃ source). The masked regions (100 × 100 μm² squares and a large 4 × 6 mm² rectangle for XPS characterization) remain lightly doped, while the rest of the Si substrate is heavily boron-doped. A PMMA brush is synthesized to deactivate the Si surface using adaptation of a previously described procedure.²⁵ Briefly, an anchoring molecule (11-undecen-1-ol) is attached to the hydrogen-terminated Si surface via hydrosilylation at 150 °C for 2 h. Next, an initiating group (bromoisobutyryl bromide) is attached at room temperature for 2 h. Finally, PMMA is polymerized at 90 °C for 4 h via atom transfer radical polymerization of methyl methacrylate. The PMMA brush is selectively removed from the lightly doped regions via cycles of exposure to KOH solution (1 ml 45 wt. % KOH: 3 ml IPA: 8.5 ml DI H₂O) to etch Si and acetone to solvate PMMA.

X-ray photoelectron spectroscopy (XPS) is used to characterize the selective removal of PMMA from the lightly doped silicon. The XPS measurements are conducted using a monochromatic Al Kα source with a spot size of 400 μm and a pass energy of 50 eV. Figure 1 shows typical C(1s) XPS spectra for the heavily- and lightly doped silicon immediately after the polymerization process and after 25 etch cycles. After polymerization [Fig. 1(a)], both the heavily- and lightly doped silicon show strong C(1s) peaks characteristic of PMMA. It is known that the C(1s) photoelectron spectrum shows four strong peaks for PMMA corresponding to the C-C/C-H, C in the α-position to the ester group, C–O, and O–C=O components at 285.0, 285.7, 286.8, 289.1 eV, respectively.^27,28 Following 25 etch cycles [Fig. 1(b)], the C(1s) spectrum is unchanged for the heavily doped silicon, while the C(1s) peaks reduce by 90% for the lightly doped Si. The C(1s) signal observed for the heavily doped silicon after PMMA removal is equivalent to that of adventitious carbon (not shown).

PMMA removal as a function of number of etch cycles is investigated and characterized with XPS integrated area ratios as well as spectroscopic ellipsometry. As seen in Figs. 2(a) and 2(b), the constant C(1s) and Si(2p) peak areas on the heavily doped Si verify the durable attachment of the PMMA brush. On the lightly doped Si, the C(1s) peak area decreases, and the Si(2p) peak area correspondingly increases as PMMA is removed. Spectroscopic ellipsometry is performed using a Woollam M200 ellipsometer, and the CompleteEASE software is used for fitting with the PMMA, SiO₂, and HfO₂ film models. Ellipsometry data in Fig. 2(c) show that the PMMA film thickness remains relatively constant on the heavily doped Si while it decreases down to just a few nanometers on the lightly doped Si. The achievable feature size relies on the underlying dopant profile and the polymer properties, as there likely will be some polymer overlapping the dopant junction. The degree of overlap and achievable feature size are expected to depend on the structure and length of the polymer and will be characterized with the future work. Overall, the results indicate that the process can achieve selective masking based on the underlying doping concentration.

To fabricate a gate stack leveraging the SCALES-patterned PMMA mask, HfO₂ and Pt are deposited via AS-ALD. A modified RCA clean consisting of 1 min in SC-1 (5 DI H₂O:1 H₂O₂:1 NH₄OH) at 75 °C, 30 s HF etch, and 10 min in SC-2 (5 DI H₂O:1 H₂O₂:1 HCl) at 75 °C is used to clean the exposed Si before depositing the oxide and metal layers. The organic SC-1 clean is shortened to 1 min to minimize damage to the patterned PMMA film, and the SC-2 clean forms a ∼2 nm-thick passivating layer of chemical oxide on the Si surface. HfO₂ is then deposited selectively with 60 cycles of thermal ALD using tetrakis(dimethylamido)hafnium (TDMAHf) and H₂O precursors at 200 °C. The exposure times for TDMAHf and H₂O are 0.25 and 0.06 s, respectively, followed by purge times of 20 and 15 s. Immediately following HfO₂ deposition, platinum is selectively deposited with 300 cycles of thermal ALD using (trimethyl)methylcyclopentadienylplatinum(IV) (MeCpPtMe₃) and O₂ precursors at 300 °C. The exposure times for MeCpPtMe₃ and O₂ are 1 and 10 s, respectively, followed by purge times of 10 s. All materials are deposited with a Cambridge Fiji ALD system with argon as a carrier/purging gas and a total chamber pressure of 0.45 Torr.

The selectively deposited Pt-HfO₂-Si gate stack is characterized with XPS after each step. Though the deposition temperatures are above the glass transition temperature of PMMA (∼115 °C),²⁹ the polymer brush offers robust passivation against ALD. The Hf(4f) XPS spectra taken after HfO₂ ALD in Fig. 3(a) show a doublet with peaks at 16.7 and 18.3 eV in the lightly doped region, confirming the selective deposition of HfO₂ on the exposed Si surface. As can also be seen, minimal HfO₂ deposits on PMMA covering the heavily doped regions. A comparison of integrated XPS peak areas for the lightly- and heavily doped Si regions reveals a deposition selectivity of 30:1. Notably, an examination of TiO₂ and ZrO₂ AS-ALD shows these materials are also compatible with this process (see the supplementary material). The Pt(4f) XPS spectra taken after Pt ALD in Fig. 3(b) show a strong doublet with peaks at 71.2 and 74.5 eV verifying selective deposition of Pt on top of HfO₂ in the lightly doped regions with very little deposition on PMMA on the heavily doped regions. Here, the deposition selectivity between the lightly- and heavily doped Si regions is found to be 69:1, consistent with what is observed with SAMs³⁰ and spincoated PMMA.¹⁶ 

Energy dispersive x-ray spectroscopy (EDS) is used to characterize the resulting self-aligned MOS structures to examine the spatial selectivity of deposition. Figure 4(a) shows an SEM image of four 100 × 100 μm² MOS capacitors that are aligned with the lightly doped Si (square) patterns. Figures 4(b), 4(c), and 4(d) show EDS maps for Si, Hf, and Pt, respectively, confirming the presence of HfO₂ and Pt mainly within the square patterns. The Hf Mα1 peak overlaps with the large Si Kα1 peak from the substrate, and the extra noise makes the pattern less clear, but a stronger intensity can be seen inside the square patterns where HfO₂ is present under the Pt layer.

The MOS capacitors are characterized with capacitance–voltage (C–V) measurements to study the electrical properties of the selectively deposited gate stack and investigate the impact of a forming gas anneal, which has been shown in the literature to reduce interface state density.^31,32 Capacitance and conductance are measured at 100 kHz with a voltage sweep range from 3 to –3 V using a Keithley 4200-SCS semiconductor analyzer. Figure 5 shows the C-V behavior of three different MOS capacitors before and after a forming gas anneal at 400 °C for 30 min (96% N₂/4% H₂). With an oxide thickness of 6.1 nm of HfO₂ and a 2 nm-thick interlayer of SiO₂ (estimated from ellipsometry measurements), the maximum capacitance (from Fig. 5) is used to estimate a relative dielectric constant of ∼25.3, as expected for HfO₂.³³ The C–V curves demonstrate typical MOS characteristics and show improved behavior after the forming gas anneal, indicated by the curve’s reduced stretch out. The average interface state density of MOS capacitors following AS-ALD is 8.0 × 10¹¹ eV⁻¹cm⁻², as approximated using the conductance peak and $Dit≈2.5qGpωmax$⁠. The inset plot in Fig. 5 shows that D_it can be reduced by a factor of 4 using a forming gas anneal. The D_it is relatively high for silicon based MOS capacitors, however, and future work will be performed to improve the interface quality with alternate surface cleaning techniques and improved interfacial layers.

In summary, a self-aligned gate stack structure is demonstrated with a process that combines SCALES and AS-ALD. The PMMA brush grafted from the Si(100) surface is selectively removed based on the underlying semiconductor carrier concentration and serves as a mask for ALD. HfO₂ and Pt are selectively deposited, forming MOS capacitors suitable for a gate stack. Current-voltage measurements show expected MOS capacitor behavior and improvement upon forming gas anneal. This process can be used to fabricate complex nano- and micro-structure devices without photolithography, which holds promise for BEOL processes and flexible electronics applications.

See the supplementary material for XPS characterization of selectively deposited TiO₂ and ZrO₂ films.

This work was supported by the Department of Defense (DOD) through the National Defense Science and Engineering Graduate (NDSEG) Fellowship Program and the National Science Foundation (No. CMMI-1916953). This work was performed in part at the Georgia Tech Institute for Electronics and Nanotechnology, a member of the National Nanotechnology Coordinated Infrastructure (NNCI), which is supported by the National Science Foundation (No. ECCS-2025462).