In this Letter, we report a back-end-of-line (BEOL), complementary metal–oxide–semiconductor (CMOS)-compatible Al0.64Sc0.36N-based ferroelectric diode that shows polarization-dependent hysteresis in its leakage currents. Our device comprises a metal/insulator/ferroelectric/metal structure (Pt/native oxide/Al0.64Sc0.36N/Pt) that is compatible with BEOL temperatures (≤ 350 °C) grown on top of a 4-in. silicon wafer. The device shows self-selective behavior as a diode with > 105 rectification ratio (for 5 V). It can suppress sneak currents without the need for additional access transistors or selectors. Furthermore, given the polarization-dependent leakage, the diode current–voltage sweeps are analogous to that of a memristor with an on/off ratio of ∼ 50 000 between low and high resistance states. Our devices also exhibit stable programed resistance states during DC cycling and a retention time longer than 1000 s at 300 K. These results demonstrate that this system has significant potential as a future high-performance post-CMOS compatible nonvolatile memory technology.
New device applications such as the Internet of Things (IoT) devices, non-von Neumann computing architectures, and artificial intelligence (AI) computing algorithms are creating a strong demand for high-density, nonvolatile memory (NVM) solutions with low power consumption. Among various emerging NVM technologies,1 ferroelectric random-access memories (FeRAM) are compelling due to their high access speed, high endurance, extremely low write energy and current, and good retention.2–5 However, the incorporation of FeRAM into commercial scale semiconductor applications has been stalled at the 130 nm node.1–5 There are three main challenges that have hindered rapid development of ferroelectric (FE) memories and kept them from challenging classical charge-based memories and other NVM technologies: (1) the traditional one transistor–one ferroelectric capacitor (1T1C) structure undergoes destructive readout and has a large footprint; (2) traditional ferroelectrics are incompatible with standard BEOL, CMOS-compatible process;6–8 (3) as perovskite FE materials such as lead zirconium titanate (PZT) or barium titanate (BTO) are scaled to thinner layers, their ferroelectric properties degrade.9,10
Various emerging technologies have been developed over the past decade to address these issues. Two terminal devices such as the ferroelectric diode11,12 and ferroelectric tunnel junction (FTJ),13–19 which utilize a polarization-dependent leakage or tunneling current and rectification to perform resistive switching (analogous to memristors20–22), are a promising alternate to a 1T1C cell. This is because they have the advantage of being compact, two-terminal geometry device that use a nondestructive readout.11–19 Recently, FTJ memristors based on doped HfO2 have attracted considerable attention for compact nonvolatile memory applications. However, the high annealing temperatures (≥ 400 °C) necessary for doped HfO2 to attain ferroelectricity in most reports renders them unsuitable for CMOS, BEOL-compatible process integration.4,5 A high on/off ratio is essential not only to enable low power, in-memory computing but also for maintaining a strong immunity to noise and variations when used in emerging applications such as multi-bit memory devices for neuromorphic computing.23
The recent discovery of Sc-doped AlN (referred to as AlScN) as a ferroelectric presents a promising avenue for the realization of practical two-terminal ferroelectric nonvolatile memory devices.24,25 AlScN exhibits a wurtzite structure similar to AlN and shows N polar or metal polar states. The key to ferroelectric switching is the energy barrier between these two polarization states, which can be lowered by increasing Sc substitutional doping that occupies Al sites or via strain engineering.24 AlScN shows large coercive fields, Ec, of 2–4.5 MV/cm, which enables scaling to thinner ferroelectric layers, while maintaining a large memory window. When combined with high remnant polarizations—Pr, of 80–115 μC/cm2—this leads to significant resistive switching, due to the strong tunnel barrier modulation, and thus a high on/off ratio. The more recently reported ferroelectric switching in sub-20 nm Sc-doped AlN at low deposition temperature (≤ 350 °C) allows for these devices to be integrated directly in a CMOS, BEOL-compatible process.26
Here, we demonstrate Al0.64Sc0.36N-based ferroelectric diodes that are fabricated in a fully BEOL, CMOS-compatible process on a 4-inch Si wafer. With 20-nm-thick Al0.64Sc0.36N as a ferroelectric layer with a thin native oxide barrier layer, the resulting ferroelectric capacitors show a polarization dependent hysteresis in leakage current, with a large self-rectifying ratio > 105, a high on/off ratio of over 50 000, a stable programed state over DC cycling, and a retention time longer than 1000 s at 300 K. These results hold promise for future high-performance, CMOS BEOL compatible NVM.
Figure 1(a) shows the schematic diagram of a Pt/native oxide/Al0.64Sc0.36N/Pt device. A Pt (100 nm) bottom electrode (BE) was deposited by sputtering onto the Si substrate. Next, a 20-nm Al0.64Sc0.36N film was co-sputtered from two separate 4-in. Al (1000 W) and Sc (655 W) targets in an Evatec CLUSTERLINE® 200 II pulsed DC Physical Vapor Deposition System. The deposition was done at 350 °C with N2 gas flow of 20 sccm. Subsequently, top electrode (TE) regions were then patterned using standard photolithography, as shown in Fig. 1(c), followed by evaporation of a Pt (100 nm) metal top electrode and liftoff process. Figure 1(b) shows a cross-sectional transmission electron microscopy (TEM) image of the Al0.64Sc0.36N film on Pt BE. In Fig. 1(b) inset, the high-resolution TEM image of the regions enclosed by the red boxes illustrates textured epitaxial growth of the Al0.64Sc0.36N film and a ∼4- nm native oxide layer at the ferroelectric surface due to exposure to ambient air. The energy dispersive x-ray spectroscopy (EDS) analysis map of the device cross section suggests that the oxide has similar Al and Sc concentration as the nitride. We note that the presence of oxide is not necessary to demonstrate the most basic and distinguishing property of our device, which is the polarization dependent leakage as discussed in more detail below. The Schottky barrier between Al0.64Sc0.36N and Pt introduces the asymmetry in the device structure. The modulation of this Schottky barrier with ferroelectric polarization switching provides the large difference in leakage current between sweeps combined with the rectification function in the device (similar to a diode) and hence the term ferroelectric diode. There are several other examples in the literature based on other ferroelectric materials that have shown the same device concept and function and have been referred to by the same name.11,12 Here, we demonstrate this concept in an AlScN-based ferroelectric material.
Since the leakage in our device is both polarization-dependent and asymmetric in nature, the ferroelectric polarization upon switching is convoluted by leakage in a typical polarization–electric field (P–E) loop measurement. To overcome this issue, positive-up-negative-down (PUND) measurements were performed at low temperature (120 K) and at a relatively high frequency (10 kHz) to suppress leakage and clarify the FE properties of the Al0.64Sc0.36N. More details of P–E hysteresis measurements at room temperature can be found in our previous reports.25–27 Figure 1(c) presents a typical P–E hysteresis loop of the Al0.64Sc0.36N device as extracted from the PUND measurements. The pulse schematic of the PUND measurement is provided in supplementary material Fig. S1 as well as our prior publications.25–27 The measurement indicates a coercive field of 6.5 MV/cm and a remnant polarization of 25 μC/cm2. The coercive field is observed to be slightly larger than the values observed in our DC measurements, and the values reported in Refs. 25 and 26 at 300 K. We posit that this is because the coercive field is reported to significantly increase as temperature drops28,29 and as the frequency of measurement increases.24,30,31 We attribute the relatively low remnant polarization to the partial ferroelectric switching during the PUND measurement at low temperature. Further, the C–V curve of our device measured at 1 MHz at room temperature [Fig. 1(d)] illustrates a butterfly shaped loop suggesting a non-linear capacitor that has decreasing capacitance with increasing applied voltage, indicating ferroelectric polarization switching. Similar C–V curves have been reported for FTJ or ferroelectric diode devices based on other FE materials.37,38 In addition, we observe a clear ferroelectric switching induced peak during our first C-V sweep, which disappears upon repeated C–V measurement sweeps (See supplementary material Fig. S2) further suggesting the ferroelectric nature of the switching.
Figure 2 shows the I–V characteristics of the Al0.64Sc0.36N ferroelectric diodes in semi-log and linear scale. The blue plots represent non-linear diode-like I–V curves in which polarization points to TE after applying a negative program voltage, whereas the orange plots show I–V curves in which polarization points to BE after applying a positive program voltage. After being programed by a positive voltage, the resistance changes from high-to-low, and the polarity of the memristor changes from a negative-forward diode (blue lines) to a positive-forward diode (orange lines). Similarly, it can be observed in a negative voltage sweep that the polarity of the memristor changes from that of a positive-forward diode to that of a negative-forward diode. Because of the existence of a Schottky barrier between the Al0.64Sc0.36N and the metal electrode (Pt), the device shows self-selective behavior as a diode with > 105 rectification ratio for 5 V, which is likely to suppresses sneak currents without additional access transistors or selectors when used in crossbar-arrays.23 A large on/off current ratio of 50 000 is obtained between forward and backward voltage sweeps at a readout bias voltage ∼2.5 V, which exceeds the on/off ratios of previously reported in hafnia-based FTJs13–19 and ferroelectric diodes.12 A summary of important characteristics of ferroelectric memristive devices from the literature is presented in Table I, with a focus on the CMOS compatibility, on/off ratio, and the thickness of the ferroelectric layers. It is worth noting that our reported Al0.64Sc0.36N-based ferroelectric diodes is one of two demonstrated examples that concurrently exhibits a high on/off ratio while being compatible with CMOS, BEOL-compatible processing. We note that while the presence of surface oxide may be critical to obtain large on/off current ratios, an oxide layer is not necessary or important to demonstrate a ferrodiode effect in our devices. This is further evident from our Al (30 nm)/Al0.68 Sc0.32N (45 nm)/Al (85 nm) in situ deposited MIM ferrodiodes27 that show a similar effect with an on/off ratio of ∼100 (see supplementary material S3).
|Ferroelectric .||CMOS compatibility .||On/Off Ratio .||Thickness (nm) .|
|BTO36||Low||6 × 106||1.6|
|This work||High||50 000||20|
|Ferroelectric .||CMOS compatibility .||On/Off Ratio .||Thickness (nm) .|
|BTO36||Low||6 × 106||1.6|
|This work||High||50 000||20|
Furthermore, we studied the effect of polarization on the band diagram and electronic transport in these Al0.64Sc0.36N ferroelectric diodes. We note that given that our Al0.64Sc0.36N films are sputter deposited and contain a large number of point and line defects, they are bound to possess several trap states within the bandgap. Therefore, current conduction through a MIM ferroelectric diode device with 20-nm-thick ferroelectric insulator must account for some trap-assisted transport/conduction mechanism as a means to explain the μA-level currents observed in our measurements under forward bias. We therefore fitted the forward current through the diode vs applied voltage with a well-known trap-assisted conduction and leakage current model, namely the Poole–Frenkel (P–F) tunneling model.4,39 In addition, we have also sought to compare Fowler–Nordheim or direct, wave-mechanical tunneling of electrons through a modulated triangular barrier. The ferroelectric polarization charge effects induce an asymmetric modulation of the electronic band diagram. As shown in Fig. 3, when P is reversed, the steepness of the electronic band diagram is changed, depending on whether the direction of P is identical or opposite to the applied electrical field. As show in Fig. 3, when a positive voltage is applied to the TE, the barrier height is—on average—higher when P points to the TE than when P points to the BE. Electronic band diagrams of high resistance states (HRS) and low resistance states (LRS) of the ferroelectric diode at positive bias, with two conduction mechanisms, have been sketched in Figs. 3(a) and 3(b). Given the ∼20- nm-thickness of the ferroelectric insulator layer, direct wave-mechanical tunneling is expected to be negligible since the tunneling probability exponentially decays with the width of the barrier. Therefore, our current–voltage data fit best to the P–F tunneling model, as shown Fig. 3(c). The extracted dielectric constant of ∼16 of the ferroelectric layer from the P–F model is also close to independent capacitance measurements of 14–15, which is also similar with the values reported by Akiyama et al.40 We note that the ferroelectric polarization switching occurs in our device due to the applied electric field and this switch in polarization changes the field profile and leakage through the 20-nm-thick ferroelectric layer. The trap-assisted Poole–Frenkel tunneling is used to describe this leakage mechanism. It is also worth noting that similar mechanisms have also been used to describe conduction through FTJ devices where the ferroelectric layer thickness is much smaller.39 For the LRS, the applied electrical field follows the ferroelectric polarization direction. The injected electrons hop from highly occupied traps to empty traps, and consequently, the current is high. Conversely, if the applied electrical field is opposite to the ferroelectric polarization direction, the electron hopping rate is significantly reduced, since there are fewer occupied electrons. This leads to empty traps, breaking the total number of conduction pathways and results in a lower current through the diode. While a full compact I–V model for the device will be important and is a subject of ongoing research, it is beyond the scope of the current manuscript and will be reported in our future publications. Finally, we would also like to note that conductive bridge formation can be ruled out as the resistive switching in our devices based on area dependent current density scaling in our MIM devices. We have verified this with linear scaling of the ON current with the area of our MIM devices further verifying the ferroelectric nature of the resistive switching (see supplementary material S4).
We have also conducted preliminary reliability tests on our ferroelectric diodes. Figure 4(a) presents data from 10 manually performed DC cycles. Cyclic I–V curves from the same device indicate that the current–voltage characteristics are stable and repeatable. Furthermore, the two different polarization states of the ferroelectric and hence resistance (current) states of the memristor can be programed as two nonvolatile memory states. Readouts at various delay times were carried out to determine retention [Fig. 4(b)]. The low and high current/resistance states can be retained for at least 1000 secs at room temperature without obvious degradation. Given the purely electronic mechanism of switching in our ferroelectric diode, like all other ferroelectric memory devices, it is subject to the voltage-time dilemma.41 However, this voltage-time dilemma can be minimized with thinner ferroelectric layers and having near-ideal (square-shaped) hysteresis loops concurrently with high coercive fields, a property that AlScN materials possess.24–27
In summary, we have demonstrated an Al0.64Sc0.36N-based ferroelectric diode that shows a large difference in leakage current as a function of ferroelectric polarization resulting in hysteretic current voltage loops analogous to a memristor. Our devices are fabricated in a fully BEOL, CMOS-compatible process on 4-in. Si wafers. With 20-nm-thick Al0.64Sc0.36N as a ferroelectric layer, the resulting ferroelectric diodes exhibit high performance with a large self-rectifying ratio > 105, a high on/off ratio of over 50 000, a stable programed state over DC cycling, and a retention time longer than 1000 s at 300 K. These results demonstrate that this system has significant potential as a future high-performance CMOS, BEOL-compatible nonvolatile memory technology.
See the supplementary material for voltage pulsing schematic for PUND measurements, additional C–V measurements of the devices, I–V curves of in situ deposited MIM devices, and J–V curves of devices with different areas.
This material is based upon work supported by the Defense Advanced Research Projects Agency (DARPA) TUFEN program under Agreement No. HR00112090046. The work was carried out in part at the Singh Center for Nanotechnology at the University of Pennsylvania, which is supported by the National Science Foundation (NSF) National Nanotechnology Coordinated Infrastructure Program (NSF Grant No. NNCI-1542153). The authors acknowledge use of facilities supported by NSF through the Penn Materials Research Science and Engineering Center (MRSEC) (No. DMR-1720530). TEM sample preparation was performed by Kim Kisslinger at the Center for Functional Nanomaterials, Brookhaven National Laboratory, which is a U.S. DOE Office of Science Facility, under Contract No. DE-SC0012704.
The data that support the findings of this study are available within the article. Additional information and data are available from the corresponding author upon reasonable request.