Supercurrent-controlled kinetic inductance superconducting memory element

Superconducting supercomputers could provide a powerful alternative to modern semiconductor-based computers since the power dissipated in superconducting elements can be very low, i.e., it can approach thermodynamic and quantum information processing limits.^1,2 The “bottleneck” for the development of superconducting computers is the absence of a compact fully superconducting memory element.¹ Nanowires^3–8 provide an important alternative to the existing elements based on tunnel junctions^9–14 since their operation is based on their kinetic inductance,^1,3,15 which could be very large in nanowires with nanometer-scale dimensions. The employment of a large kinetic inductance for the memory function allows for a great reduction of the dimensions of the device.^1,3

Previously reported superconducting memory elements either required magnetic fields for their functioning or were not fully superconducting since some of their elements required Joule heating.^3,4,16 Here, we report a fully superconducting kinetic inductance memory (SKIM) element, based on single quantized superconducting fluxons, which is expected to be free from previously existing drawbacks listed above. The SKIM is made of Nb, deposited over a pair of suspended SiN nanoconstrictions. The reported memory does not require sub-Kelvin temperatures, as was the case in many previously reported devices. Our SKIM element was tested in a cryogen free refrigerator and was operational up to a temperature of ∼3 K. The highest frequency of the memory switching, tested up to ∼50 kHz, was limited by the setup equipment and, in principle, could be much higher since the phase of the order parameter can change at a much higher rate.¹⁷ 

The sample geometry is shown in Fig. 1(a). The cross section is shown in Fig. 1(b), where the trench design is illustrated while the bridge is not shown. The top view is shown in Fig. 1(c). The sample contains two suspended nanobridges connected at each their end to thin superconducting films, which are referred to as “electrodes” or “leads.” The electrodes and the nanoconstrictions are made of a 15-nm-thick Nb film. To fabricate the sample, a line-with-break pattern is prepared by e-beam lithography with a line dosage of 9 nC/cm on a 60 nm SiN/500 nm SiO₂/500 μm Si substrate. In each e-beam lithography session, we pattern a whole 4″ wafer with hundreds of pairs of SiN bridges,²¹ which can be later used for metal deposition followed by photolithography patterning of the leads. Each device has its unique number markers (device numbers) near the nanobridges, such that we can tell them apart. The dimension of each nanobridge is a function of the device number. This design allows us to produce nanobridges of various sizes. We intentionally make multiple devices with the same device number and control the fabrication process so that devices with the same numbers always have very similar nanowire dimensions. This method allows us to make batches of samples with high reproducibility. The trench and nanobridges are developed in a 2 min 30 s SF6 reactive ion etching (RIE) and a 10 s HF wet etching, needed to form an undercut, to make the nanobridges suspended. The undercut is visible in Fig. 1(a) as a gray area on both sides of the trench. The resulting structure contains a 200-nm-wide trench [dark area in Fig. 1(a)] and two constrictions bridging the gap over the trench. The width of the SiN nanobridges is typically in the range of 10–30 nm. A 15 nm Nb film is sputtered over the SiN nanobridges to form superconducting nanoconstrictions, the width of which is defined by the width of the underlying SiN bridge. Initially, there are many nanobridges crossing the trench. We use photolithography to select and protect a pair of nearby nanoconstrictions and to define the electrodes. The unprotected Nb is removed by 2 min 30 s SF6 RIE.

The sample was placed in a cryogen-free cooler RDK-101DL (Sumitomo Heavy Industries, Ltd.) providing the base temperature of 2 K. The leads were thermalized by passing them through copper powder RF radiation filters, filled with a fixture of Stycast epoxy and Cu particles.¹⁸ 

The current bias of the sample was set by taking an ac voltage, U, from a high precision source DS360 and applying it to the sample connected in series with a standard resistor of R_st = 1 kΩ [see Fig. 1(d), inset]. Such a circuit will be referred to as the “DS360 circuit.” The sample resistance was much lower than the standard resistor. The lowest frequency was 10 Hz, low enough so that further reduction of the frequency would not change the shape of the voltage pulses. Yet it was possible to push the frequency up to 50 kHz and still obtain reliable reading of the memory states. The voltages on the sample, V, and on the resistor, V_st, were measured using National Instrument data acquisition card NI-DAQ USB-6216. The current in the circuit, I, was calculated as I = V_st/R_st. The voltages on the sample and the resistor were amplified using low noise differential preamplifiers SR560 Stanford Research Systems, before being supplied to the DAQ card. In some cases, a modified circuit was used, which will be called the “DAQ card circuit.” This circuit is exactly the same as the “DS360 circuit,” except that the voltage, needed to generate the bias current, was taken from the outputs of the same card NI-DAQ USB-6216. In the latter case, the experiment was controlled using Python code. In each measurement presented below, we will specify the type of the circuit and the frequency.

The temperature dependence of the resistance (R = V/I) of the sample is shown in Fig. 1(d). There are two curves on the graphs: one is taken at low bias current (the red curve), which does not impact the shape of the curve significantly, while the other (blue) is taken at a much higher current, which was smaller but of the same order as the critical current of the nanobridges. The first curve shows the true temperature dependence and confirms that nanobridges have the same critical temperature as the film. However, since they have a much lower critical current (since they are much narrower than the film), the curve taken at a higher bias current shows two transitions. This R-T curve shows that the normal resistance of the film was ∼85 Ω and the normal resistance of the nanobridges was ∼15 Ω. Taken the dimensions of the nanobridges (20 nm by 15 nm), we estimate the resistivity 9 μΩ cm, which is a typical value for the Nb thin film.¹⁹ 

The voltage vs current curve (“I-V curve”) is shown in Fig. 1(e). It exhibits two different switching currents of the order of 1 mA (only one critical current is observed in each sweep though). There were two possible switching currents on the positive side, indicating that the system could be in two possible states. The same is true for the negative side of the I–V curve. The positive and negative switching currents were approximately equal but not exactly equal, i.e.,

The origin of the two switching currents, as will be discussed later, is the possibility of different integer values of the winding number of the superconducting condensate wave function defined on the loop formed by the two nanobridges. This winding number will be used to store information. It should be emphasized that if the curve would be measured just one time, then it would show just one value of the critical current. Yet if the bias current is cycled many times, as is the case in Fig. 1(e), then the multivalued I-V curve, having two switching currents, emerges. The I-V curve also shows hysteresis, and the re-trapping current appears much lower than the switching current. We explain this by Joule heating. Note that the voltage observed after the switching is of the order of 15 mV, which is in agreement with the normal resistance of the nanobridges estimated from the R-T curves (see above).

We have also tested the temperature dependence of the critical currents (“switching currents”) [Fig. 2(a)]. It appears that the distinction between the two critical currents becomes smaller and almost disappears at ∼3.2 K. Since the distinction between the critical currents will be used to determine the winding number of the loop, the temperature has to be substantially lower than ∼3.2 K for the memory to function reliably.

The fluctuations of the switching current have also been measured [Fig. 2(b)]. It is clear that the standard deviation is of the order of 1 μA, which is much smaller than the difference between the two critical currents (∼0.1 mA). Thus, these fluctuations cannot cause the memory switch between the states.

Figure 3 shows the dependence of the switching current on the perpendicular magnetic field. The function is periodic and multivalued. Each branch of this periodic function represents a certain vorticity of the memory loop, or, in other words, the winding number of the order parameter, or, in other words, the number of fluxoids trapped in the loop.^3,6,22 This number will be denoted as n_v. The observed periodicity shows that vortices do not sit in the nanobridges themselves but enter the space between the bridges. Also, it shows that the vortices enter the loop in a periodic manner as the magnetic field is increased. The key observation is that the function is multivalued even at zero field. Thus, we conclude that two vorticity states are possible at zero field. These states can be used to store one bit of information. Below, we will discuss how to switch the system between the two stable vorticity states by the bias current, without applying external magnetic field. Generally speaking, this will be possible because a state with a fixed number of vortices in the loop (n_v) has different positive and negative critical currents due to the fact that the bridges are not identical (asymmetry).

The reason that the switching current has two possible values at zero magnetic field is that the system can have vorticity zero (n_v = 0) or a unit vorticity (n_v = 1), which is realized if a vortex is trapped in the loop.⁶ As the bias current is applied, it is added to the persistent current in the loop. Therefore, the observed switching current is lower in the case n_v = 1.

The main question is how to switch the system between the states without applying the external magnetic field. Our method is as follows. We apply a control current I₀ = (I⁺_sw1 + I⁺_sw2)/2 and measure the voltage. If the voltage is zero, that means n_v = 0. These memory states are considered logical zero (mem = 0). If the voltage is not zero, then the bias current is reduced to zero and increased again to the value I₀. Again, if the voltage is zero, then the logical zero state is considered written (mem = 0). This cycle is repeated until the voltage is zero when the current I₀ is applied. Since the process is stochastic, each time we apply current and reduce it to zero the probability that the desired state is established is roughly 50%. To test the effectiveness of this procedure, we have made 12 500 measurements. The results are shown in Fig. 4(a). The plot shows the distribution of the number of attempts needed for the creation of the state mem = 0 after the memory eraser. In 50% of cases mem = 0 obtains from the first attempt, in 25% of cases two attempts are needed, in 12.5% cases three attempts are needed, etc. Therefore, for example, if one requires a confidence of 10⁻⁶, then one needs to cycle the current 20 times. If the frequency of the pulses would be set at a high value, say 10¹⁰ s⁻¹, then the time needed to create the desired memory state would be 5 × 10⁻⁸ s.

To write the state mem = 1, a similar procedure is used, but the applied current is negative, namely, I₁ = (I⁻_sw1 + I⁻_sw2)/2. Note that here the switching currents are negative, I⁻_sw1 < 0 and I⁻_sw2 < 0.

To read out the state of the memory, we always apply the current I₀ = (I⁺_sw1 + I⁺_sw2)/2 and measure the voltage on the device. If the measured voltage is zero, then the state was mem = 0; if the voltage is a few mV, then the state was mem = 1 before the measurement. The state is destroyed if mem = 1 is measured, since in this case, the system switches into the normal state and the order parameter is destroyed. By repeating the critical current measurement many times, we can plot distributions as shown in Figs. 4(b)–4(d). The top distribution [Fig. 4(b)] was measured without preparing the sample state in any way. Thus, a random sequence of the critical currents I⁺_sw1 and I⁺_sw2 was measured. The corresponding distribution (black) shows two peaks due to the fact that the sample can be found in two different vorticity states, n_v. Different vorticity states have different values of the persistent supercurrent. Thus, they impact differently on the critical current of the device.

Next, we perform a test in which the vorticity state is set to n_v = 1 (mem = 1) before each measurement of the switching current. In this state, the system shows the lower critical current I⁺_sw1 at the positive bias and the higher critical current, I^-_sw2, at the negative bias. Note that |I^-_sw2|>|I⁺_sw1|. The corresponding distribution, measured at positive bias currents, is shown by the red bars in Fig. 4(c). The distribution shown by the blue bars [Fig. 4(d)] was measured in a similar way, but the state of the memory was mem = 0 (n_v = 0) before each measurement of the switching current. The key observation from Figs. 4(b)–4(d) is that it is possible to select the desired state of the memory and the distribution becomes a well-defined single peak, with only one error out of about 200 000 measurements.

The measurement of Fig. 5(a) illustrates the operation of the memory. [Note that the plots in Fig. 5(c) represent a different algorithm, which will be explained later.] In Fig. 5(a), we first write the memory state, then read it out to verify that the state is still the same as was written. The sequence of written states was 0000–1111-0000–1111, etc. Let us remind that the term “write mem = 0,” here as always, means to cycle the bias current between zero and I₀ until we detect zero voltage at I₀=(I⁺_sw1 + I⁺_sw2)/2. Similarly, the term “write mem = 1,” here as always, means to cycle the bias current between zero and I₁=(I^-_sw1 + I^-_sw2)/2 < 0 until we detect zero voltage at I₁. After each state from the sequence was written, the memory state was read out. For the readout, the current was set to I=I₀ and the voltage was measured. It the voltage is zero, then mem = 0, and if the voltage is high, then mem = 1. (In the latter case, the reading procedure destroys the memory state.) Figure 5(a) clearly shows that the resulting sequence of readout states is exactly the same as the sequence of the written states. Within this example, a total of 25 write-read cycles is performed and no errors observed. If the test is continued for 100 000 write-read cycles, then we find a few errors. Thus, the error rate is of the order of 10⁻⁵.

The two types of error rates (write-0-read-1 error rate, w0_r1, and write-1-read-0 error rate, w1_r0) were calculated by dividing the error number by the number of measurements [Table I; Fig. 5(b)]. The total error rate, Err_tr, is calculated by dividing the sum of the two types of errors by the total number of measurements, N, which was typically N ∼ 300 000.

At higher frequencies (∼10 kHz), the “DS360 circuit” was used. The generator output was exactly periodic, i.e., no “read” and “write” algorithm defined above was possible when the generator DS360 was used. The error rates have been determined by applying a sequence of current-bias square pulses, switching between the positive limit I₀ and the negative limit I₁ < 0. The result is shown in Fig. 5(c). In this case, we show the voltage on the sample (red) and the voltage on the standard resistor (blue) vs time. The current is proportional to the voltage on the standard resistor. In some cases, such circuit performs non-demolition measurements (when the detected voltage is zero), and only such measurements have been used as starting points of the error-evaluation cycles. More specifically, if the current was positive and the sample voltage was zero, the state was assumed mem = 0. Then, the current switched to the negative bias. If the measured voltage was high, then it was concluded that mem = 0, so, there is no error. If, on the other hand, the voltage remained zero even when the current changes its polarity to negative, then the readout value was mem = 1, so we counted this event as an error event. Thus, we tested the error rate w0_r1. Analogously, the other error rate, w1_r0, was also tested. The resulting total error rate was 2.3 × 10⁻⁵ for the 10 kHz memory switching rate and 3.2 × 10⁻⁵ for the 50 kHz switching of the memory. In the latter case, the error was higher due to the top speed limit of the DAQ card.

The dissipated power, P, can be estimated as P∼(I⁺_sw1 + I⁺_sw2)·V/2, i.e., a typical switching current multiplied by the voltage, V, occurring during the switching event, when the wire enters the normal state. The switching current depends on temperature, so the estimated power is different for different temperatures. Namely, P ≈ 5 μW at T = 2.1 K, and P ≈ 1 μW at T = 3.2 K. The dissipated energy can be estimated as the dissipated power divided by the number of switching events per second. At the maximum tested rate, f = 50 000 s⁻¹, the energy per one switching event is, therefore, E∼P/f = 10⁻¹¹ J at T = 3.2 K (taking into account that there are two switching events per cycle). The dissipated energy can be strongly reduced if narrower or much narrower voltage pulses are used in future realizations of such devices. Also, the switching current and correspondingly the dissipated energy can be further reduced if the bridges are made narrower.

The error rate in our devices is of the order of 10⁻⁵ or less. It is instructive to compare this to the commercial memory devices. For example, according to Ref. 20, the raw bit error rate (RBER) in new NAND flash memories was 10⁻⁹–10⁻⁸. After 10 000 cycles, the RBER increased to 10⁻⁷–10⁻⁶. These values represent the raw error rate. When an error correction was employed, the rate became much lower.²⁰ Our devices do not have any error correction mechanism, but it could be implemented in more advanced realizations. The advantage of the superconducting nanowire devices is that the RBER does not depend on the number of cycles, unlike in NAND memories.

In conclusion, we present a superconducting kinetic inductance memory (“SKIM element”), which can operate at temperatures as high as ∼2.8 K, in a cryogen free cooler. The SKIM element is made of only superconducting materials, containing no normal-metal dissipative elements or ferromagnetic inclusions. Our SKIM was tested at frequencies of up to ∼50 kHz, the frequency being limited by the setup. The SKIM memory shows a low error rate (∼10⁻⁵). This nonvolatile memory device stores information in a form of single flux quanta. Thus, in principle, just one phase slip in one of the nanowires would be sufficient to switch the memory from one state to the other. Such a regime is not yet realized but could be achieved if very narrow current pulses are applied to the device. In the future, the system can be coupled to a microwave readout system, thus increasing the rate drastically. Our next goal is to integrate such elements into an array. For this, a horizontal array of “bitlines,” composed of multiple chains of such memory elements, will be crossed by an array of “wordlines,” which will be superconducting wires able to create magnetic fields. The current in a bitline will be set slightly below the critical current so it cannot switch by itself. Then, the switching will occur only at the crossing point of the current-biased wordline and the current biased bitline, where the magnetic field will help the cell to switch.

This study was supported by the U.S. Army (United States Army) Grant No. W911NF-18-1-0117.