Due to their unique properties as lossless, nonlinear circuit elements, Josephson junctions lie at the heart of superconducting quantum information processing. Previously, we demonstrated a two-layer, submicrometer-scale overlap junction fabrication process suitable for qubits with long coherence times. Here, we extend the overlap junction fabrication process to micrometer-scale junctions. This allows us to fabricate other superconducting quantum devices. For example, we demonstrate an overlap junction-based Josephson parametric amplifier that uses only two layers. This efficient fabrication process yields frequency-tunable devices with negligible insertion loss, a gain of 30 dB, and quantum limited noise performance. Compared to other processes, the overlap junction allows for fabrication with minimal infrastructure, high yield, and state-of-the-art device performance.

Superconducting electronics have experienced rapid growth over the last decade. Advances in quantum information processing based on superconducting qubits have fueled much of this growth. Improvements in design, materials, development of quantum-limited amplifiers, and the implementation of low-loss superconducting components are some of the pillars supporting progress in the field.

Fundamental building blocks of superconducting quantum circuitry include discrete components, e.g., capacitors, inductors, and Josephson junctions (JJs), as well as distributed element resonators. Modern microfabrication technology allows for the realization of these circuit elements with infrastructure that typically includes optical lithography techniques and metal/dielectric deposition. The JJs, formed by two superconducting electrodes separated by a thin tunnel barrier, play a central role in superconducting quantum circuits. The lossless, nonlinear inductance is the most salient property of these JJs, which render JJs indispensable circuit elements for superconducting qubits and quantum-limited amplifiers.

There are various methods to realize JJs. These include subsequent layer removal of deposited superconductor-insulator-superconductor (SIS) tri-layers (i.e., the “trilayer process”),1,2 shadow evaporation (e.g., the Dolan-Bridges and Manhattan geometries),3,4 and the overlap-junction technique.5–7 The trilayer process, typically used for superconducting electronics, involves many steps and significant infrastructure for different etches and both metal and dielectric deposition/patterning. On the other hand, shadow evaporation has become the norm for qubit JJs because they can be made very small with a single electron beam (e-beam) lithography step. This minimizes infrastructure and has enabled generations of researchers to make nano-scale quantum devices at the cost of scalability. However, with modern optical lithography that extends down to nanometer dimensions, this has become a moot point. Overlap junctions now allow access to a full range of simple fabrication from micro- to nano-scale dimensions. This opens efficient wafer-level fabrication of JJs with high dimensional control and a wide range of applications.

Here, we develop low-critical-current JJs and demonstrate a simple process for micrometer-scale junctions. We describe the process bias and measure the current-voltage (I-V) characteristics of the resulting junctions. This enables the realization of a wide range of superconducting devices. In particular, we demonstrate the fabrication and characterization of important devices for the field, Josephson parametric amplifiers (JPAs), which use only two steps of photolithography.

As shown in Fig. 1, the process is started by depositing ∼200 nm Al onto a 76 mm (3 in.) intrinsic Si wafer with native oxide in an e-beam evaporation chamber at a base pressure of ∼2.7 × 10 −5Pa. In the first step of photolithography, the desired pattern for the bottom-electrode (BE) layer is formed using an ∼1-μm-thick positive photoresist (PR), Megaposit SPR 660–1.0M, on the Al deposited wafer.8 The pattern is exposed through a photomask, i.e., reticle, in a 5:1 reduction stepper and developed in a tetramethylammonium hydroxide (TMAH) based solution [Fig. 1(a)]. The pattern is then transferred onto the Al film by agitating the wafer in a solution of Transene aluminum etchant—type A for ∼28 s heated to ∼50 °C [Fig. 1(b)].8 The total etching time includes an over-etch of ∼10 s to ensure complete removal of Al in developed regions (unprotected by the PR). The remaining PR is stripped in a commercial NMP-based solvent (Remover PG) heated to ∼70 °C.8 

FIG. 1.

Fabrication steps for the micrometer-scale overlap junction process. (a) 3D sketch of the Si substrate after deposition of the bottom Al layer followed by patterning the PR layer. (b) After etching of the Al bottom layer with etchant and stripping of the PR layer. A native surface oxide forms on the bottom Al electrode. (c) After coating with a thin protective PMMA layer. (d) A bi-layer of PR/LOR is patterned in a second lithography step to define the pattern of the TE. The thin protective PMMA layer is removed by O2 ashing at room temperature. (e) The native oxide on the bottom Al electrode surface is removed by Ar RF-plasma cleaning. (f) Ultrahigh-purity grade low pressure O2 is used to form a controlled AlOx tunnel barrier. (g) The TE is formed by subsequent Al evaporation. (h) Metal-liftoff in solvent completes the overlap junction process. (i) A cross-sectional view of the junction along the dashed line in panel (h) of this figure.

FIG. 1.

Fabrication steps for the micrometer-scale overlap junction process. (a) 3D sketch of the Si substrate after deposition of the bottom Al layer followed by patterning the PR layer. (b) After etching of the Al bottom layer with etchant and stripping of the PR layer. A native surface oxide forms on the bottom Al electrode. (c) After coating with a thin protective PMMA layer. (d) A bi-layer of PR/LOR is patterned in a second lithography step to define the pattern of the TE. The thin protective PMMA layer is removed by O2 ashing at room temperature. (e) The native oxide on the bottom Al electrode surface is removed by Ar RF-plasma cleaning. (f) Ultrahigh-purity grade low pressure O2 is used to form a controlled AlOx tunnel barrier. (g) The TE is formed by subsequent Al evaporation. (h) Metal-liftoff in solvent completes the overlap junction process. (i) A cross-sectional view of the junction along the dashed line in panel (h) of this figure.

Close modal

In the second photolithography step, a metal liftoff resist (LOR) process was used [Fig. 1(c-i)]. An ∼1-μm-thick imaging PR layer (Megaposit SPR 660–1.0M) on top of an ∼540-nm-thick LOR layer (LOR 5A) comprises the bi-layer PR stacking.8 Since TMAH etches Al, an ∼200-nm-thick polymethyl methacrylate (PMMA) protective layer was applied, before the bi-layer PR stacking, to protect the BE Al layer from the PR developer. This process yields an undercut profile of ∼0.7 μm after photo-exposure and development, resulting in a clean metal liftoff.

The subsequent steps shown in Figs. 1(d)–1(f) are critical for the precise definition of the tunnel barrier area. Before the wafer is loaded into the high vacuum e-beam evaporator, it is subjected to room-temperature O2 plasma ash (100 W for 3 min) at a pressure of ∼67 Pa [Fig. 1(d)]. This step removes PMMA and other organic residues in the developed regions of the wafer. Next, the wafer is loaded into the high vacuum deposition chamber and argon RF-plasma cleaning is employed to remove the native oxide on the patterned bottom Al layer as described in an earlier work.7 This cleaning is carried out by applying RF power to an electrically isolated wafer holder that is water cooled. Typically, an RF power of 50 W is applied for ∼1 min at room temperature; the argon pressure is maintained at ∼1.3 Pa [Fig. 1(e)]. An AlOx tunnel barrier is formed by controlled oxidation of the cleaned Al surface [Fig. 1(f)]. The oxidation is carried out by pumping out and sealing the chamber and then introducing ultra-high purity grade (99.999%) O2 into the chamber. The oxidation dose is tuned by adjusting the oxidation time and the oxidation pressure.9,10 The overlap junction is completed by depositing 350 nm Al as the top-electrode (TE) using e-beam deposition [Fig. 1(g)]. The TE is created by liftoff in solvent with ultrasonic agitation [Fig. 1(h-i)].

An important step in fabricating tunnel junctions is the oxidation step [Fig. 1(f)]. In our studies, we explored three different oxidation doses to vary the Josephson junction tunnel resistance (hence, critical current) by nearly two orders of magnitude. The oxidation doses explored were 4 min at ∼40 Pa, 36 min at ∼40 Pa, and 36 min at ∼100 Pa.

In order to design wafer-scale lithography patterns, it is necessary to understand the dimensional process biases and apply those to the drawn dimensions. In addition, for devices that are oxidized in situ after argon cleaning, it is also necessary to include intrinsic process bias. These may be due to, e.g., inhomogeneous junction cleaning, oxidation, and extended edge profiles. To accomplish this, we plot and fit the room-temperature junction resistance R as a function of both the drawn and the measured dimensions of the junctions. Making use of optical microscopy, we determined that the fabrication process yields actual dimensional biases of a=+0.47±0.03μm and b=1.92±0.05μm for the TE and BE, respectively. These reflect the fact that the top layer is additive and the bottom is subtractive. For the R vs electrode width fits, we start from R×A=c (where A is the junction area and c is a constant dependent on oxidation dose). To fit using the drawn areas, we can write

R=c(WTDrawn+a)×(WBDrawn+b).
(1)

Here, a and b correspond to only dimensional bias and WTDrawn (WBDrawn) is the drawn width of the top (bottom) electrode. The dimensional bias may be expected to correspond to the optically measured values if there is no intrinsic bias. However, as shown in Table I and discussed below, we see that the fit bias for the BE is significantly smaller than the measured value, while they match fairly well for the TE. A fit using the measured dimensions helps to understand this; since the actual widths of the TE and the BE are known, we can fit it using only two parameters,

R=cWTMeasured×(WBMeasured+2λ),
(2)

where c is the oxidation constant, while the parameter λ includes intrinsic effects.

TABLE I.

Oxidation dose and fitting results for models based on measured and drawn dimensions.

Oxidation doseDrawn dimensions modelMeasured dimensions model
P (Pa)t (min)c(Ωμm2)a(μm)b(μm)c(Ωμm2)λ(μm)
100 36 1634 ± 45 0.40 ± 0.03 −0.11 ± 0.09 1727 ± 42 0.96 ± 0.05 
40 36 1087 ± 55 0.34 ± 0.06 −0.19 ± 0.17 1198 ± 38 1.01 ± 0.07 
40 382 ± 20 0.70 ± 0.08 0.28 ± 0.19 333 ± 9 0.92 ± 0.07 
Oxidation doseDrawn dimensions modelMeasured dimensions model
P (Pa)t (min)c(Ωμm2)a(μm)b(μm)c(Ωμm2)λ(μm)
100 36 1634 ± 45 0.40 ± 0.03 −0.11 ± 0.09 1727 ± 42 0.96 ± 0.05 
40 36 1087 ± 55 0.34 ± 0.06 −0.19 ± 0.17 1198 ± 38 1.01 ± 0.07 
40 382 ± 20 0.70 ± 0.08 0.28 ± 0.19 333 ± 9 0.92 ± 0.07 

Resistance data were acquired for the three different oxidation doses and plotted vs electrode widths, where first WB was varied with fixed WT and then WT is varied with fixed WB (Fig. 2). For Figs. 2(b) and 2(c), data for drawn vs measured widths are plotted using solid and open symbols, respectively. Each data point in Figs. 2(b) and 2(c) represents the statistical average of 10 individual resistance measurements of nominally identical junctions across a die. Measurements from two dies across the wafer are included for a given oxidation dose. For the various oxidation doses, we performed fits where WB is varied in Fig. 2(b) and WT is varied in Fig. 2(c). The dashed and solid lines in Figs. 2(b) and 2(c) show the fits using models based on measured [Eq. (2)] and drawn [Eq. (1)] electrode dimensions, respectively. The fitting results are summarized in Table I.

FIG. 2.

Room temperature junction characterization. (a) Optical microscope image of a typical micrometer-scale overlap junction is shown on the left of the panel. A drawing of the cross section is presented on the right side. (b) Junction resistance R vs WB at different oxidation doses as indicated on the plot. (c) Junction Resistance R vs WT. Error bars are smaller than the symbol size.

FIG. 2.

Room temperature junction characterization. (a) Optical microscope image of a typical micrometer-scale overlap junction is shown on the left of the panel. A drawing of the cross section is presented on the right side. (b) Junction resistance R vs WB at different oxidation doses as indicated on the plot. (c) Junction Resistance R vs WT. Error bars are smaller than the symbol size.

Close modal

For the resistance vs measured width fits, we see that the intrinsic process bias on the bottom electrode, 2λ2μm, accounts for the missing process bias in the parameter b in the fit for the drawn dimensions. This could explicitly be accounted for in Eq. (1) by using

bb+2λ.
(3)

Note that λ is significantly larger than the BE thickness. Two possible explanations for this are that (a) the edge profile is curved due to wet etching, which yields a length that is longer than the BE thickness, and (b) RF plasma cleaning is localized toward the film edges, and hence, the edges are more electrically transparent than the top surface. This is by no means detrimental to the fabrication process and is easily accounted for in process bias or by extending the RF clean cycle time.11 

The fitting parameter c is a measure of normal resistance of the junction and is, therefore, proportional to the effective oxidation dose, given as tα×Pβ, where t and P are the oxidation time and pressure, respectively. From the results presented in Table I, α=0.58 and β=0.40 (α=0.48 and β=0.44) based on measured (drawn) dimensions. This result is in good agreement with accepted values in recent studies,9 illustrating that the oxidation process is not significantly altered by the air exposure and subsequent RF plasma cleaning step.

We next discuss the low temperature (130 mK) characteristics of the micrometer-scale overlap JJs. The current–voltage (I–V) characteristics are measured by driving current from a low-noise current source and measuring the voltage across the junction with a voltage pre-amplifier.

The measured I–V curve for a JJ with RN=7.3Ω exhibits clear hysteresis (Fig. 3). We measure a superconducting gap 2Δ/e=337μV, in agreement with values expected for Al.12 We observe a critical current (Ic) of ∼30 μA and a retrapping current of ∼0.4 μA, indicative of high-quality JJ. The measured Ic is slightly lower than that is expected (∼36 μA) from the Ambegaokar-Baratoff (A-B) formula at T = 0 K.13 This is not surprising because the A-B formula is derived for an ideal uniform tunnel barrier and sets an upper limit for the maximum critical current. However, for an actual JJ, defects due to interface roughness, crystal and grain structures, impurities, and processing conditions may all lead to suppression of the critical current.14,15

FIG. 3.

Low temperature characterization of a single Josephson junction. WB=2.18μm. The normal state resistance RN=7.3Ω is determined by a linear fit outside the hysteretic regions of the I–V curve. The measured superconducting gap is 2Δ/e=337μV.

FIG. 3.

Low temperature characterization of a single Josephson junction. WB=2.18μm. The normal state resistance RN=7.3Ω is determined by a linear fit outside the hysteretic regions of the I–V curve. The measured superconducting gap is 2Δ/e=337μV.

Close modal

As a concrete and useful application of these JJs, we designed and fabricated JPAs around the overlap process. This process offers a method for making overlap JPAs (O-JPAs) reliably and with far fewer resources than are typically employed. Early research on JPAs dates back several decades.16–18 More recently, JPAs have been employed as indispensable tools for quantum information processing due to their ability to amplify small microwave signals with ultralow added noise. We refer to the literature for various implementations and design aspects of JPAs.19–22 

Here, we implement an O-JPA design, which is composed of a capacitive element in parallel with a non-linear inductor [Fig. 4(a)].20 The inductance is provided using a tunable superconducting quantum interference device (SQUID) array with inductance Ls that is grounded on one end. For this device, eight nominally identical SQUIDs, with a junction inductance of Lj0.5 nH, provide a minimum Lsmin=2.05 nH [inset of Fig. 4(a)]. An interdigitated shunt-capacitor, Cs = 396 fF, is connected in parallel with the SQUID array to ground. The resulting lumped-element resonator is coupled to a coplanar waveguide (CPW) transmission line with a coupling capacitor Cc = 90 fF. The capacitors were made by etching a 2-μm-wide trench between metal fingers.

FIG. 4.

Physical layout and characterization of overlap junction-based JPA. (a) The O-JPA is configured to be a lumped element LC resonator using an interdigitated capacitor (Cs = 396 fF) and a series array of eight nominally identical SQUIDs with minimum Lsmin=2.05 nH as a tunable inductor. The lower right inset shows the SQUID with 2.1×2.2μm2 overlap junctions. (b) Gain vs Frequency of O-JPA driven by an RF pump at 5.06 GHz. The inset shows frequency tunability as a function of external magnetic flux.

FIG. 4.

Physical layout and characterization of overlap junction-based JPA. (a) The O-JPA is configured to be a lumped element LC resonator using an interdigitated capacitor (Cs = 396 fF) and a series array of eight nominally identical SQUIDs with minimum Lsmin=2.05 nH as a tunable inductor. The lower right inset shows the SQUID with 2.1×2.2μm2 overlap junctions. (b) Gain vs Frequency of O-JPA driven by an RF pump at 5.06 GHz. The inset shows frequency tunability as a function of external magnetic flux.

Close modal

The O-JPA is designed to have an unbiased resonance frequency of fres5.05 GHz with a quality factor of QTotal32.23 It is operated as a single port device in reflection mode. A circulator is used to separate the input signals (strong RF pump and weak RF signal) from the reflected output signals (idlers and amplified RF signal).

Initial tests of the O-JPA in an adiabatic demagnetization refrigerator (T < 100 mK) are shown in Fig. 4, with the resonant frequency vs SQUID bias in the inset of panel (b). The inductance of the SQUID array is tuned by applying an external magnetic flux to the SQUID loops by running a DC through a coil placed nearby. This provides a frequency tunability of ∼3–5 GHz. A gain of more than 25 dB with a bandwidth of about 7 MHz is centered at 5.06 GHz. It is possible to engineer a wider bandwidth at the expense of lower gain.

Cavity decay measurements at the base temperature of a dilution fridge (23 mK) allowed the initial estimate of noise in O-JPAs.24 The decay of an ultra-high finesse cavity at 5 GHz was measured using an O-JPA, operated at a gain of 17 dB. The O-JPA was followed by a high-electron-mobility-transistor (HEMT) amplifier with 2.4 K thermal noise. The signal-to-noise ratio improved by 11 dB when the O-JPA is turned on, indicating near quantum limited noise performance for our O-JPA.

We further investigate the gain and noise temperature of the O-JPA in a dilution refrigerator by performing an Y-factor analysis on a different sample from the one described above. The procedure for noise characterization is detailed in the supplementary material and further described in Ref. 25. For this sample, we observe gain in excess of 25 dB centered around the pump at 6340 MHz, with the lowest JPA noise temperature of 0.40.2+0.1 K at a gain of 21 dB obtained at 6330 MHz. The error bounds represent uncertainties in the insertion loss of the coaxial components and statistical uncertainty. This noise temperature agrees with the quantum limit of 0.30 K.

In conclusion, we developed a simple two-step process to realize micrometer-scale overlap JJ devices. The process requires minimal infrastructure compared to typical processes. The geometry, process, and oxidation dose are outlined, and we show how to determine the process bias. We characterized the I–V curves of the JJs. We used this information to design and fabricate an ultra-low noise O-JPA with over 25 dB of gain and quantum limited noise performance.

See the supplementary material for more information on noise temperature calibration of O-JPA.

We acknowledge support from the NIST Quantum Measurements Initiative, the U.S. Department of Energy (Award No. de-sc0019199), and the National Science Foundation (Grant No. 1839136). R. Lake was supported by the NIST NRC Research Postdoctoral Associateship during the work at NIST. We are very grateful for helpful discussions with H.-S. Ku, X. Wu, G. Hilton, K. Lehnert, M. Malnou, and D. Palken during the initial stages of JPA design.

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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Supplementary Material