Short-channel robustness from negative capacitance in 2D NC-FETs

For decades, low-power digital technologies have been realized using silicon-based metal-oxide-semiconductor field-effect transistors (MOSFETs) that have followed Moore's law, enabling an exponential increase in functionality by scaling down the transistor size to increase transistor density on a chip. However, decreasing the size of transistors has become increasingly difficult due to short-channel effects (SCEs) and increasing power consumption.^1,2 These challenges can potentially be resolved by reducing the subthreshold swing (SS) in MOSFETs below the 60 mV/decade thermal limit at room temperature, thus enabling low-voltage operation. Negative capacitance field-effect transistors (NC-FETs)^3,4 have the potential for reducing the SS by adding a ferroelectric (FE), such as doped hafnium oxide,^5–7 to the gate stack of an otherwise traditional FET.^8–13 

The use of low-dimensional channel materials, including 2D transition metal dichalcogenides [(TMDs), such as molybdenum disulfide (MoS₂)], can also enable miniaturization of transistors thanks to sub-nm thinness to enhance electrostatic control of the channel.^14,15 Bringing together the benefits of sub-thermal switching from the NC effect with the electrostatic scalability of 2D material-based channels offers a device of great potential significance for future technologies. NC-FETs with 2D channels (2D NC-FETs) were first demonstrated using a ferroelectric polymer in the gate stack¹⁶ but have since been studied with a variety of gate stacks based on doped hafnium oxide ferroelectric films.^17–20 To date, the behavior of long-channel 2D NC-FETs has been widely explored; however, the impact of NC on SCEs in 2D NC-FETs has received little attention. While all of the proper motivation is in place regarding the anticipated scalability of 2D NC-FETs, the complexity of the fields in such a capacitively dependent device suggests the need for more careful consideration of the impact of scaling.

Experimental evidence from Si-based NC-FETs confirmed that SS improvement becomes pronounced at shorter channel lengths.^21–23 Other studies propose NC-FET operation will be significantly impacted by the reduction of channel potential at short channel lengths,^24,25 which could have unique implications for ultrathin 2D channels. However, understanding of how the NC effect influences short-channel behavior in 2D NC-FETs has yet to be examined experimentally. Recently, a study experimentally reported that the SS of a top-gated MoS₂ NC-FET with a polymeric FE drastically degraded with extreme channel length scaling.²⁶ Hence, further experimental studies are needed to ascertain if the NC effect can be beneficial for alleviating SCEs in the unique electrostatic environment of 2D NC-FETs.

In this work, we experimentally demonstrate 2D NC-FETs using MoS₂ with CMOS-compatible hafnium zirconium oxide (HZO) as the FE. With a bottom-gated structure, 2D FETs are directly compared with 2D NC-FETs having the exact same gate stack (without annealing to drive ferroelectricity in HZO for the 2D FETs) across gate lengths ranging from 80 nm down to 20 nm. The 2D NC-FETs not only exhibit more robustness when scaled to ∼20 nm channel lengths, but they actually show marked improvement in the SS and on/off-current ratio as the device is scaled—an unanticipated fallout of the unique fields in the NC-based device. The mechanisms behind this observed improvement in scaling behavior for 2D NC-FETs are discussed and analyzed, providing important forecasting for the potential of these devices in future scaled technologies.

The device structure of the 2D NC-FETs studied in this work is shown in Fig. 1(a) and includes a gate stack based on previous results,¹⁸ which reported a more stable switching behavior under changing drain-source bias (V_ds) when using Al₂O₃ as the dielectric at an equal thicknesses of 10 nm with the FE HZO.²⁷ Gate stack characteristics were obtained using FE capacitors of 10 nm HZO/10 nm Al₂O₃ grown using atomic layer deposition (ALD) on p⁺⁺ Si wafers with top Pt electrodes, which were annealed at 550 °C for 30 s in an Ar ambient [Fig. 1(e)] to drive the crystal transition in the HZO that yields ferroelectric properties. Transistors were fabricated by transferring MoS₂ onto the wafer and forming source/drain contacts (20 nm Ni). Thicknesses of the MoS₂ flakes were 1–2 nm. Channel lengths (L_ch) were confirmed using scanning electron microscopy (SEM) imaging, from 20 to 80 nm [Figs. 1(b) and 1(c)]. The 2D FET devices fabricated for comparison followed the same process flow, including the same ALD-formed gate stack, but without the annealing so that the HZO film did not exhibit FE behavior [Fig. 1(e)].²⁸ All devices were electrically characterized using the same measurement conditions as previous publications in the field for consistency.¹⁷ 

A comparison of the 2D NC-FET and 2D FET devices both at a short channel length of 30 nm reveals significant improvement in subthreshold behavior, including the SS and hysteresis, in the 2D NC-FET [see Fig. 1(d)]. The steeper SS of the 2D NC-FET is attributed to the enhancement of capacitance through appropriate matching between the positive device capacitance (C_dev > 0) and the negative differential capacitance of the FE (C_FE < 0); however, this is analyzed further below. Particularly important in investigating the performance of NC-FETs is the capacitive network in the device, where an effective capacitance matching with the FE is an indication of better gate-control. To achieve stable sub-thermionic operation in NC-FETs, it is crucial that the gate stack capacitance is designed to be larger than C_dev, where the negative C_FE compensates the positive capacitances in the device.²⁹ 

Regarding this comparison between the 2D NC-FET and 2D FET (where the only difference is an anneal performed on the HZO/Al₂O₃ gate stack for the NC-FET), it is acknowledged that there are several features these devices do not share in common. First and foremost, the anneal yielded ferroelectric behavior in the HZO compared to standard dielectric polarization in the unannealed stack. Second, and related to the first point, the HZO undergoes a crystalline transition to the orthorhombic phase, which is a key aspect of yielding the ferroelectric behavior. Third, as a ferroelectric, the annealed HZO will exhibit a much higher relative permittivity compared to the unannealed HZO, which will by its very nature yield a gate stack with stronger gate coupling. Despite these differences, the comparison between these devices is still quite insightful as they share a common overall dimensional and design structure and material stack, minus the annealing step. What is more, it will be seen that the scalability of the 2D NC-FET actually defies conventional expectations, even with a higher permittivity gate stack, as the performance in terms of gate control actually improves with scaling of the gate length below 50 nm.

Polarization behavior of the annealed gate stack used in these 2D NC-FET devices [Fig. 1(e)] was tested by using the PUND (positive up negative down) method for excluding the impact of leakage current on the P–E curve. While testing, triangle waves of 1 kHz were applied. The P–E curve shows that remnant polarizations +P_r and −P_r are 1.60 and −3.23 μC/cm², respectively, which are lower than those of other works in the field,¹⁷ allowing for more effective match between the C_FE and the channel capacitance and resulting in lower hysteresis in these 2D NC-FETs. This phenomenon arises from the lower ferroelectric capacitance (low |dP/dE| near E = 0) for a given FE thickness due to the absence of the interfacial metal layer.^19,30

The effect of V_ds on the subthreshold behavior is shown in Fig. 2(a), which also shows a gate leakage current orders of magnitude less than the drain current (∼10⁻¹¹ A). An increase in V_ds from 0.1 V to 1 V causes the I_d-V_gs curve to shift in the negative direction—this is consistent with drain-induced-barrier-lowering (DIBL), widely observed in conventional n-type MOSFETs, where the threshold voltage (V_th) shifts negatively as V_ds increases. In some long-channel 2D NC-FETs, negative DIBL has been observed, which originates from the capacitance coupling from the drain to the interface between Al₂O₃ and HZO;¹⁹ this phenomenon is explained by an interfacial potential reduction when increasing V_ds. In the case of these short-channel 2D NC-FETs, particularly that shown in Fig. 2(a), it is clear that the more traditional lowering of the energy barrier in the channel from an increased drain field is overwhelming the potential reduction at the dielectric/ferroelectric interface—this is not surprising considering the physical thickness of the gate stack (20 nm total thickness) compared to the channel length.

The impact of the NC effect on MoS₂ device performance at scaled channel lengths is demonstrated by comparing the subthreshold curves of conventional 2D FETs with 2D NC-FETs at similar channel lengths (Fig. 3). The 2D NC-FETs clearly exhibit resilient scaling behavior compared to their 2D FET counterpart. As shown in Fig. 3(c), in 2D NC-FETs [where ΔSS/SS_LC denotes the difference between the SS at the current channel length to that of the longest channel device (ΔSS), divided by the SS of the longest channel device (SS_LC)], the minimum SS achieved decreases as the channel length scales down, i.e., scaling actually improved the switching behavior of the 2D NC-FET. Compared to the device with a channel length of 70 nm, the devices with channel lengths of 20 nm, 40 nm, and 50 nm have an SS that is 57%, 42%, and 37% lower, respectively. Additionally, the on/off-current ratio (I_ON/I_OFF) increases by 1–2 orders of magnitude when scaling the channel length from 70 to 20 nm [Fig. 3(d)]. The on-current is defined as the maximum value of the drain current from within the gate voltage sweep window (approximately −8 V < V_gs < 2 V), while the off-current is the minimum current from within the same sweep range. In contrast, the 2D FETs displayed a SS increase with shorter channel lengths, with the I_ON/I_OFF ratio decreasing by an order of magnitude when the channel length scaled from 80 nm to 30 nm. This phenomenon is most evident when scaling to extremely small channel lengths (∼20 nm). Due to the SCEs, which are typically seen in conventional devices, and based on the thickness of our gate stack (hence, the electrostatics), the device performance deteriorates when scaling the channel length down to sub-20 nm.³¹ 

Implications from the capacitive network [Fig. 2(b)] in the devices may be contributing to the improved scaling capability of the 2D NC-FETs. The gate stack capacitance can be expressed as²² 

Accordingly, it can be derived from this equation that a lower negative C_FE results in a larger C_stack, which implies stronger gate control.

The small-signal capacitance circuit shows that a 2D NC-FET can be regarded as an intrinsic 2D FET in series with an HZO FE capacitor. The Landau–Khalatnikov (LK) equation describes the electrical behavior of the HZO FE capacitor,³² and C_FE can be calculated using Landau coefficients:

where α, β, and γ are Landau coefficients and t_FE is the ferroelectric thickness. For a stabilized FE material with first-order phase transition, α, β < 0 and γ > 0.^25,33 It has been reported that reducing the channel length results in an increased inner fringing field that induces a larger |P_FE|.^24,33 This leads to a decrease in |C_FE| (C_FE being less negative) and an increase in C_stack when β is negative.³⁴ Thus, as coupling of inner fringing fields to the FE increases with scaling, short-channel devices exhibit enhanced potential amplification and gate control. Note that the back-gated device structure in these transistors is fully overlapping the source/drain contacts, so the coupling of the inner fringing fields across the FE is expected to be fairly uniform compared to devices without a fully overlapped source/drain structure—a distinction worthy of further exploration. On a side note, the appearance of ferroelectricity in nanometer-size ferroelectrics generally stems from the emergence of multidomain states,^35,36 which can over-respond to an applied charge, hence impacting the NC effect.³⁷ Studies can be conducted in the future to take the multidomain states into account for the scaling behavior observed in this study.

The results we observed for the subthreshold behavior in 2D NC-FETs can also be explained by the design principles in its small-signal capacitance circuit.¹⁹ The SS derived is

where k_B is the Boltzmann constant, T is the temperature, q is the elementary electronic charge, Φ_s is the surface potential in the channel, C_2D is the 2D semiconductor channel capacitance, and C_ox is the dielectric capacitance. As the channel length scales down, the SS decreases with the reduction of |C_FE|. The improvement in subthreshold behavior we demonstrated for short-channel 2D NC-FETs is consistent with the above derivation from the small-signal capacitance circuit.

Comparing the performance of the short-channel devices in this work to that of a previously reported top-gated MoS₂ NC-FET with HfO₂ (4 nm)/P(VDF-TrFE) (26 nm) gate stack layers highlights the pronounced improvement from this work.²⁶ In the top-gated devices, the transfer characteristics of channel lengths ranging from 42 to 130 nm were measured; however, as the channel length scaled, the SS became drastically larger and the on/off-current ratio degraded. The authors pointed out that the SS changes only slightly when the channel length is greater than 60 nm, indicating the source of the degradation to be from SCEs. In contrast, the back-gated 2D NC-FETs with HZO from this work show promising scaling behavior. While there remains some debate regarding which device structure is most favorable for NC-FETs, our results make it clear that the NC effect provides more favorable scalability when properly implemented.

In summary, we experimentally demonstrated 2D NC-FETs using MoS₂ with CMOS-compatible HZO as the FE to achieve remarkable robustness to channel length scaling. From a bottom-gated structure, we compared 2D FETs with 2D NC-FETs having exactly the same gate stack (with or without an anneal) to investigate the NC impact on the operation and performance of the devices across many gate lengths. Finally, we revealed unconventional behavior when scaling down to 20 nm, including stronger gate control and preferential performance from the 2D NC-FET. Based on these experimental results and analysis of the capacitive network, we find that the NC effect is beneficial to channel length scaling and enhances gate control as the length is scaled.

This work was supported in part by the National Science Foundation (Grant No. ECCS-1915814). This work was performed in part at the Duke University Shared Materials Instrumentation Facility (SMIF), a member of the North Carolina Research Triangle Nanotechnology Network (RTNN), which was supported by the National Science Foundation (Grant No. ECCS-1542015) as part of the National Nanotechnology Coordinated Infrastructure (NNCI).