We develop an engineered microwave environment for coupling high Q superconducting resonators to quantum dots using a multilayer fabrication stack for dot control wiring. Analytical and numerical models are presented, which show that high resonator quality factors can be attained by either minimizing the parasitic coupling capacitance to the leads or creating a low effective environmental impedance at the cavity frequency. We implement the later approach by fabricating low characteristic impedance () microstrips on-chip for the dot bias wiring and show resonator quality factors of 8140 that can be attained without the addition of explicit filtering. Using this approach, we demonstrate single electron occupation in double and triple dots detected via dipole or quadrupole coupling to a superconducting resonator. Additionally, by using multilayer fabrication, we are able to improve ground plane integrity and keep microwave crosstalk below −20 dB out to 18 GHz while maintaining high wire density, which will be necessary for future circuit quantum electrodynamics quantum dot processors.
Gate-defined quantum dots are a nascent platform for quantum computing in which electron charge and spin states are used to define the quantum bit.1,2 In silicon and Si/SiGe heterostructures, recent work has shown that it is possible to fabricate single, two, and four qubit systems3–9 with control infidelities at or approaching the level requisite for error correction.10 For most quantum dot circuits, the control wiring scheme consists of an electron beam (e-beam)-defined gate electrode structure with a rapid fan out into pads that are connected by aluminum or gold wire bonds to a printed circuit board (PCB) with typical die sizes of only a few millimeters. While this keeps the fabrication complexity to a minimum, it results in a minimally controlled microwave environment for the device and any readout circuitry. Near-term quantum computing effort with quantum dots faces significant quantum system engineering challenges balancing the needs for high fidelity readout, coupling, and control.
In this Letter, we demonstrate a wiring scheme for quantum dot devices in a circuit quantum electrodynamics (cQED) architecture. This approach allows for high-density, low crosstalk wiring with controlled RF leakage characteristics, paving the way for larger quantum dot processors utilizing cQED techniques.8,11,12 A simple and intuitive circuit model for cavity leakage from external leads reveals that minimization of the impedance of the environment at the cavity frequency ameliorates photon leakage out of the gate leads, which, otherwise, presents an undesired load on the cavity. We implement this method with a microstrip wiring scheme that achieves a low characteristic lead impedance of Ω and demonstrate resonators with quality factors as high as 8140 (design ) while connected to the quantum dot gate stack.
For these experiments, we fabricate cavity-coupled pairs of triple quantum dot structures on an undoped Si/SiGe heterostructure using an overlapping aluminum gate stack.13 The two-dimensional electron gas (2DEG) is formed in a 9 nm thick strained silicon layer either 20 or 30 nm below the surface. To avoid accumulation of 2DEG under the resonator, we remove the heterostructure using a / reactive ion etch everywhere except for two 50 × 100 mesa regions on the sample where the dot structures are located. The circuit consists of four key components: the overlapping aluminum gate electrodes, the dot lead wiring, the superconducting microwave resonator, and the resonator DC voltage tap. An optical image of a finished device is shown in Fig. 1(a). To understand the control environment of the device, Fig. 1(b) shows a simplified circuit diagram illustrating the key components for the on-chip microwave engineering. Additional wires and parasitic cross capacitances are not drawn for simplicity. We confine the 2DEG into quantum dots using three layers of overlapping aluminum gates patterned by e-beam lithography [Fig. 1(c)] and deposited by e-beam evaporation. High yield electrical isolation between gate layers is achieved by cleaning and oxidizing aluminum after lift-off of each layer with a 250 W downstream oxygen plasma asher for 10 min.14
Measurements of these samples are performed by wire bonding each device in a hybrid PCB-metal box enclosure designed to raise unwanted chip-mode frequencies to >20 GHz by creating a milled pocket below most of the 6.15 × 6.15 die.15 The packaged sample is cooled in a dilution refrigerator with a base temperature of and typical electron temperatures between 80 and 100 mK determined by fitting to a thermally broadened conductance peak.16 Charge detection is achieved by measuring the cavity-charge interaction during electron tunneling events.17,18 These interactions are formed by connecting a gate [in our case, P2 in Fig. 1(c)] to an aluminum or niobium microwave resonator. Zero point fluctuations in the electric potential of the LC oscillator couple to the dipolar (quadrupolar) detuning degree of freedom (ϵ) for the charge in the double (triple) dot system, allowing for detection of the quantum capacitance . By probing the cavity with a microwave tone at the bare cavity frequency (fr) and recording the transmitted amplitude and phase as a function of plunger gate voltage, damping and phase shifts of the probe are observed during electron tunneling events when the rates are comparable to the cavity frequency (of order several GHz). In the overlapping gate architecture, this condition is easily achieved through tuning of the dot barrier gate voltages B1–B4. Using plunger gates P1–P3, we can empty out the electrons in a double (or triple) dot and reach the (0,0) [or (0,0,0)] charge state configuration, as demonstrated in Fig. 1(d).
In order to maintain a high cavity quality factor, we engineer the microwave environment to minimize photon leakage out of the 25 bias leads of the two triple dot gate structures. This engineering amounts to maximizing the reflection coefficient of the microwave energy out of any lead other than the readout port by making the other leads look like high or low impedance to ground. A unique requirement for cQED experiments with dots is DC voltage biasing of the center pin of the coplanar waveguide (CPW) resonator in order to accumulate a quantum dot under P2. Test devices with DC taps at the center of the waveguide had quality factors less than 103, which was much lower than the explicit coupling defined by and . We eliminate leakage out of this lead by turning the tap into a -length CPW. The end of the CPW is shunted with a load impedance ZL in the form of a large parallel plate capacitor using an dielectric. The input impedance for a segment of the transmission line terminated by a load ZL is given by19
where is the propagation constant of the transmission line and is its physical length. By making the shunt capacitance large ( pF), we achieve . In combination with tapping at the voltage node, this effective impedance leads to minimal leakage out of the DC bias tap at the resonance frequency. Using this DC bias, devices without the overlapping aluminum gates achieved loaded quality factors as high as , well beyond the limit imposed by parasitic loading from the quantum dot circuit. We note that the quadratic dependence of on Z0 provides a way to further increase the quarter-wave tap input impedance through the use of large Z0 CPWs.12
The use of the overlapping gate stack poses a unique challenge for RF readout schemes, because of the large parasitic capacitances Cp (order 1 fF) between the gate electrodes in the region where the dots are formed. These parasitic capacitances are of the same order of magnitude as the capacitance used to purposefully couple photons into the readout port ( fF for a quality factor of 104 at 7.25 GHz) and, therefore, result in substantial microwave leakage out of the leads. To analyze this leakage, we first use a lumped element circuit model for loading of an LCR oscillator to a transmission line environment with characteristic impedance Zg and parasitic capacitance Cp.19,20 We then extend this model to real circuits with finite length leads where the general transmission line impedance transformer behavior captured in Eq. (1) must be taken into account. After including finite length effects, we show that the intuition from the lumped element model is qualitatively correct as long as dot gate lead lengths sufficiently avoid half integer multiples of the resonance wavelength λ (e.g., for ).
For the lumped element analysis, we write the resonator intrinsic quality factor as . Here, Rr is the effective damping resistance arising from the lossy dielectrics coupled to the electric field of the resonator. Schematically, each dot lead looks like the series combination of a capacitance Cp and, in the limit of an infinite transmission line, an effective real impedance Zg to ground [Fig. 2(a)]. In the Norton equivalent circuit, the gate impedance transforms to an additional parallel resistance,
By computing the new total load resistance , we find the effective quality factor . In terms of the impedance of the parasitic capacitor Zc, gate impedance Zg, and effective internal resistance Rr, we find
revealing that there are, in principle, two ways for reducing the effect of unwanted loading: minimizing the parasitic capacitance (maximizing Zc) or altering the gate impedance Zg to minimize the effect of the term in the denominator of Eq. (3). Notably, it is easier to reach the limit of than , as for typical superconducting resonators. Figure 2(b) shows a contour plot of Eq. (3) in the low Zg regime. For our experiments, the characteristic cavity impedance is Zr = 50 Ω, but the core result holds for higher impedance cavities as well and is captured by the definition of Rr.
Since reducing the parasitic capacitance in the overlapping gate stack is intrinsically difficult, we opt to control the gate impedance Zg. Previous effort to improve cavity quality factors involves the use of RF choke inductors or LC low pass filters, which have either high or low impedance at the cavity frequency, suppressing leakage.17,18 In both cases, the leads acquire a frequency-dependent filter function, which substantially limits the control bandwidth. To eliminate this potentially undesired feature, we choose to reduce the characteristic impedance of the transmission line on-chip using a microstrip geometry. The design and implementation of microstrip wiring are illustrated in Fig. 2(c). The wires are fabricated in a multilayer fabrication process that has three essential steps: deposition of the base layer ground plane, growth of an insulating dielectric layer, and deposition of the microstrip counter electrode.
To obtain the desired low impedance, we fabricate microstrips with a width of W = 3 and an thickness of h = 0.2 , yielding the limit where the parameter . The impedance of the microstrip in this limit can be calculated using conformal mapping and is given by19,21
with an effective permittivity
For our parameters, we find , which compares favorably to LC low pass filters in the literature,18 which have an input impedance of , while retaining the flexibility of a flat frequency response. The low impedance leads come at the cost of an insertion loss of approximately 3.5 dB due to the mismatch between the Ω coaxial cabling and the microstrip. This effect could be mitigated by an impedance matching element such as a Klopfenstein taper.21,22
The multilayer stack also provides a means for improved and reliable microwave performance in increasingly complex processors through additional on-chip crossovers. These structures serve as low inductance connections between ground planes on-chip, thereby suppressing spurious slot line modes more efficiently than with traditional aluminum wire bond stitching.23 Furthermore, aluminum wire bond stitching suffers from the low critical field of aluminum ( mT), which can damp the cavity upon application of an external magnetic field.24 Since both the crossover and base ground plane metals can be made of field tolerant superconductors such as niobium, they are useful for preserving circuit performance in cavity-spin coupling experiments. Finally, in Fig. 2(c), we demonstrate that this microstrip wiring scheme maintains less than −20 dB crosstalk between adjacent leads over a broad frequency range with a 7 μm wire pitch for approximately 1 mm, which could be important for minimizing off-resonant driving observed in recent resonant two-qubit gate experiments.6,7
Using these design principles, we fabricated and measured over twenty cavity coupled quantum dot structures and found a total spread in resonance quality factors between 2600 and 8140 [example spectra are shown in Fig. 2(d)]. We attribute the spread in the quality factor to variation in parasitic capacitance and finite length effects for the low impedance microstrips (discussed below). We note that in addition to the spread in quality factors for identical resonator designs (with the lithographic variation on the order of 0.2 ), the fundamental resonance frequencies show a large spread of approximately ±100 . Using the measured frequency, length of the waveguide, and conformal mapping20,21 to estimate the capacitance of the CPW structure, we back out a mean substrate permittivity to be . Using linear interpolation,25 we estimate the permittivity of the SiGe alloy to be , where x = 0.3. The origin of the apparent deviation is unknown at this time. Variation in the observed resonance frequencies could be explained by variation in the relative dielectric constant of the SiGe alloy by ±0.3, possibly caused by fabrication processing or growth variation across the wafer.
Although Eq. (3) is correct19,20 for coupling to an infinitely long transmission line with impedance Zg, in practice, the low impedance leads on-chip are only a few millimeters long and are wire bonded to a 50 Ω environment. To elucidate the impact of the finite length of on-chip low impedance leads, we use “Simulation Program with Integrated Circuit Emphasis” (SPICE) to calculate the resonator linewidth under various conditions. Figure 3(a) shows the circuit schematic used to understand the consequences of using finite transmission lines of length . Similar to the lumped element case, lowering Zg and Cp results in suppression of leakage. For a microstrip, the contour plot of the leakage path impedance in Fig. 3(b) is qualitatively similar to that in Fig. 2(b), but the roll-off is stronger as a function of .
In Figs. 3(c) and 3(d), we compute as a function of and leakage path (gate) length. When the gate length is a quarter wavelength of the resonance frequency, no voltage drop occurs across the 50 Ω environment at the end of the lead, effectively eliminating loss out of the lead. Conversely, when the lead is exactly in length, the voltage drop across the 50 Ω environment is maximal, resulting in the loss to the environment equivalent to using no leakage suppression scheme at all. As shown in Figs. 3(c) and 3(d), if Zg is low, the range of gate lead lengths that suppress leakage becomes very wide, with only lengths very close to displaying any significant degradation in . Figures 3(e) and 3(f) show that analogous results hold for as a function of Cp. The inset in Fig. 3(c) shows the reflection coefficient of a 50 Ω-terminated transmission line calculated using Eq. (1). The result is very similar to the SPICE calculation in the main panel, and thus, the simple analytical form provides good intuition for the finite length effects in maintaining a high Q.
In conclusion, we demonstrated a high-density, low-crosstalk, low impedance wiring scheme for quantum dots in a cQED framework. Using a simple circuit model, we designed a filterless low impedance wiring strategy for minimal microwave leakage achieving quality factors as high as 8140. We showed how this approach remains robust even in the presence of finite length effects of the low impedance leads. For devices with functional quantum dots, the measurement of the charge configuration down to zero electrons in both double and triple dots is achieved, paving the way toward the study of spin-photon coupling of exchange-based qubits in Si/SiGe.26
We acknowledge discussions on multilayer superconducting circuit fabrication with A. Opremcak, E. Leonard, M. Beck, F. Schlenker, and M. Vinje. We acknowledge technical advice in the development of processing recipes by K. Kuptcho, Q. Leonard, and E. Gonzales. Research was sponsored in part by the Army Research Office (ARO) under Grant No. W911NF-17-1-0274 and by the Vannevar Bush Faculty Fellowship program under ONR Grant No. N00014-15-1-0029. We acknowledge the use of facilities supported by NSF through the UW-Madison MRSEC (DMR-1720415) and an electron beam lithography tool supported by the NSF MRI program (DMR-1625348). The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the Army Research Office (ARO), or the U.S. Government. The U.S. Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation herein.
The data that support the findings of this study are available from the corresponding author upon reasonable request.