Tunnel field-effect transistors (TFETs) have attracted much attention as building blocks for low-power integrated circuits because they can lower the subthreshold slope (SS) below the physical limitation of conventional FETs. There, however, remains a difficulty in increasing the tunnel current in TFETs since the energy gap at the tunnel junction has a unique probability. Here, we investigated the strain effect stemming from the InGaAs-InP core–shell (CS) structure on the tunneling current in a vertical TFET using an InGaAs nanowire (NW)/Si heterojunction. We found that the TFET demonstrated a 10-fold enhancement in current while achieving a steep SS (minimum SS = 41 mV/dec). Strain analysis for the InGaAs NW/Si tunnel junction revealed that specific strain induced at the junction affected the increase in the on-state current.

Using a huge number of field-effect transistors (FETs) with miniaturization inherently increases the power consumption of integrated circuits (ICs) because thermionic carrier transport in the FETs physically limits the minimum subthreshold slope (SS) to 60 mV/dec at room temperature (SS = 60 mV/dec at room temperature). The power consumption of the ICs is proportional to the square of supply voltage,1 which is basically defined by the SS. Lowering the SS below 60 mV/dec is important when we expect a significant decrease in the power consumption, which is difficult for state-of-the-art FETs due to the physical limitation. Steep-slope transistors in which the carrier transport process involves a subthermionic process, such as TFETs,2–4 negative capacitance FETs,5,6 and impact ionization FETs,7 have been proposed to overcome this SS limitation.

TFETs with a steep SS are promising building blocks for future ICs with very low power consumption because reduction in the SS decreases the supply voltage to as little as 0.20 V. The steepness of the SS in TFETs strongly depends on the bias condition, meaning that a tunnel junction with an applied high internal electrical field under a smaller bias condition can achieve a steep SS.2,3 Thus, designing the series resistance in the TFET structure is key for achieving a steep SS. At the same time, exploiting a moderate tunnel junction and using materials with precise controlled doping and gate stacking technology are required for TFETs with steep SS switching. A TFET with the SS below 60 mV/dec was demonstrated by using Si,8–14 Ge,14–16 InGaAs,14,17–19 InGaAs/GaSb,20–22 two-dimensional materials,23,24 and III-V/Si junctions.25–28 Moreover, various transistor architectures, such as the conventional planar structure,8,10,11,17–19,22,23 back-gate type,24 lateral gate-all-around (GAA),19 and vertical GAA (VGAA),11,12,20,21,25–28 have been utilized for a TFET that can achieve a steep SS.

There is still a challenge when it comes to the on-state current (ION) in TFETs because the ION strongly depends on the tunneling probability,29 which is uniquely determined by junction material parameters such as energy gap, effective mass, and screening tunneling length. Material designs that achieve high tunneling probability by utilizing a heavy doped p–i–n junction,18 isoelectronic traps,30 and narrow-gap junctions such as InGaAs/GaSb20–23 have been proposed. However, there have been few reports on scalability in specific tunnel junctions to maximize the tunneling probability while maintaining a steep SS.27 Recently, the scaling of channel length VGAA-TFETs using an InGaAs nanowire (NW)/Si tunnel junction27 has been investigated to exploit the current-boosting technology. The benefits of the vertical NW channel include its surrounding-gate architecture with good gate-electrostatic control and its core–shell (CS) structure for surface passivation and strain. Using the strained InGaAs enables the bandgap to be changed31 and can possibly increase the tunneling probability. Here, we investigate VGAA-TFETs using an InGaAs-InP CS NW/Si heterojunction to characterize the effect of the CS structure with respect to the current-boosting.

In experiment, we used a p-type Si(111) substrate with the carrier concentration of 3 × 1018 cm−3. After degreasing the substrate with organic solvents, 12-nm-thick and 20-nm-thick SiO2 films were formed by thermal oxidation, and opening holes were formed by using electron beam lithography and dry and wet etching processes. The diameter of the opening holes was 30 nm for the TFET device and 50 nm for the characterization of NW growths. In0.7Ga0.3 As NWs were grown in a low-pressure (0.1 atm) horizontal metal-organic vapor-phase epitaxy (MOVPE) system with H2 carrier gas. Trimethylgallium (TMGa), trimethylindium (TMIn), tertiary-butylphosphine (TBP), and arsine (AsH3) gas were used as the source materials. Mono-silane (SiH4) was used as an n-type dopant. Tetraethyltin (TESn) and diethylzinc (DEZn) were used as n-type and p-type dopants for the pulse-doping technique to form a heavily n-type and compensated segment in the NW, respectively. After cleaning the SiO2-coated Si(111) by RCA cleaning processes, we utilized a specific growth sequence to align vertical InGaAs NWs on Si(111) substrates.32 The InGaAs NWs were grown for 15 min at 670 °C. The InGaAs NW was composed of a 100-nm-long Zn pulse-doped segment, a 200-nm-long part with a Si-doped layer, and a 700-nm-long part that was heavily doped with Sn. These lengths were arranged by growth time, where the NW growth rate was estimated from the representative growth results. The carrier concentrations were 3.5 × 1015 cm−3 for the intrinsic segment, 3 × 1018 cm−3 for the Si-doped segment, and 1 × 1019 cm−3 for the Sn-doped segment. The lateral overgrowth for InP33 was used for shell layer growth. The InP was grown for 7 and 10 s at 580 °C.

The VGAA-TFET was fabricated against a single vertically aligned InGaAs/InP CS NW on a p-Si (see the supplementary material, Fig. S1). The device process flow was almost the same as that in the previous reports.27,28 The gate oxide was a 7-nm-thick Hf0.8Al0.2O (ε = 20.4)] film deposited by atomic layer deposition after the self-cleaning process of Al sources. The gate metal was tungsten (W). The NW covered with the gate oxide and metal was spin-coated with benzocyclobutene (BCB) and etched back by reactive-ion etching (RIE) with CF4/O2 to etch the BCB, W, and Hf0.8Al0.2O gate oxide simultaneously. The gate length (LG) was adjusted by the RIE etching time, and the LG was fixed to 200 nm, meaning that the gate metal overlapped the intrinsic (channel) and Si-doped NW segments. A Ni/Ge/Au/Ni/Au multilayer was evaporated on the RIE-revealed InGaAs/InP CS NW to serve as the drain metal and a Ti/Au multilayer was deposited onto the Si substrate to serve as the source (ground) terminal. Finally, the TFET structure was annealed at 400 °C in N2. We evaluated the transistor performance with Agilent 4156C and Keysight B1500A parameter analyzers under the standard measurement condition at room temperature in the dark.

FIG. 1.

(a) Illustration of the InGaAs NW array on Si composed of Zn pulse-doped/Si-doped/Sn pulse-doped axial junctions. (b) 30°-tilted SEM image showing InGaAs NWs on Si. (c) Schematic diagram of the InGaAs-InP CS NW array on Si. (d) 30°-tilted SEM image showing a CS NW array on Si.

FIG. 1.

(a) Illustration of the InGaAs NW array on Si composed of Zn pulse-doped/Si-doped/Sn pulse-doped axial junctions. (b) 30°-tilted SEM image showing InGaAs NWs on Si. (c) Schematic diagram of the InGaAs-InP CS NW array on Si. (d) 30°-tilted SEM image showing a CS NW array on Si.

Close modal

Figures 1(a)–1(d) show the representative growth results of vertically aligned InGaAs NWs and InGaAs/InP CS NWs on Si(111). The growth time of the InP shell was 10 s. As shown in Figs. 1(b) and 1(d), the vertical InGaAs NWs and InGaAs/InP CS NWs were integrated on Si(111) substrates. The morphology of the NW consisted of hexagonal-shaped pillar structures surrounded with vertical {−110} facets and a (111)B plane. The average diameter of the InGaAs NWs was 85 nm, which was larger than the opening diameter (50 nm), indicating that slight lateral growth along the ⟨−110⟩ directions occurred. The diameter of the InGaAs/InP CS NW was around 105 nm. The average height of the InGaAs NW was 1.5 μm, and it was virtually the same height after the InP shell growth. This means that the InP layer was grown only onto {−110} vertical facets. The thickness of the InP shell was 10 nm, and the growth rate was 1.0 nm/s.

Figure 2 shows the transmission electron microscopy (TEM) image of the InGaAs-InP CS NW on Si and energy dispersive x-ray spectroscopy (EDX) elemental mappings. The InP shell was grown for 7 s. The incident direction of the electron beam was the [−110] direction. As shown in Fig. 2(a), the core InGaAs NW was epitaxially grown on p-Si(111) and a crystal structure was composed of a zinc blende type with rotational twins. The InP shell layer formed a smooth sidewall. The InP shell layer exhibited inversed mesa facets formed at the bottom part of the CS NW. The angle between the facet and the {−110} sidewalls was ∼56°, indicating that the facet orientation was (111) A. This occurred because the InP shell layer was grown under the optimum growth conditions for the selective-area growth of InP NWs and, as such, the (111) A facet was preferentially formed.

FIG. 2.

(a) TEM image showing the vertical InGaAs-InP CS NW grown on Si(111). The incident beam direction was along the ⟨−110⟩ direction. EDX elemental mapping images for (b) In, (c) As, (d) Ga, (e) P, and (f) P-As-Si mixed mapping.

FIG. 2.

(a) TEM image showing the vertical InGaAs-InP CS NW grown on Si(111). The incident beam direction was along the ⟨−110⟩ direction. EDX elemental mapping images for (b) In, (c) As, (d) Ga, (e) P, and (f) P-As-Si mixed mapping.

Close modal

The EDX elemental mappings in Figs. 2(b)–2(f) show that the InP shell layer was clearly separated from the core InGaAs NW. In Figs. 2(d) and 2(f), we can see that an overlapping area of the P and Ga atoms was formed. This was because the cleaved surface of the TEM specimen overlapped the region of the InP shell with the core InGaAs NW in the incident depth direction. The overlapped area in Fig. 2(f) corresponds to the core InGaAs NW and the InP thickness was estimated to be 7.5 ± 0.5 nm, which corresponds to that of the growth rate of the InP shell.

Figure 3 shows the switching properties of the VGAA-TFET using the InGaAs-InP CS NW/Si junction. The core InGaAs NW was 30 nm in diameter. The LG was fixed to the channel length (the intrinsic layer was 100 nm). Typical TFETs often show negative differential resistance (NDR) curves in the forward direction.21 In this case, the InGaAs NW/Si junction, whose concentration of p-Si was above 1019 cm−3, showed the NDR signal under a heavy doped condition, which indicates that the band-to-band tunneling (BTBT) regime occurred at the InGaAs NW/Si junction.27 However, the channel layer was compensated as nearly intrinsic, resulting in the absence of NDR (see the supplementary material, Fig. S3).

FIG. 3.

(a) Transfer characteristics of the VGAA-TFET using the InGaAs-InP CS NW/Si junction. The pink dashed curve is the transfer property for the VGAA-TFET using the InGaAs NW/Si junction at VDS = 0.50 V. (b) Output properties of the VGAA-TFET. (c) SS vs drain current with variation of VDS and that of the TFET using InGaAs NW/Si. (d) Kane's model plot of the VGAA-TFET (e) Variation of device performance of 23 VGAA-TFETs using the InGaAs NW/Si junction (blue curves) and InGaAs-InP CS NW/Si junction (red curves). (f) Distribution of on-state current at VDS = VG = 0.50 V. Blue bars are the VGAA-TFET with InGaAs NW/Si and red bars are the VGAA-TFET with the InGaAs-InP CS NW/Si junction.

FIG. 3.

(a) Transfer characteristics of the VGAA-TFET using the InGaAs-InP CS NW/Si junction. The pink dashed curve is the transfer property for the VGAA-TFET using the InGaAs NW/Si junction at VDS = 0.50 V. (b) Output properties of the VGAA-TFET. (c) SS vs drain current with variation of VDS and that of the TFET using InGaAs NW/Si. (d) Kane's model plot of the VGAA-TFET (e) Variation of device performance of 23 VGAA-TFETs using the InGaAs NW/Si junction (blue curves) and InGaAs-InP CS NW/Si junction (red curves). (f) Distribution of on-state current at VDS = VG = 0.50 V. Blue bars are the VGAA-TFET with InGaAs NW/Si and red bars are the VGAA-TFET with the InGaAs-InP CS NW/Si junction.

Close modal

We can see steep turn-on behavior with a minimum SS of 41 mV/dec in Fig. 3(a), which indicates an improvement in the CS NW/oxide interface compared to the InGaAs NW (the pink dashed curve in Fig. 3(a) shows the SS of 80–90 mV/dec; the on-current was 2.6 nA/μm at VDS = VG = 0.50 V). Prior research has shown that the VGAA-FET using InGaAs NW-channels on n-Si exhibits no hysteresis due to few traps in the oxide interface.28 The VGAA-TFET showed a drain-induced-barrier-lowering (DIBL) of ∼20 mV/V, meaning that the TFET effectively circumvented the short-channel effect (SCE). The ION was about 21 nA/μm at VDS = VG = 0.50 V, which was about 10 times higher than that of the VGAA-TFET without the InP shell. A steep SS ranged over three digits, as shown in Fig. 3(c). The output properties in Fig. 3(b) indicate that the saturation region appeared at a very low bias, meaning that the Zener tunneling under backward bias was modulated by the VG. As shown in Fig. 3(d), the ID with log (ID/VG2) as a function of 1/VG at VDS = 0.25 V exhibited a linear slope, following Kane's tunneling model,29 which indicates that the dominant transport processes in the VGAA-TFETs include the quantum tunneling transport. Further characterization to identify the detailed tunneling mechanism should be examined in future work.

We evaluated the variability of 23 VGAA-TFETs: InGaAs NW and InGaAs-InP CS NW. Figure 3(e) shows the device variability of the InGaAs NW and InGaAs-InP CS NW. The variation in the threshold voltage for the InGaAs-InP CS NW was decreased compared to that of InGaAs NW. This is because the internal electrical field was uniformly induced in the case of the InGaAs-InP CS NW-channel. Figure 3(f) shows the variation in ION of the VGAA-TFETs. The current distribution was 2.5 nA/μm ± 2 nA/μm for the InGaAs NW and 25 nA/μm ± 5 nA/μm for the InGaAs-InP CS NW. The ION for the InGaAs/InP CS NW was ten times higher than that for the InGaAs NW. This enhancement of the ION seems to stem from the bandgap narrowing at the InGaAs/Si junction due to strain from the CS NW structure. Narrowing the effective energy gap by the strain induced a stable internal electrical field and variations in the threshold voltage and current distribution. There were no concrete parameters for device variability such as delta-sigma for the threshold voltage and current distribution.

To clarify what causes the enhancement of ION for the CS NW-channel, we characterized the crystal structure and strain mapping in the vicinity of the InGaAs-InP CS NW/Si tunnel junction, as shown in Fig. 4. In these strain mappings, a partial lamellar compressive strain (about 4%) in the ⟨2¯11⟩ direction [Fig. 4(c)] was generated at the bottom of the core InGaAs NW. A compressive strain area (about −2%) was also observed in the vicinity of the InGaAs/InP core–shell interface. In contrast, a local compressive strain area (4%) was formed at around the bottom of the core InGaAs NW in Fig. 4(d). These strain distributions differ from coherent growth. The lattice mismatch of the InGaAs/InP was −1.8% in this case. The lattice constant of the core InGaAs NW was compressed along the [−1 − 1 − 1] (yy) direction and elongated in the ⟨−211⟩ (xx) directions following the lattice mismatch. Thus, the 2% compressive strain area in Fig. 4(c) originated from the core–shell structure. Though the 4% compressive strain in Fig. 4(c) was thought to be originated from the lattice mismatch of InGaAs/Si (∼10%), the strain was only 4% and had no tensile strain in the yy-direction. At the same time, compressive strain remained in the vicinity of the InGaAs/Si interface. This strain behavior differs from conventional coherent growth, and no such strain behavior has been observed at the bare InGaAs NW/Si junction.28 These results suggest that the unique strain behavior was caused by the edge effect of strain induced from the core–shell structure and the lattice strain of Si and InGaAs NWs.

FIG. 4.

(a) High resolution HAADF-STEM image of the InGaAs-InP CS NW on Si. (b) Schematic of panel (a). (c) εxx strain mapping estimated from the filtered image of panel (a). (d) εyy stain mapping estimated from the filtered image of panel (a).

FIG. 4.

(a) High resolution HAADF-STEM image of the InGaAs-InP CS NW on Si. (b) Schematic of panel (a). (c) εxx strain mapping estimated from the filtered image of panel (a). (d) εyy stain mapping estimated from the filtered image of panel (a).

Close modal

This strain behavior can be divided into two strains: one is the biaxial compressive strain, which was induced to the cross section of the tunnel junction [Fig. 4(c)], and the other is the uniaxial compressive strain, which was applied along the transport direction [Fig. 4(d)]. The former strain reduces the tunnel current and the latter strain increases the tunnel current due to the shifting up of the valence band.31 We ascribe that tunneling probability has increased due to the narrowing of the effective energy gap as a result of the competition between these two strain situations. In fact, a reduction in the bandgap of about 0.05 eV increases the BTBT tunnel current by about 20 times.34 Therefore, we conclude that the current enhancement in the VGAA-TFET using the InGaAs-InP CS NW/Si junction originated from the unique strain situation at the InGaAs/Si junction.

In summary, the VGAA-TFET using the InGaAs-InP CS NW/Si junction can exploit a current-boosting technology (enhancement of tunneling probability) against a specific junction structure in terms of scalability by the strain effect. The VGAA-TFETs showed steep SS (minimum SS ∼41 mV/dec) turn-on properties and a current enhancement that was ten times higher than that of the same VGAA-TFET structure without the InP shell layer. The benefits of using the InP shell layer are the improvement of the SS as a passivation effect and the enhancement of the ION due to the strain effect induced at the InGaAs NW/Si tunnel junction.

See the supplementary material for the details of the fabrication procedure for the VGAA-TFET (Fig. S1); the strain profiles for Figs. 4(c) and 4(d) (Fig. S2); and output properties for the VGAA-TFET (Fig. S3).

We especially thank Dr. Masatoshi Yoshimura and Dr. Eiji Nakai for their help with the MOVPE. This work was financially supported by a Grant-in-Aid (KAKEN Grant Nos. 16H06080 and 19H02184) provided by the Japan Society for the Promotion of Science (JSPS).

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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