Thermal properties of carbon nitride toward use as an electrode in phase change memory devices

Phase change memory (PCM) is an emerging technology offering benefits such as higher scalability and faster read/write mechanisms compared to its transistor-based counterparts DRAM and NAND flash memory.^1–3 Moreover, PCM has recently attracted increased attention due to its crossbar architecture⁴ and multi-level storage capability,⁵ which allow the construction of a neural network within the memory device.⁶ These capabilities extend the applicability of PCM to synaptic devices and artificial intelligence.^7–9 

In PCM devices, the data are written (set) and erased (reset) via short pulses of electrical current on the order of nanoseconds. These pulses switch the phase of the memory cell between high (amorphous) and low (crystalline) electrical resistance states. During the write process, a short electrical pulse heats the amorphous phase change unit above its crystallization temperature, resulting in a reduction in the electrical resistance. In order to erase the data, an even shorter but higher amplitude pulse heats the phase change unit above its melting point and switches the material back to its high resistivity amorphous state. Subsequently, the read process is performed by a low electrical current that measures the resistance across the memory cell. The phase change material used in these devices is most commonly a chalcogenide-based material with ultrafast sub-nanosecond switching time scales,¹ such as Ge₂Sb₂Te₅ (GST).

In PCM devices, efficiency is strongly tied to the materials surrounding the GST and how efficiently heat is localized to the memory cell. For instance, it has been shown that a majority of heat generated in the memory cell is lost through the bottom electrode.^10–12 Thus, the thermal conductivity of the bottom electrode and thermal conductance across its interface are of critical importance for controlling the temperature and optimizing the operating conditions of PCMs. A common electrode material for PCM is titanium nitride (TiN), which has a range of thermal conductivities and electrical resistivities, depending on the deposition process ranging from 8 to 63 W m⁻¹ K^–1 and 13.5 to 150 $μΩ$ cm, respectively.^11,13–17 The mechanical strength of TiN, coupled with its relatively low thermal conductivity, makes it appealing for electrode applications, such as PCM, as it reduces heat leakage during the rapid temperature rise associated with both the set and reset operations. Recently, there have been a number of advancements in the design of electrodes in order to reduce the minimum current required for programming. Xiong et al.² showed that through utilization of carbon nanotube electrodes, the programming current can be reduced by up to two orders of magnitude. Ahn et al.¹⁸ observed an approximately 40% reduction in the reset current via insertion of a single sheet of graphene between the bottom electrode and the GST.

Here, we investigate a method toward minimizing the programming current by introducing a carbon-based electrode that has a low intrinsic thermal conductivity, over an order of magnitude lower than the intrinsic thermal conductivity of TiN, low thermal boundary conductance, and appreciable electrical conductivity. In this Letter, we report the thermal properties of carbon nitride (CN_x) thin films at length scales applicable to memory cells (⁠$≤40$ nm) across a wide temperature range (25–400 °C). Our results suggest that CN_x electrodes could offer significant improvement in the thermal confinement of PCM devices.

Magnetron sputtering was used to deposit the CN_x thickness series of interest in this study. Figure 1(a) shows a schematic of the CN_x layer on either side of the phase change material with the corresponding thicknesses. Due to the existence of low thermal conductivity layers in this study, a precise knowledge of the thicknesses is essential to correctly calculate the thermal conductivity of individual constituent materials, as well as the thermal conductance across material stacks comprising several layers. Therefore, for all samples reporting values of thermal conductance, transmission electron microscopy (TEM) was performed, similar to that presented in Fig. 1(b), to examine the exact thickness of each layer. The TEM images for the remainder of samples are provided in the supplementary material. The elemental composition of the deposited CN_x is characterized using X-ray photoelectron spectroscopy (XPS). Figure 1(c) shows the surface energy measurements and the corresponding binding energy peaks for C and N. The area under each intensity peak represents the relative atomic percentage of one element to another.^19,20 According to Fig. 1, we detect 90% of carbon and 10% of nitrogen in the CN_x layer with no traces of oxygen due to the existence of a Ru capping layer. The trace Ar observed in Fig. 1 is not inherent to the CN_x layer but rather a result of ion sputtering in order to remove the Ru transducer and reach the CN_x film, which was performed under vacuum.

In order to quantify the thermal properties of the thin film CN_x, we employ time-domain thermoreflectance (TDTR) in a “two-tint” configuration.²¹ Our two-tint TDTR system utilizes a sub-picosecond Ti:sapphire oscillator with an 80 MHz repetition rate centered at 808 nm, which is split into a high energy pump path and a low energy probe path. The pump is modulated at a frequency of 8.4 MHz via an electro-optical modulator and focused onto the sample surface. The probe is focused to the same spot, and the change in reflectivity due to the modulated heating event is sampled with a photodetector and recorded with a lock-in amplifier. At the sample surface, the 1/e² diameters of the focused pump and probe spots are 22 and 12 μm, respectively. All samples are coated with 80 nm of ruthenium to serve as an opto-thermal transducer for TDTR measurements.

The total thermal resistance, R, measured across the Ru/CN_x/Si interface as a function of CN_x film thickness is shown in Fig. 2 for both the as-deposited and annealed CN samples. For comparison, the total thermal resistance for the corresponding thicknesses of silicon nitride (SiN_x) is shown. The intrinsic thermal conductivity of these thin films can be extracted from the data in Fig. 2 by applying a linear fit to the total thermal resistance as a function of film thickness, where the inverse of its slope (ΔR/Δd)^–1 corresponds to the thermal conductivity. This approach yields the thermal conductivity of 1.47 ± 0.09 W m⁻¹ K^–1 for the as-deposited CN_x and 1.72 ± 0.1 W m⁻¹ K^–1 for the annealed films. For comparison, we measure the intrinsic thermal conductivity of SiN_x as ∼1.20 W m⁻¹ K^–1, derived from the same slope analysis, in good agreement with SiN_x fabricated under similar conditions.^22,23 These CN_x films exhibit thermal conductivities typical of amorphous materials and are over an order of magnitude lower than that of the commonly used electrode material TiN. These results demonstrate promise using CN_x as a heat confining low thermal conductivity electrode.

To understand the possible microscopic mechanisms leading to the enhancement in electrical and thermal conductivity upon annealing, we perform Raman spectroscopy and compare the Raman spectra for CN_x at different annealing temperatures. Although CN_x maintains its amorphous structure, based on the Raman spectra, the density of the defective regions decreases by annealing at high temperatures.²⁴ A more comprehensive discussion on the interpretation of Raman spectra is given in the supplementary material. We attribute the ∼0.2 W m⁻¹ K^–1 gain in the thermal conductivity of the CN_x as a result of annealing to an increase in electrical conduction. The electrical resistivity of the as-deposited CN_x at room temperature is above 120 mΩ cm. This implies that the contribution of electrons to thermal conduction is negligible compared to the phononic contribution. However, upon annealing to 400 °C, the electrical resistance drops to nearly 5 m Ω cm, which corresponds to an electronic thermal conductivity of ∼0.15 W m⁻¹ K^–1 via the Wiedemann Franz law. As a result, we posit that the increase in electrical contribution to thermal conductivity is the driving factor, leading to the enhancement of total thermal conductivity and reduction of thermal resistance from annealing CN_x.

In PCM devices, the CN_x layer can add to the total device resistance and, therefore, its benefits for thermal design and integration need to be balanced against the desired device electrical properties. Crystalline PCMs have resistivity in the range of 1–5 m Ω cm, while the amorphous phase resistivity is several orders of magnitude larger.²⁵ The CN_x resistance will be insignificant compared to the PCM resistance in the amorphous state. However, if a very low device resistance is required for fully crystallized devices, then it is important to minimize the thickness of the CN_x layer to allow acceptable electrical resistance at the expense of the thermal isolation and heat generation that the CN_x layer provides.

Figure 3 shows the total thermal conductance across the Ru/CN_x/Si and Ru/SiN_x/Si stacks for the 10 nm CN_x and SiN_x samples in their as-deposited states. As a comparison, we also show the conductance across Ru/W/Si interfaces, where W is a common high temperature contact in phase change memory devices. As expected, due to the high intrinsic thermal conductivity of W, the Ru/W/Si configuration has the highest conductance, which is relatively constant over the temperature range studied in this work. While the intrinsic electrical resistance of bulk W should increase with increasing temperature, due to fact that the thickness of the W is only 10 nm, we expect the temperature dependence of the electrical and thermal transport properties to be suppressed due to boundary scattering. This, combined with the fact that we expect phonon dominated thermal boundary conductance across each interface to be relatively temperature independent as temperatures approach and exceed the Debye temperature of these materials, explains the lack of temperature dependence in the Ru/W/Si thermal conductance.²⁶ The Ru/SiN_x/Si configuration yields the lowest thermal conductance due to the low, and relatively temperature insensitive, thermal conductivity of SiN_x, a common behavior for amorphous dielectrics.^27–29 In the case of Ru/CN_x/Si, the conductance is higher than that of the Ru/SiN_x/Si stack (as expected from the results in Fig. 2), but noticeably increases at elevated temperatures. This increase is expected due to the enhancement of the electronic contribution to thermal conductivity, as previously discussed. In the case of 400 °C annealed CN_x, the 0.15 W m⁻¹ K^–1 increase in thermal conductivity is equivalent to a thermal conductance of 15 MW m⁻² K^–1 for a 10 nm thick film, which is comparable to the increase observed in the CN_x data in Fig. 3 from room temperature to 400 °C.

In order to study the GST/CN_x interfacial conductance, two sets of samples with GST thicknesses of 10 nm and 40 nm are fabricated. The GST layers are sandwiched between 5 nm films of W, CN_x, and SiN_x for each combination of GST thickness. As shown in Fig. 1(a), the samples are grown on a silicon substrate with 80 nm of Ru on top for TDTR measurements (80 nm Ru/5 nm (CN_x,W,SiN_x)/10 nm GST/5 nm (CN_x,W,SiN_x)/Silicon substrate). The exact thickness for each layer has been confirmed from the TEM results. From the TEM images, we observe an approximately 3 nm amorphous region at the surface of the silicon substrate, which is present in all samples and is attributed to the ion milling cleaning procedure prior to film deposition.

Figure 4 shows the thermal conductance between Ru and Si (across the various thin films in between and their corresponding interfaces) at elevated temperatures. For the case of the W spacer, the thermal conductance is the highest. This implies that W would result in a large heat leakage, which increases the power consumption in the PCM device. Although W is a better electrical conductor than CN_x and allows for more efficient Joule heating in the GST, it also allows for substantial thermal loss that is detrimental to the performance of the device. On the contrary, CN_x has a reduced electrical conductivity compared to W but proves to be a better choice from a thermal transport perspective. To support this, the thermal conductance measurements reported in Fig. 4 show significantly lower thermal conductance for CN_x spacers and indicate the promise of CN_x as a potential electrode material to confine heat in the GST more efficiently than W, particularly at elevated temperatures. Although the comparison drawn between W and CN_x electrodes can only be quantified if used in a device, the results of this paper pave the way for future studies of CN_x electrodes. Furthermore, even though CN_x is used for electrode applications and SiN_x is used as an insulator, in the thin film GST regime (10 nm), CN_x/GST/CN_x shows a lower thermal conductance up to nearly 340 °C. Considering the higher thermal conductivity of CN_x, this observation indicates that the interfacial conductance between GST/CN_x is lower than that of GST/SiN_x, which results in a lower overall thermal conductance. At temperatures above 340 °C, for the CN_x spacer, thermal conductance is suppressed by almost a factor of three compared to the W spacer. This observation implies that CN_x can serve as an efficient heat barrier in phase change memory cells. Furthermore, Fig. 4(a) shows that at the crystallization temperature (∼150 °C), unlike W and SiN_x spacers, CN_x does not exhibit as large a change in the thermal conductance and yields almost 30% lower conductance than that of the SiN_x, which is an insulator. This is particularly crucial during the “set” process where the GST temperature rises above its crystallization temperature for a longer duration. Figure 4(b) shows the conductance for a similar set of samples with a thicker GST layer (40 nm). As a result of the increased thickness, the measured conductance for all cases is lower than that of samples with 10 nm of GST. In this regime, the total conductance from the Ru to the Si is less dominated by the thermal boundary conductance across the various spacer/GST interfaces and instead is dominated by the resistance from the GST films. As a result of this thickness effect, the thermal conductance for CN_x/GST/CN_x and SiN_x/GST/SiN_x is nearly identical up to 340 °C.

In summary, we report on the thermal properties of a potential class of electrodes for phase change memory devices with relatively low electrical resistance and high thermal insulation. We show that CN_x yields better thermally insulating properties than a common electrode such as W and a common insulator such as SiN_x at length scales used in devices. We measure the thermal conductivity of CN_x for as-deposited and 400 °C annealed cases to be 1.47 ± 0.09 and 1.72 ± 0.1 W m⁻¹ K^–1 and the electrical resistivity to be ∼120 and 5–10 m Ω cm, respectively. Based on our observations, from 150 °C to 340 °C, CN_x as an electrode retains heat better than an insulating material, SiN_x, due to the high CN_x/GST interfacial thermal resistance. Our results indicate that above the GST crystallization temperature (∼150 °C), the thermal transport for thin film GST (10 nm) in contact with CN_x is suppressed compared to W due to the low thermal conductivity of CN_x and high GST/CN_x interfacial resistance. We observe that the effect of boundaries begins to disappear as the overall resistance due to the thickness of GST increases. The thermal conductance in the case of thick film GST (40 nm) is predominately dictated by the intrinsic thermal conductivity of the GST layer rather than the interfaces.

See the supplementary material for a more comprehensive discussion regarding the effect of annealing on Raman spectra as well as compositional characterization of the CN_x film and corresponding transmission electron microscopy.

We appreciate support from Western Digital Technologies, Inc. This manuscript is based upon work supported by the Air Force Office of Scientific Research under Award No. FA9550-18-1-0352 and the National Science Foundation under Award No. 162601.