Ferroelectric memory field-effect transistors using CVD monolayer MoS₂ as resistive switching channel

The ever-increasing demand for energy-efficient and high-speed data processing and storage has triggered the research community to look for new electronic materials and device architectures.¹ For this reason, the family of two-dimensional transistor metal dichalcogenides (2D TMDs) has attracted considerable attention since the successful exfoliation of graphene in 2004.² Though graphene does not have a bandgap, TMD crystals, when reaching the single-layer limit, can possess sizable direct bandgaps with moderate carrier mobilities and rich physical properties for various applications, including transistors,³ photodetectors,⁴ energy harvesting devices,⁵ and spintronics.⁶ Combined with their ultimate thinness in vertical dimensions, devices based on 2D TMDs are highly desirable for the compact integration of computing chips, logic, and memory cells with further reduction in power consumption enabled by the strong coupling between the gate electric fields and their ultrathin bodies. Among all TMDs, molybdenum disulfide (MoS₂) is noteworthy because of its relatively high chemical stability and large bandgap (1.8–1.9 eV).⁷ High-performance transistors and optoelectronics based on MoS₂ have been reported.^3,8,9 However, detailed investigations of its applications for data storage devices based on different device architectures are still lacking.

Very recently, layered 2D materials have been introduced into various types of emerging memory technology based on resistive switching through either electrical or optical excitations such as two-terminal memristors and optical memory devices.^10–14 Given the excellent properties that MoS₂ holds as the transistor channel, memory devices adopting the field-effect transistor (FET) architectures, namely, ferroelectric FETs (FeFETs), would be a promising strategy to integrate MoS₂ into high-performance data storage systems, where a high-density memory cell array and a low operational power are highly desired. Ferroelectric-based memory devices ideally exhibit nonvolatility, fast switching, a high on/off ratio, and programmable multilevel conductance states for applications in artificial neural networks.^15–20 Until now, organic ferroelectric polymers have been widely used in promising FeFETs due to the advantages of large-scale preparation and mechanical flexibility.^9,18,19,21 Nevertheless, since organic ferroelectric materials are usually highly soluble in common organic solvents and show low thermal budgets, integrating organic ferroelectric-based devices into integrated circuits (ICs) could be challenging, considering that high-performance computing systems require complicated semiconductor manufacturing processes. Moreover, those organic FeFETs in general show high writing voltages (e.g., ±35 V for the 2D MoSe₂ FeFET),¹⁸ likely due to the spin-coating-process-limited thickness of the ferroelectric poly (vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] layer (∼300 nm), which limits the gate control efficiency. Those aforementioned limitations make such types of FeFETs difficult to be commercially feasible. On the other hand, attempts at building high-performance FeFETs using 2D TMD channels have so far relied on mechanically exfoliated flakes,^17,18,21 which are not applicable to high-volume manufacturing and large-scale memory networks.

In this work, we demonstrate 2D FeFETs using monolayer semiconducting MoS₂ and inorganic ferroelectric thin films of zirconium-doped hafnium oxide (HfZrO_x) with a back-gated configuration. The MoS₂ channel was synthesized through chemical vapor deposition (CVD), and the ferroelectric HfZrO_x gate insulator was deposited by atomic layer deposition (ALD). Both the processes and materials are scalable and CMOS-manufacturing compatible. Our 2D FeFETs exhibit a low-voltage-driven feature (<±3 V) with hysteresis for data storage applications at room temperature, and the memory hysteresis characteristics can be further modulated by the gate bias. Moreover, the device shows synapticlike characteristics with potentiation and depression of the channel conductance when stimulated through a sequence of electric pulses. An ultrathin HfO₂ dielectric film placed between the semiconducting channel and the ferroelectric in the gate stack was found to act as a passivation layer that stabilizes the ferroelectricity of the device. Meanwhile, the device architecture of our MoS₂ FeFETs offers a noticeable amplification of the MoS₂ photoluminescence (PL), which originates from Fabry–Pérot cavity reflection of the bottom gate mirror.²² Our results demonstrate the great potency of CVD-grown TMD/HfO₂-based ferroelectric heterostructures for future energy-efficient memory and brainlike computing applications.

The schematic structure of a back-gated single-layer MoS₂ FeFET as a nonvolatile memory cell is shown in Fig. 1(a). The process flow is depicted and described in detail in Fig. S1. A layer of Ti/Au (5 nm/70 nm) serves as the metal gate. A 15 nm thin film of HfZrO_x is employed as the ferroelectric gate insulator through atomic layer deposition (ALD). The TiN layer sandwiched between the metal gate and the HfZrO_x thin film effectively blocks the migrations of metal ions into the ferroelectric layer during the rapid thermal annealing (RTA) process, preventing the device from a high gate leakage current. Our devices show a low gate leakage current of <100 pA during operation (Fig. S2). In our study, those samples without the intermediate TiN layer suffered from significant leakage current after RTA. Next, a thin dielectric HfO₂ layer (∼5 nm) was deposited on the sample to passivate the ferroelectric surface. Figure 1(b) shows the cross-sectional transmission electron microscopy (TEM) image, focusing on the gate stack of the device. The channel material, monolayer MoS₂, was first synthesized on a SiO₂/Si substrate using our previously reported CVD method²³ and was then transferred onto the hybrid HfO₂/ferroelectric HfZrO_x substrate through the wet transfer technique.

An optical image of the fabricated single-layer MoS₂ FeFET is shown in Fig. S4(a), and an AFM image focusing on the MoS₂ channel is also displayed in Fig. S4(b). A thickness of <1 nm evidences the monolayer nature of the MoS₂ channel used in the device. Since the underlying substrates could induce strain and charge doping in the MoS₂ crystals, we first investigate the effect of the hybrid HfO₂/HfZrO_x ferroelectric substrates on the MoS₂ channel. By analyzing the shifts and broadening of phonon peaks in Raman spectra [Fig. S4(c)], we confirm that the transferred sample is slightly n-doped by the HfO₂/HfZrO_x substrate,^24,25 1% tensile strain in the as-grown MoS₂ was relaxed after the transfer process,²⁶ and no significantly defective crystal structure was introduced during the transfer process. More detailed discussion on Raman and PL spectra is given in the supplementary material.

The ferroelectric properties of the as-grown HfZrO_x thin film were characterized through fabricating ferroelectric capacitors of Au/TiN/HfZrO_x/TiN/Ni with a metal/insulator/metal (MIM) structure [Fig. 2(b), insets and Fig. S8(a)]. It was found that the ferroelectric capacitor reaches a larger remnant polarization (P_r) of 48 μC/cm² with a coercive voltage (V_c) at ∼2 V when annealed at 400 °C [Fig. 2(a)]. Such a sharp polarization-voltage (P-V) hysteresis loop suggests that the leakage current through the MIM capacitors is sufficiently low.^27,28 The XRD examination reveals that the ferroelectric orthorhombic phases [o(111) and o(200)] can be substantially formed at 400 °C with suppression of the undesired monoclinic phase, and the width of the o(111) peak becomes shaper compared to 375 °C, indicating a higher crystallinity [Fig. S8(b)]. Figure 2(b) shows the capacitance-voltage (C-V) characteristic at 1 kHz of the ferroelectric capacitor annealed at 400 °C. The butterfly-shaped hysteresis curve showing the two clear polarization states is another evidence of good ferroelectricity in the as-grown HfZrO_x thin film. The nonlinear response, instead of a monotonic linear curve, again manifests a low leakage current in the as-grown HfZrO_x. The capacitance of the ferroelectric capacitor reaches its maximum at 2.8 μF/cm² at ±1.5 V. As a comparison, a MIM capacitor based on a dielectric HfO₂ thin film (∼15 nm) shows a capacitance of ∼1.4 μF/cm², weakly depending on the applied voltages. Based on the above results, a ferroelectric HfZrO_x thin film annealed at 400 °C was selected for further characterization and fabrication of our MoS₂ FeFETs.

To investigate the intrinsic properties of the as-grown HfZrO_x ferroelectric, the P-V characteristic was modeled using the Landau-Khalatnikov (L-K) equation.²⁹ The Landau coefficients of the as-grown ferroelectric HfZrO_x thin film annealed at 400 °C are extracted to be α = –2.19 × 10¹⁰ cm/F, β = 4.53 × 10¹⁸ cm⁵/F C², and γ = 0 cm⁹/F/C [Fig. 2(c)]. In addition, Gibbs free energy of the as-grown ferroelectric HfZrO_x can be further calculated based on the relationship of $VHfZrOx$ = d$UHfZrOx$/dP (see the supplementary material for details). Figure 2(d) plots the free energy vs charge of the HfZrO_x thin film annealed at 400 °C based on the experimental Landau coefficients. The energy of the as-grown ferroelectric thin film exhibits a two-valley shape, of which the two local minima manifest that there are two stable polarization states available in the as-grown HfZrO_x thin films. The region between those two valleys where d²$UHfZrOx$/dQ² < 0 suggests an unstable negative capacitance state in the ferroelectric, resulting in the observed hysteresis characteristics in the HfZrO_x thin films. The above results based on both experiment and simulation indicate good ferroelectricity in the as-grown HfZrO_x and reinforce its candidacy of being a gate insulator for applications in FeFETs.

Next, we demonstrate back-gate FeFETs based on our CVD-grown monolayer MoS₂ integrated with the as-grown ferroelectric HfZrO_x thin films. As shown in Fig. 1(a), the surface of the ferroelectric HfZrO_x is passivated by a thin HfO₂ layer (∼5 nm) to prevent the degradation and fluctuation of the ferroelectricity originating from trapping and detrapping centers formed at the semiconductor/ferroelectric interface.^20,30 Figure 3(d) shows the electronic transport properties (I_DS-V_G) of the fabricated CVD monolayer MoS₂ transistor driven by the bottom gate of the ferroelectric HfZrO_x thin film. The transfer characteristics were measured at gate voltages (V_G) sweeping between –3 V and 3 V with various drain-to-source voltages (V_DS). The sweeping direction is from negative to positive and then back to negative. The device shows n-type conduction with a clear counterclockwise, ferroelectric hysteresis loop, which is opposite to the transfer characteristic of a MoS₂ transistor modulated by a dielectric gate insulator (Fig. S3). The counterclockwise hysteresis suggests that the polarization switching nature of underlying ferroelectric HfZrO_x is preserved in the FETs and strongly couples to the single-layer semiconducting MoS₂, giving rise to the resistive switching of the transistor channel. Specifically, during the device operation, when a positive V_G is applied, the polarization of the ferroelectric layer is directed to the MoS₂ channel, which brings the MoS₂ channel into the electron accumulation regime and results in a high drain current as the on state [or the low resistance state (LRS)], as shown in Fig. 3(a). After the V_G is removed, the HfZrO_x layer remains polarized and provides a locally positive electric field on the channel. Therefore, the channel remains conductive as the LRS for the write program until the V_G becomes negative. Once a suitable negative V_G is applied, the ferroelectric polarization changes sign (pointing to the gate), which depletes the electron away from the MoS₂ channel and produces the off state, corresponding to the high resistance state (HRS) for the erase program [Fig. 3(c)]. Such two LRS and HRS retain at V_G = 0 V, which signifies the desired nature of a data storage device. The on current of the MoS₂ FeFET increases as the V_DS increases and a large write/erase ratio of >10³ between the LRS and HRS can be obtained at lower V_DS. Note that FeFET memory devices typically show a larger dynamic range (or on/off ratio) than that of two-terminal resistive switching devices such as phase change memory and resistive random access memory.³¹ This feature of wider programmable conductance range offers FeFETs a better weight mapping capability for improving the training accuracy of the machine-learning related algorithms in which the weight range is mapped to the conductance range of the memory devices. Figure 3(e) shows the dynamic write/read/erase/read processes of the MoS₂ FeFET by applying alternating pulses onto the gate. Voltages applied to the gate of write, erase, and read were +3 V, –3, and 0 V, respectively. The dynamic write/read ratio is over 10² under V_DS = 0.4 V. From the transfer characteristic, we note that the MoS₂ FeFET shows as a higher off current of 10⁻⁹ A than that of our typical CVD MoS₂ transistor using a SiO₂ dielectric gate stack, suggesting a higher degree of electron doping level in the channel of the MoS₂ FeFET. This can be attributed to the charge transfer between the CVD MoS₂ and the HfO₂ passivation layer that leads to n-type doping of the MoS₂ channel, as observed from the Raman and PL spectra shown in Figs. S4(c) and S4(d). Further improvement in the on/off current ratio of the MoS₂ FeFETs should be able to achieve through reducing the charge transfer at the MoS₂/HfO₂ surface, for example, by introducing a few layers of chemically inert 2D hexagonal boron nitride (hBN) that physically separate the MoS₂ channel and HfO₂.

On the other hand, compared to other 2D FeFETs reported in previous studies, we note that our MoS₂ FeFET can reach one order of magnitude higher current at the LRS with a much smaller driving voltage (±3 V), indicating a more efficient gate control in our device. For example, the 2D FeFETs using ferroelectric P(VDF-TrFE) and 2D CuInP₂S₆ show an on current of ∼10⁻⁷ A with switching voltages of ±40 V and ±5 V, respectively.^17,18 The ferroelectric hysteresis loop in the I_DS-V_G characteristics of the MoS₂ FeFET can be further modulated by applying different gate biases [Fig. 3(f)]. With a larger V_G, a larger hysteresis loop can be obtained, illustrating the on/off current ratio of the MoS₂ FeFET is controllable through adjusting the gate bias. A clear ferroelectric hysteresis characteristic with two distinct states can maintain even at a smaller V_G range, although the corresponding on/off ratio decreases. It is likely that the thin HfO₂ layer inserted between the semiconducting MoS₂ channel and the ferroelectric HfZrO_x layer plays two crucial roles: (i) preserving the ferroelectricity of the underlying HfZrO_x through surface passivation and (ii) lowering the threshold switching voltage of the device. First, it was reported that in the organic FeFETs, there exists polarization fluctuation at the semiconductor/ferroelectric interface.³⁰ Such polarization fluctuation can be suppressed by placing a thin buffer layer of PMMA between the channel and ferroelectric insulator, thus improving the device performance. Accordingly, the thin layer of HfO₂ in our device could act as a buffer layer that suppresses the polarization fluctuation and retains the ferroelectricity. Second, since the thin dielectric HfO₂ layer exhibits a finite capacitance with a free energy of $UHfO2$ = Q²/2 $CHfO2$ (Fig. S6), when connected in series to the ferroelectric layer, the energy of the hybrid HfO₂/HfZrO_x gate stack can be redistributed to U_gate (=$UHfZrOx$ + $UHfO2$⁠).³² Figure 2(d) illustrates the total energy of the hybrid HfO₂/HfZrO_x gate stack based on the experimentally extracted Landau coefficients and the measured capacitance. It can be seen that the presence of the thin HfO₂ passivation layer in the gate stack effectively lowers the energy barrier between the two polarization states in the ferroelectric, which is fundamentally associated with the threshold of the switching voltage for a ferroelectric-based device. Therefore, the ferroelectric characteristic in FeFETs is able to appear when a sufficient gate bias is applied. As can be seen in Fig. S7, a MoS₂ FeFET without the thin HfO₂ passivation layer shows no ferroelectric characteristics at the same range of gate bias, indicating the significance of the presence of the thin HfO₂ passivation layer in the device. Table S1 summarizes the key parameters of the reported FeFETs using different ferroelectrics and channel materials. Among these devices, the FeFET based on the CVD MoS₂/HfZrO_x heterostructure shows the feature of low-power consumption. Finally, we demonstrate the synapticlike behavior from our MoS₂ FeFET. Figure 3(g) displays the dynamic response of the MoS₂ FeFET-based synapse by applying sequences of pulsed voltage stimulations with identical amplitudes, durations, and intervals, and the change in channel conductance was simultaneously monitored. The conductance of the device increases and decreases with the sequential electrical excitations in a stairlike way, thus producing multilevel conductance states. Such programmable and cumulative conductance fundamentally benefits from the nature of multidomain switching dynamics in the ferroelectric HfZrO_x gate oxide [Fig. 3(b)]. The fraction of the ferroelectric polarization charge in the certain orientation can be increasing with the sequential pulsed stimulations. Then, the changes in the net polarization charge modulate the transistor threshold voltage, and therefore, the channel conductance (at a fixed gate read voltage). The observed potentiation and depression of the conductance dynamics and the low-voltage-driven characteristic of the CVD MoS₂ FeFETs promises future applications in electronic synapses for artificial neural networks (i.e., machine/deep learning).^33,34 Our results have provided preliminary but important insights into the design and integration of synthetic TMDs and HfO₂-based ferroelectrics for energy-efficient 2D memory devices.

In summary, 2D FeFETs using CVD-grown monolayer MoS₂ and a hybrid HfO₂/HfZrO_x ferroelectric gate insulator have been demonstrated. The devices show memory hysteresis characteristics and feature a low operating voltage, a good on/off ratio, multilevel conductance states, and an insignificant leakage current at room temperature. The ferroelectric characteristics of the devices can be further modulated by the gate biases. The thin HfO₂ layer in the gate stack effectively passivates the ferroelectric surface to stabilize the device operation and enables lower switching voltages though the energy redistribution of the gate stack. The 2D FeFETs exhibit programmable, cumulative conductance for electronic synapse applications. Based on our FeFETs structure, the integration of synthetic 2D semiconducting TMDs and inorganic HfO₂-based ferroelectrics shows great promise for future applications in large-scale high-performance nonvolatile memory and neuromorphic computing systems.

See the supplementary material for Figs. S1–S8, CVD and transfer processes of MoS₂, process flow of the device fabrication, discussion on the MoS₂ Raman and PL characterization, and method for the Gibbs free energy calculation.

This work was supported by Mitsubishi Electric Research Laboratories (MERL) at Cambridge, Massachusetts, USA. The authors acknowledge the support from Microsystems Technology Laboratories, Professor Tomás Palacios' group, Professor Caroline Ross' group, and Professor Jesus del Alamo's group at the Massachusetts Institute of Technology. P.C.S., H.W., and J.K. acknowledge the financial support from the Center for Energy Efficient Electronics Science (NSF Award No. 0939514) and the U. S. Army Research Office through the Institute for Soldier Nanotechnologies at MIT, under Cooperative Agreement No. W911NF-18-2-0048, and the helpful discussions and technical support from Yuxuan Lin and Ahmad Zubair from Professor Tomás Palacios' group.