In this Letter, a series of metal-insulator-semiconductor capacitors consisting of Si_{3}N_{4} dielectrics with different thicknesses on GaN have been fabricated to investigate their interface states. The measurement value extracted from ultraviolet assisted capacitance-voltage methods can be explained by the existence of spatially uniform hole traps in Si_{3}N_{4}. An improved model combining the effects from interface states and hole traps in Si_{3}N_{4} is proposed to extract the interface state density ($Dit$) accurately. Based on the model, $Dit$ can be obtained by extrapolating the trap density to a zero-thickness dielectric. The extracted average $Dit$ value of the Si_{3}N_{4}/GaN interface is ∼3.8 × 10^{11} cm^{−2 }eV^{−1}, and the hole trap concentration in Si_{3}N_{4} is ∼3.1 × 10^{18} cm^{−3}. The results, model, and analysis presented here provide new insights into studying $Dit$ of various dielectrics on GaN and other wide-bandgap semiconductors.

Wide-bandgap (WBG) materials, such as GaN and SiC, have boosted the development of RF power electronics dramatically, providing high operation voltage, low on-resistance, and high output power.^{1,2} Developing high-quality gate dielectrics on WBG semiconductors is crucial to achieve low gate leakage and high operation voltage in metal-insulator-semiconductor field effect transistors (MISFETs) and metal-insulator-semiconductor high electron mobility transistors (MISHEMTs).^{3} The interface state density ($Dit$) of dielectrics on WBG semiconductors is one of the key performance metrics to assess the quality of dielectrics. In WBG semiconductor based MISFETs and MISHEMTs, high $Dit$ at the interface between the gate dielectric and the channel is detrimental to device performance and can cause inefficient Fermi level response and poor gate control.^{4} Moreover, when poor-quality dielectrics passivate the access regions, interface states with a relatively long time constant can lead to current collapse and reduce the maximum current.^{5–7}

In order to improve and optimize the dielectrics on WBG semiconductors, an accurate method to evaluate $Dit$ is required. The conventional Terman method, high-low frequency method, and conductance method, well-established for the SiO_{2}/Si system,^{8} may not be an effective way to measure the whole bandgap $Dit$ distribution for WBG semiconductors due to the low minority carrier generation rate in WBG semiconductor systems.^{9} Deep Level Transient Spectroscopy and Deep Level Optical Spectroscopy^{10,11} probe a fraction of the gap depending on temperatures or the availability of incident light wavelengths.^{12} An effective and efficient approach developed, to date, for characterizing $Dit$ on WBG semiconductor systems is the photo-assisted high-frequency capacitance-voltage (C-V) method.^{12–16} However, in this method, the effect from traps in bulk dielectrics has been ignored, which may result in an inaccurate extraction of $Dit$.^{8,17,18}

In this work, using ultraviolet photo-assisted capacitance-voltage (UV-assisted C-V) methods, an improved physical model and analysis are proposed to extract $Dit$ accurately by accounting for the effects of dielectric hole traps through a series of metal-insulator-semiconductor capacitors (MISCAPs) with various dielectric thicknesses. The MISCAPs consist of *in situ* grown Si_{3}N_{4} (SiN) on N-polar GaN. SiN is often used as the effective passivation dielectric for GaN HEMTs.^{7} Moreover, devices based on N-polar GaN have demonstrated tremendous potential for high power and high frequency electronic applications.^{19,20} Therefore, the accurate $Dit$ determination of SiN/N-polar GaN is of great interest.

The cross-sectional schematic of SiN on N-polar GaN MISCAPs is shown in Fig. 1. The epitaxial layers are grown by metal organic chemical vapor deposition (MOCVD) on c-plane sapphire substrates misoriented by 4° toward the a-plane.^{21} The doping concentrations for 800 nm n+ GaN and 600 nm n− GaN are 2.5 × 10^{18} cm^{−3} and 2.5 × 10^{17} cm^{−3}, respectively. SiN with different thicknesses (5 nm, 10 nm, 20 nm, and 30 nm) was grown *in situ* at 1030 °C. The dielectric thickness was measured by X-ray reflectivity and ellipsometry. The difference between them is within the range of 5%. The ohmic contact to n+ GaN was formed by etching ∼200 nm into the n+ GaN layer using RIE before Ti/Au (25 nm/200 nm) was deposited as the gate and Ohmic electrodes. All measurements were performed using an Agilent B1500 semiconductor device analyzer equipped with medium power source/monitor units and a multi-frequency capacitance measurement unit. The frequency and amplitude of AC signals used for the C-V measurement were 1 MHz and 50 mV, respectively. The DC voltage was swept with a 30-mV voltage step and a 0.6 V/s sweep rate. An EXFO OmniCure1000 spot curing system with a high-pressure Hg lamp filtered between 320 nm and 500 nm was used as the UV illumination source.

There are three main sweep steps for UV-assisted C-V methods as shown in Fig. 2(a).^{12,13} First, the voltage is swept from depletion to accumulation. During accumulation, the device is held for 10 min to ensure that all the traps are filled with electrons, which is considered as the initial state. Second, another C-V sweep from depletion to accumulation is implemented to register the initial state as the *dark curve* in Fig. 2(a). The aforementioned C-V sweeps are done under the dark condition. Third, the device is held at −10 V bias and is UV-illuminated to generate electron-hole pairs for 30 s with a power intensity around 0.18 W/cm^{2}. The free holes generated by UV are captured by the interface traps and bulk dielectric traps, as shown in the energy band diagram in Fig. 2(b).^{22} Note that the dielectric bulk hole traps are taken into consideration in the band diagram, which are generally ignored and can cause inaccurate determination of the interface state density value. The existence of hole traps in SiN after the UV illumination is mentioned by previous studies^{23–26} but not analyzed. In these band diagrams, assuming that the hole trap concentration is low in SiN, for simplicity, we take its valence band and conduction band as straight lines. The electron quasi-Fermi level (*E _{Fn}*) and hole quasi-Fermi level (

*E*) split because of electron and hole generation from UV illumination. After the UV exposure and under the depletion electric field with a bias of −10 V for 10 min or more, free holes leave the SiN and the SiN/GaN interface through the gate contact as shown in Fig. 2(c). The holes captured by interface states and bulk hole traps can be measured by a following C-V sweep from depletion to accumulation, which is referred to as the

_{Fp}*post-UV curve*in Fig. 2(a). During this sweep, the interface states will follow electron the quasi-Fermi level, keep capturing electrons, and become neutralized, resulting in a capacitance ledge. As illustrated in Fig. 2(d), while the interface states are capturing the electrons, the dielectric bulk hole traps also capture the electrons and become partially neutralized, thus contributing to the capacitance ledge as well. In Fig. 2(d), the hole quasi-Fermi level (E

_{Fp}) varies a little as the electron Fermi level (E

_{Fn}) moves across interface states due to the interface E

_{Fp}pinning.

^{13}

Based on the two measured curves, *dark curve* and *post-UV curve*, the interface state density and dielectric hole trap concentration after UV illumination can be calculated. The *dark curve* is shifted to match the capacitance value *of the post-UV curve* in the deep depletion regime as shown in Fig. 2(a). The voltage shift, $\Delta Vtotal$, is the consequence of the total captured holes. If the hole trap distribution in dielectric bulk is assumed to be homogeneous with concentration $nht0$, $\Delta Vtotal$ can be written as

where $q$ is the electron charge, $Q0$ is the captured hole number at the interface, *ε* is the dielectric constant of SiN, $t$ is the thickness of SiN, $A$ is the device area, and $nht0$ is the hole trap concentration in SiN with unit cm^{−3}. The two terms in Eq. (1) reflect the contributions from the interface and the bulk dielectric captured holes after the UV illumination. The measured curves of MISCAPs with 10 nm and 30 nm SiN are shown in Figs. 3(a) and 3(b), whose $\Delta Vtotal$ values are 0.8 V and 4.8 V, respectively. The measured $\Delta Vtotal$ values vs SiN thickness are plotted in Fig. 3(c). The red dot line is the fitting curve assuming that there is no hole captured in SiN, while the blue solid curve according to Eq. (1) shows the homogeneous distributed hole traps in SiN. The excellent fitting of the latter with a coefficient of determination $R2=0.9996$ confirms the presence of spatially uniform-distributed hole traps in SiN. Furthermore, the $nht0$ value is extracted to be ∼3.1 × 10^{18} cm^{−3}.

In Fig. 2(a), $\Delta V$ can be defined as the voltage difference between the *post-UV curve* and the *shifted dark curve* with the same capacitance value. The negative-charged electron capturing during the *post-UV* sweep results in a larger bias voltage in order to achieve the same capacitance and thus a positive $\Delta V$. As the gate bias swings to the accumulation regime, the magnitude of semiconductor surface potential $\psi s$ gradually reduces and the interface states below the electron quasi-Fermi level continue to populate with electrons and become neutralized. Thus, $\Delta V$ keeps increasing as the corresponding capacitance increases. Moreover, hole traps in the dielectric also capture electrons and contribute to $\Delta V$ with the change in $\psi s$. Then, the total contribution of $\Delta V$ coming from the interface states and the hole traps in SiN can be expressed as

where $Nit$ is the number of captured electrons by interface states, $Cox$ is the insulator capacitance and equal to $\epsilon A/t$, $C(x)$ is the capacitance at the distance $x$ from the metal and equal to $\epsilon A/x$, and $nht$ is the number of captured electrons by the dielectric hole traps per cm^{3}. The first term and the second term in Eq. (2) are the contributions from electron capture by (i) the interface states and (ii) the bulk dielectric, respectively. The interface state density $Dit$ is defined as the number change of captured electrons by interface states per unit area following the change in surface potential,

$\psi s$ can be calculated by the GaN depletion region width from the measured series capacitance composed of the insulator capacitance and the semiconductor capacitance. To connect Eq. (3) with $\Delta V$, we take the derivative of $\Delta V$ in Eq. (2) with respect to $\psi s$ and multiply by $Cox/(A\xd7q)$. The parameter is named as trap density $Dt$,

where $Dt$ combines the effects from the interface states and the dielectric hole traps. The second term in Eq. (4) represents the contributions from $dnht/d\psi s$ with unit cm^{−3} eV^{−1}, which is related to the dielectric hole trap distribution on the energy scale. $Dt$ has a linear relationship with dielectric thickness $t$ if $dnht/d\psi s$ remains constant. The $Dt$ values for 10 nm and 30 nm SiN are shown in Figs. 4(a) and 4(b) along with their average $Dt$ in the range of *E _{C}* to

*E*-2eV, where

_{C}*E*is the energy of the conduction band bottom. The average $Dt$ is typically used to characterize the overall interface state density.

_{C}^{14,16,27}As shown in Fig. 4(c), the average $Dt$ values for different thicknesses are summarized and $Dit$ can be extracted according to Eq. (4). The good linear fitting indicates that $dnht/d\psi s$ has a constant value of 3.35 × 10

^{17}cm

^{−3 }eV

^{−1}. A possible reason for the constant $dnht/d\psi s$ can be explained as follows. For amorphous SiN, previous studies demonstrated a “band tail” existing above the valence band, which can act as the hole traps in a continuous form.

^{28}When $\psi s$ is changed, the hole quasi-Fermi level only varies a little bit because of the nearly pinning of

*E*as shown in Fig. 2(d). Therefore, as a first-order approximation, the change in hole occupancy with $\psi s$ can be treated as a constant.

_{Fp}The extracted value of the actual average $Dit$ is around 3.8 × 10^{11} cm^{−2 }eV^{−1}, which is lower than the measured $Dt$ without considering hole traps in SiN. Mizue *et al.*^{15} did not consider the effect from bulk Al_{2}O_{3} hole traps in the Al_{2}O_{3}/AlGaN system and reported a minimum interface state density value of 1 × 10^{12} cm^{−2 }eV^{−1} near the bottom of the conduction band using photo-assisted CV methods, which is overestimated when compared to (1–3) ×10^{11} cm^{−2 }eV^{−1} from the Terman method.^{29} Using UV-assisted C-V methods, Swenson and Mishra^{13} also obtained the overestimated interface state density value for SiN/GaN. The analysis demonstrated in this study suggests that the overestimated values can be obtained by describing $Dt$ as the actual $Dit$.

The methods developed here are very useful to study the dielectrics on GaN or in general WBG semiconductors, in terms of two aspects. First, the actual interface state density can be extracted when the $Dt$ fitting line is extrapolated to zero-thickness, which is the exact interface ideally. The methods pointed out a direction for the accurate interface state density measurement since a MISCAP device with a real zero-thickness dielectric cannot be fabricated. By accounting for the bulk effects in dielectrics, a series of MISCAPs with different thicknesses can achieve this “zero-thickness” idealization. Second, the parameters $nht0$ and $dnht/d\psi s$ can set up a comparable value to evaluate the quality of the bulk dielectrics. To some extent, $nht0$ is an overall indicator for the bulk dielectric structural imperfections. Also, $dnht/d\psi s$ can provide information of dielectric trap distribution across the energy scale. In all, the two aspects quantified in this study can be critical for evaluating and improving the quality of dielectrics, which may determine the gate leakage, breakdown voltage, DC-RF dispersion, and reliability during device operations.

In summary, we have analyzed the interface states of SiN on N-polar GaN systematically through a series of dielectrics with different thicknesses. Our results indicated the existence of uniform hole traps in bulk SiN after UV exposure. An improved model including the effect of SiN hole traps is derived and applied to extract the accurate $Dit$ value. The average $Dit$ is ∼3.8 × 10^{11} cm^{−2 }eV^{−1} after extrapolating the measured trap density to the zero-thickness dielectric. Also, new hole trap parameters in SiN from the analysis are proposed as potential evaluation for the quality of dielectrics grown on semiconductors. The model and analysis can potentially pave the way for accurate determination of $Dit$ in dielectrics on GaN and can be extended to other WBG semiconductor systems as well. Based on the accurate $Dit$ data obtained from the model, researchers are able to optimize the dielectrics on WBG semiconductors.

The authors thank Dr. Xun Zheng, Dr. Brian Romanczyk, and Christian Wurm for helpful discussions on this manuscript. This work was financially supported by the Office of Naval Research (monitored by Dr. Paul Maki).

## References

_{X}passivated N-polar GaN MIS-HEMTs on sapphire with high f

_{max}⋅V

_{DS,Q}

_{2}dielectric and Al

_{2}O

_{3}interfacial passivation layer grown by atomic layer deposition

_{3}N

_{4}/AlGaN/GaN-metal-insulator-semiconductor heterostructure field effect transistors

_{2}interface

_{2}/SiC interfaces

_{3}N

_{4}/GaN interface

_{2}O

_{3}/GaN metal-oxide-semiconductor structures

_{2}O

_{3}/AlGaN/GaN structures and state density distribution at Al

_{2}O

_{3}/AlGaN interface

_{2}/AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors by use of ac transconductance method

_{3}N

_{4}and SiO

_{2}grown in-situ on 000-1 N-polar GaN

_{3}N

_{4}/GaN(0001) interface

_{2}O

_{3}on Ga-face GaN metal-oxide-semiconductor capacitors

_{2}O

_{3}/n-GaN structure prepared by atomic layer deposition