Two buffer traps at EC-0.7 eV and EC-0.8 eV have been individually identified as causing threshold voltage and on-resistance instabilities in β-Ga2O3 Si -doped transistors grown by plasma-assisted molecular beam epitaxy (PAMBE) on semi-insulating Fe doped β-Ga2O3 substrates. The instabilities are characterized using double-pulsed current-voltage and isothermal constant drain current deep level transient spectroscopy. The defect spectra are compared between transistors grown using two different unintentionally doped buffer layer thicknesses of 100 nm and 600 nm. The EC-0.8 eV trap was not seen using the thicker buffer and is shown to correlate with the presence of residual Fe in thePAMBE buffer layer. The EC-0.7 eV trap was unchanged in concentration and is revealed as the dominating source of the threshold voltage instability. This trap is consistent with the characteristics of a previously reported intrinsic point defect [Ingebrigtsen et al., APL Mater. 7, 022510 (2019)]. The EC-0.7 eV trap is responsible for ∼70% of the total threshold voltage shift in the 100 nm thick buffer transistor and 100% in the 600 nm thick buffer transistor, which indicates growth optimization is needed to improve β-Ga2O3 transistor stability.
Beta-phase gallium oxide (β-Ga2O3) is a promising ultrawide bandgap material for next generation high voltage electronics due to its large bandgap of ∼4.6–4.8 eV,1–3 high theoretical breakdown field of ∼8 MV/cm, and large Baliga figure of merit, meaning that a higher breakdown voltage can be achieved without increasing the device on-resistance. Already, β-Ga2O3 devices with high breakdown voltages and breakdown fields have been reported, surpassing limits of the competitive material systems of GaN and SiC.4–6 Additionally, the large theoretical Johnson figure of merit for β-Ga2O3 devices indicates its potential for RF device applications.7 Recently, cutoff frequencies of 27 GHz, 3.3 GHz, and 3.1 GHz have been demonstrated showing the promise for RF transistors.8–10 One of the most impactful pragmatic advantages of β-Ga2O3 devices for future technology implementation is that β-Ga2O3 is available as large area substrates, meaning that epitaxial devices can be grown homoepitaxially, suggesting that dislocation-mediated degradation might not be a future limiting factor in performance and reliability.11–14
For β-Ga2O3 transistors, however, the ability to grow devices on semi-insulating (S.I.) substrates and/or buffer layers is crucial for achieving maximum device performance. To date, it is typical for S.I. β-Ga2O3 to be formed via intentional doping using Fe or Mg to pin the Fermi level deep within the bandgap. The possible challenge of this is that during device operation, occupancy of these states can vary, creating instabilities in transistor parameters. This phenomenon has been widely reported for GaN RF devices15–17 and is already observed to be an issue for β-Ga2O3 devices.18,19 There is also a concern for the thermal stability of the deep acceptor and donor dopants20 at elevated temperatures and potential diffusion out of a S.I. substrate into epitaxially grown device layers. Recent work has shown diffusion characteristics for Fe, N, and Mg-doped β-Ga2O3.21,22 This work focuses on the issue of Fe diffusion into epitaxial layers and builds from our previous work where two traps, at EC-0.7 eV and EC-0.8 eV, were detected in plasma-assisted molecular beam epitaxy (PAMBE) grown Si δ-doped β-Ga2O3 transistors on Fe doped S.I. substrates.18 Here, a quantitative comparison and trap analysis was performed on β-Ga2O3 δ-doped MESFETs grown on Fe-doped S.I. substrates as a function of the unintentionally doped epilayer thickness between the substrate and channel, commonly called the buffer. This enables clear differentiation between substrate-related and epitaxial layer-related sources of traps.
Two device structures were studied with buffer thicknesses of 100 nm and 600 nm as shown in Figs. 1(a) and 1(b), respectively. These structures were grown by plasma-assisted molecular beam epitaxy (PAMBE) on (010) edge-defined film-fed grown (EFG) Fe doped semi-insulating substrates. The growths were performed in an oxygen-rich condition with a substrate temperature of 700 °C using Si δ-doping to provide charge in the channel.23 This results in high-quality material with Hall channel densities of cm−2 and cm−2 and mobilities of 65 cm2/V s and 105 cm2/V s for the 100 nm and 600 nm devices, respectively.24
The MESFETs were processed by first etching the source and drain contact regions, and then a heavily doped layer was regrown by MBE and patterned through a lift off process with a silicon dioxide mask. A Ti/Au/Ni source/drain metal contact was formed through electron beam evaporation and photoresist lift-off patterning with a one minute anneal at 470 °C in an N2 atmosphere. This MBE regrowth contact process yields contact resistances of ∼0.35–0.44 Ω mm.24 After inductively coupled plasma-reactive ion etching plasma etching for mesa isolation, the Ni/Au/Ni Schottky gates were patterned through lift-off as well. More details of the processing techniques and growth are explained in the work by Xia et al.25 This process resulted in transistors with maximum drain currents, ID, between 140 and 180 mA/mm with a gate source voltage, VGS, set to 0.0 V.
To study the impact of trap-induced instabilities in the transistor structures, two techniques were used: double-pulsed current-voltage (I-V) and isothermal constant drain current DLTS (CID-DLTS). The combination of these measurements allows traps to be characterized individually and the impact of each trap on the transistor stability to be quantified. Along with information learned from other studies, the physical sources of the traps can be identified and strategies to mitigate the trap-induced problems can be developed.
Using a Keithley SCS-4200, with two fast pulse modules, double-pulsed I-V was performed to understand the changes in the threshold voltage (VT) and the on-resistance (Ron). In the pulsed I-V measurements, the quiescent bias controls the quasi-Fermi levels throughout the device, which enables the trap occupation in different regions of the device to be separately controlled during the measurements. Additionally, the characteristic curves can be measured before any significant trap emission occurs by the control of the pulse widths. Self-heating effects can complicate the defect analysis, but the fast pulsing nature of the measurement and low-power quiescent conditions mitigate self-heating effects. These qualities allow the total dispersion between the cases of traps filled and traps empty to be measured. In this study, zero-bias quiescent ( = 0 V) and high-VDS pinch-off quiescent conditions are used.
While pulsed I-V gives insight into how total trapping effects manifest in terminal characteristics, isothermal CID-DLTS is a technique that determines the traps' energies and cross sections through temperature dependent exponential trap emission transients.26 A high-VDS pinch-off trap filling pulse is applied for 100 ms. Then, the device is biased to a fixed low VDS and constant ID in the saturation regime that is maintained by dynamically controlling VGS to record the emission transients. Under these conditions, , where VT is affected by trapping under the gate. The isothermal transients were done in a temperature range of 270 K–360 K in 10 K increments and analyzed following Ref. 26 to extract the time constant of each trap at each temperature. These data are used in an Arrhenius plot to extract the trap energy and cross section and to compare with previously reported data.
To determine the effect of traps on the channel charge in both pulsed I-V and gate-controlled (GC) CID-DLTS using the gate capacitance, the change in the threshold voltage can be calculated as a change in the sheet charge concentration in the channel, which is defined as
where is the β-Ga2O3 permittivity of 10.2 from Refs. 27 and 28, ts is the spacer thickness between the gate and channel, and is the total threshold voltage instability due to one or more traps. The trap concentration allows for comparison of the MESFETs even with different spacer thicknesses.
The results of the pulsed I-V measurements, which are consistent over multiple devices on each sample, indicate significant dispersion in both VT and Ron as shown in Fig. 2. The difference in the curves at each quiescent condition is caused by the change in trap occupation. The zero bias condition is the empty condition with more charge in the channel and a more negative VT, while the high-VDS pinch-off condition has a more positive VT, indicating filled traps and a reduction in channel charge. Under a pinch-off condition with a high-VDS, the channel charge no longer screens the buffer from the electric fields, which allows electrons to be pushed into the buffer as described in Ref. 18. The VT instability was only observed after pulsing with , indicating surface states are not playing a role in the VT instability and the traps are in the buffer. The buffer traps are expected to fill through the raised electron quasi-Fermi level in the buffer due to gate leakage.18 In addition to the threshold voltage shift, there is also an observed dynamic Ron shown in Figs. 2(c) and 2(d), which is also due to trapping effects. While the Ron effects are interesting to study for device performance concerns, this study focuses on the impact of traps on VT. The threshold voltage instabilities measured in this work are done in the saturation regime, which is not sensitive to Ron effects. Additionally, since the traps are in the buffer region, as explained above and in detail in Ref. 18, surface states are not significantly influencing the threshold voltage.
When looking at devices with different layer thicknesses, the measured VT shift itself is not useful to be directly compared because it depends on both the trap concentration and spacer thickness as shown in Eq. (1). The trap concentration is the best metric for comparison because it removes the influence of device design. For example, even though the 600 nm buffer sample's in Fig. 2(b) was about 0.4 V larger than the 100 nm buffer sample in Fig. 2(a), the total , calculated using Eq. (1), is slightly smaller in the 600 nm buffer sample with a concentration of 1.8 × 1012 cm−2 compared with 2.2 × 1012 cm−2 in the 100 nm buffer sample. The larger VT shift with a smaller trap concentration is due to the larger spacer thickness in the 600 nm sample. To compare a device level parameter, an effective can be calculated using the trap concentrations above assuming a 20 nm spacer to allow for a direct comparison of . Using Eq. (1), values of 0.65 V and 0.78 V are calculated for the 600 nm and 100 nm buffer samples, respectively. This calculation indicates a 0.13 V smaller effective in the 600 nm buffer sample, which is consistent with the reduced impact of the Fe-doped substrate on trapping effects which is shown in the defect spectroscopy results next.
Isothermal GC CID-DLTS was done on both MESFETs to identify traps that may be present, which can be linked to the threshold voltage behavior observed in the pulsed I-V measurements. Measurements made on the 100 nm buffer MESFET revealed two distinct electron trap levels, one appearing as the dominant negative peak and the other as a smaller magnitude shoulder, shown in Fig. 3(a). The EC-0.7 eV trap is responsible for ∼70% of the signal, determined by dividing its peak height to the sum of both the EC-0.7 eV and EC-0.8 eV peak heights. In contrast, measurements made on the MESFET with the 600 nm buffer revealed the presence of only one DLTS peak, and therefore, the EC-0.7 eV is fully responsible for the dispersion. The single peak in the 600 nm buffer's spectrum was slightly shifted (∼30 ms) in the main peak time constant. This shift could be due to the higher current level in the 600 nm buffer MESFET. Nonetheless, the correct method to compare traps detected by DLTS in any material or device is to compare the full Arrhenius characteristics for a trap, where the trap emission properties (activation energy and cross section) can be observed over a wide range of temperature measurements, not just at a single peak temperature. This enables unambiguous comparisons. The Arrhenius data for all the detected traps in both MESFET samples are shown in Fig. 3(b). It is clear that the main DLTS peak seen for the 100 nm buffer MESFET aligns with the single trap seen for the 600 nm buffer MESFET, having a trap activation energy of EC-0.7 eV. As will be discussed below, this trap matches a trap seen in several prior works done on gallium oxide material test structures and was attributed to an intrinsic point defect source. The Arrhenius data, in Fig. 3(b), for the shoulder trap seen in the 100 nm buffer MESFET are clearly distinct from the main trap, with an energy level at EC-0.8 eV. Even with the seemingly close energy level positions (0.1 eV difference), the distinct nature of both traps is clear, suggesting different physical sources for each.
The lack of the EC-0.8 eV trap in the 600 nm thick buffer MESFET is telling, especially after considering the Fe concentration profile obtained using secondary ion mass spectroscopy (SIMS), which is shown in Fig. 4. There is a measurable Fe concentration tail extending from the substrate approximately 200 nm into the epitaxial layer before it falls below SIMS detection limits of 1 × 1015 cm−3. Since the 600 nm buffer increases the separation of the Fe doped substrate and the channel, it is proposed that the EC-0.8 eV level's absence in the CID-DLTS links this trap to the presence of Fe impurities in β-Ga2O3. This is due to the regions of higher concentration of Fe being significantly farther from the channel and thus can no longer influence the threshold voltage significantly because of a small channel to substrate capacitance.
To gain more insights into the physical sources for the EC-0.8 eV and 0.7 eV traps, Fig. 5 compiles a wide range of trap Arrhenius characteristics from a wide range of DLTS studies made on β-Ga2O3 substrate materials grown by edge defined film fed growth (EFG) and Czochralski (CZ) methods, on substrates having different crystal orientations, and on materials that had been exposed to high energy particle radiation. The MESFET-based CID-DLTS Arrhenius data are replotted in this figure to compare with prior material-level studies.
The results are unambiguous. First, the EC-0.8 eV trap seen here in the MESFET studies clearly matches a trap that has already been linked to Fe impurities.32,33 In fact, theoretical work has suggested the physical configuration of this defect to be a FeGa substitutional point defect, though it is not yet clear whether the Ga site is the preferential octahedral site (GaII) or the tetrahedral (GaI), both of which have similar energies.32 What is important is the source of this trap is likely to be Fe, as conjectured in this work directly through its contribution to the VT shift on the MESFET. It should be noted in the prior literature, this EC-0.8 eV trap has been labeled as the E2 trap.32,34 Second, the EC-0.7 eV trap observed by CID-DLTS on the MESFET aligns with the previously reported E2* trap, which has been connected to intrinsic defect sources via high energy particle radiation studies using DLTS.31 Moreover, density functional theory calculations predict that several intrinsic point defect structures can generate an energy level in this energy range, including VGa and GaO defects.31 While the precise physical source of this native defect is still under investigation, what is important here is the intrinsic origin of this trap. Considering the large effect this EC-0.7 eV trap has on the measured transistor VT shift indicates significant growth optimization is still necessary to mitigate its effect from ∼1 V to an acceptable level around less than 0.1 V.
In conclusion, two trap levels, at EC-0.7 eV and EC-0.8 eV, are shown to directly cause threshold voltage instabilities in β-Ga2O3 transistors grown by PAMBE on Fe doped gallium oxide substrates. The EC-0.8 eV level has been correlated with FeGa defects, and its impact on the VT instability is mitigated when the buffer thickness is increased. In this device design, a 600 nm buffer is sufficient to mitigate the Fe-related VT instability. On the other hand, the concentration of the EC-0.7 eV level is found to be unaffected by the buffer thickness, which is consistent with its prior assignment to a native point defect source. Since this level is responsible for ∼70% of the VT instability in the 100 nm buffer sample and all the VT instability in the 600 nm buffer sample, it is important to further optimize growth conditions in order to eliminate this primary source for the VT instability that is currently observed for PAMBE-grown β-Ga2O3 devices.
The project or effort depicted was sponsored by the Department of the Defense, Defense Threat Reduction Agency Grant No. HDTRA11710034 (Jacob Calkins, Program Manager). The authors acknowledge the funding support from the Air Force Office of Scientific Research No. FA9550-18-1-0479 (Ali Sayir, Program Manager). This work was also sponsored by NSF under Grant No. NSF ECCS-1809682 and the NSF Graduate Research Fellowship Program under Grant No. DGE-1343012. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the funding provider.