Conduction mechanisms at distinct resistive levels of Pt/TiO_2-x/Pt memristors

Metal-oxide (MO) resistive random access memories (RRAMs) have attracted significant attention as potential candidates for next generation nonvolatile memories¹ that enable applications in neuromorphic^2–4 systems and reconfigurable^5,6 electronics. This interest is fueled by their competitive to standard technology attributes, such as their simple 2-terminal structure and scalability,⁷ along with their ability to change their resistive levels by proper biasings.^8,9 Further maturing the technology requires a thorough understanding of the physics underlying the resistive switching (RS) effect which will eventually pave the way towards commercialization of the envisioned applications through device performance optimization and enhanced reliability.

Bias induced RS effects are typically attributed to either modification of the metal/MO interfacial properties or to the formation and rupture of conductive nano-filaments.^10–12 However, switching is observed on a variety of MO based systems, and depending on the employed core- and electrode materials, these can be classified into different categories including electrochemical (ECM), valence change (VCM), and thermochemical (TCM) memories.¹³ The dominant mechanism thus appears to be case-dependent, but metal-MO interactions strongly affect the RS. Particularly for VCM cells, the application of an electric field results in oxygen exchange reactions, inducing oxygen vacancies.^14,15 A targeted study revealed that introduction of interlayers that suppress oxygen redox reactions significantly affects the switching dynamics.¹⁶ On the contrary, utilization of layers^17,18 or electrodes^19,20 favouring oxygen exchange was found to improve device switching characteristics, further highlighting the importance of metal/MO interfaces. In addition, it is also worth recognizing the important role of the initial electroforming process, typically performed by utilizing current compliance, as it may bring identical devices to discrete resistive levels²¹ potentially attained due to different mechanisms. To date, the majority of reports studying the underlying RRAM mechanisms are focused on a single post-forming condition and are typically performed at room temperature.^10,21–25

This work aims to shine more light on the governing RS mechanisms at discrete resistive levels obtained on identical TiO₂-based RRAM devices by studying the conduction mechanisms dominating the transport across the Pt/TiO_2-x/Pt stacks. Our study is performed via a pulsing-based and compliance-free electroforming process followed by temperature dependent current–voltage (I-V) characterization. Considering a similar field dependence of the various potential conduction mechanisms in wide bandgap materials,²⁶ this temperature study allows identifying the dominant ones, through the corresponding signature plots.

The electrical measurements were performed on Ti(5 nm)/Pt(10 nm)/TiO_2-x/Pt(10 nm) devices fabricated on an oxidized (200 nm SiO₂) six-inch Si wafer. The oxide films were deposited by reactive sputtering (Helios XP, Leybold optics) from a Ti target in an oxygen plasma environment by our standard recipe, described in Ref. 27. The film thickness was calculated using a “Woollam MD2000D Ellipsometer” to be 24.09 ± 0.16 nm,²⁸ and the roughness after the bottom electrode (BE) deposition and atop of the oxide film was 2.322 ± 0.1321 nm and 1.434 ± 0.08461 nm, respectively.²⁹ The material level characterization study performed previously³⁰ on films/stacks fabricated using the same recipe revealed an amorphous sub-stoichiometric nature of the TiO_2−x films with x in the range of 0.05–0.10. The current vs voltage (I-V) characteristics were obtained from 20 × 20 μm² standalone RRAM cells using our in-house memristor characterization platform ArC ONE^TM31 by applying biases to the Pt top electrode (TE) with respect to the Pt bottom electrode (BE) that was continuously kept at ground potential. All experiments were performed on a Cascade SUMMIT 12000B semi-automatic probe station that incorporates a thermal chuck, whose temperature can be controlled by an ESPEC ETC-200L unit. Measurements were carried out in the range of 300 K–350 K, with a 10 K step.

Devices in their pristine state exhibit resistance in the GΩ range attributed to very high interface barriers (Fig. S1 in the supplementary material). Prior to further characterization, the devices underwent a pulsing-based and compliance-free electroforming process at room temperature, as depicted in Fig. 1. This is performed by applying a bespoke time-width train of pulses with progressively increasing amplitude until the device resistance reaches a set limit. This experimental protocol is then repeatedly applied by modifying the resistance limit that allows reaching distinct resistive levels.

For our Pt/TiO_2−x/Pt prototypes presented in this work, three stable resistive levels were attained. Level #1 exhibits resistance on the order of MΩ, level #2 tens of kΩ, and level #3 of kΩ. Fine tuning and programming to specific resistive states around these levels are possible as demonstrated previously.⁹ The room temperature I-V curves, shown in Fig. 2(a), reveal two major operation regimes. The first one corresponds to levels #1 and #2 and thus to higher resistances and is characterized by an asymmetric signature with respect to the applied bias polarity for both their high resistive state (HRS) and low resistive state (LRS). The second one, for the lower resistances of level #3, shows an asymmetric characteristic signature for the HRS, transformed into symmetric for the LRS regime [Fig. 2(b)]. For a metal-insulator-metal (MIM) stack, the asymmetry in the I-V is an important indication of interface-controlled transport in contrast to the symmetric performance that typically arises by the core film area determined conduction.³² This is a preliminary qualitative observation (should be confirmed by the signature plots) which showcases that dissimilar mechanisms are responsible for the RRAM operation at these resistive levels.

In order to shine more light on the responsible mechanisms underneath, the current voltage characteristics have been recorded with temperatures spanning from 300 K to 350 K. This temperature analysis allows for reliable separation between dissimilar conduction mechanisms. For wide bandgap materials, these exhibit a characteristic temperature dependence.²⁶ The dependence can be extracted through the corresponding signature plots, and thus, any potential misinterpretation is minimized.

The device operation at level #1 (corresponding to the MΩ range), apart from being asymmetric, also exhibits a temperature activated conductivity at both LRS and HRS [Fig. 3(b)]. This behavior is a strong indication for transport dominated by Schottky barriers formed at the metal/TiO₂ interfaces that can be described by the following equation:²⁶ 

where K is the Boltzmann constant, T is the absolute temperature, Φ_B0 is the zero bias potential barrier, A includes the area and the Richardson constant, and α is the barrier lowering factor. To verify this, each branch of the I-V [1–4 in Fig. 3(a)] has been assessed independently following the temperature analysis discussed in Ref. 33. The signature plots (Fig. S2 in the supplementary material) lead to the estimation of the apparent barrier that results in the zero bias potential barrier (intercept) and the barrier lowering factor “α” (slope) for each interface [Fig. 3(c)]. The Schottky barrier appears to change from 0.17 eV (branch 2) and 0.2 eV (branch 3) (HRS) to 0.1 eV (branch 4) (LRS) during switching. Moreover, all branches comply with the constant temperature signature plots. This provides strong evidence in support of an interface controlled RS mechanism in the operation regime which corresponds to level #1.

Level #2 exhibits clear Schottky type characteristics in the HRS (Fig. 4), allowing for the calculation of the interface barrier [0.065 eV (branch 2) and 0.055 eV (branch 3)] through the corresponding analysis (Fig. S3 in the supplementary material). Regarding the LRS, this is found to be thermally activated [Fig. 3(b)], showing however very low asymmetry [for Fig. 2(b)], making it difficult to draw clear signature plots and thus calculating the barrier. Considering also the LRS characteristics of level #3, such a behavior can be interpreted as a boundary case at the transition between the two regimes, corresponding to a very low interface barrier.

Following from this, level #3 also demonstrates interface controlled transport for the HRS [Figs. 2(b) and 5 and Fig. S4 in the supplementary material], but the case is different for the LRS. The transport is then dominated by the core-film rather than the interfaces, as demonstrated by the highly symmetric [Fig. 2(b)] and practically temperature independent I-V curves [Fig. 5(b)]. In this case, where the I-V can be expressed as $I∼ Vn+1$⁠, the conductivity is either ohmic (n = 0) or governed by space charge limited currents (SCLC). Considering also the temperature dependence, an ohmic conductivity should exhibit an Arrhenius type activation, whist the SCLCs typically show a very weak or a negligible temperature variation.²⁶ Based on the latter and despite the exponent value, in our case, we may conclude that SCLCs are the most suitable mechanism to describe the conduction mechanism in this regime. Overall, at level #3, the transport switches from the interface to the core-material controlled mechanism which can be considered also as a form of interface controlled RS. Comparable operation was reported previously in similar devices that were electroformed using current compliance. This process leads them directly to resistance and switching characteristics corresponding to level #3. For these stacks, the X-ray absorption study did not reveal any structural changes during RS³⁰ which along with our temperature analysis further highlights the important role of the interfaces.

Thus, we may assume that our pulsing-based forming protocol progressively and gently modifies the interfacial barriers. These are further modulated during the I-V sweep by the bias induced charge (due redox processes, electronic trapping/de-trapping, and ionic motions), resulting in RS. The barrier in HRS reaching level #3 (below 20 kOhms, level #2 is considered as the boundary case) appears to be low enough so that the bias induced charge is sufficient to nearly eliminate it (thus, carriers may freely overcome it or to tunnel through it), and therefore, it is the core-film that determines the transport in the LRS.

The control of RS in interfacial RRAM devices by the Schottky barrier offers broad opportunities for optimization. This is because the macroscopically obtained resistance states could be considered as

For a conventional Si-based Schottky type contact, the barrier height Φ is determined by the metal work function, by the doping level, and by the total charge at the interface states and the depleted area (W).²⁶ For the case of metal-TiO₂ contact, we need to consider the metal electronegativity (X_M) instead of its work function^28,34 and the oxygen vacancies (V_ox) as equivalent to doping³⁵ and to bear in mind the important role of the interface states (N_it) as pointed out by recent reports^28,34 on partial Fermi pinning. Qualitatively, this can be expressed as

where a, b, and c are constants having the appropriate units and E_f the Fermi level. Each of the terms in Eq. (3) highlights the directions towards resistive switching engineering in TiO₂ based devices. In particular, defect engineering could turn out to be of great interest along with establishing appropriate biasing schemes that may offer analog performance through bespoke modification of the interfacial barriers.

In summary, a detailed electrical characterization study of the conduction mechanism at different resistive levels of the Pt/TiO_2−x/Pt stack was presented. These levels were attained via a pulsing-based compliance-free forming protocol. The analysis of the temperature dependence for each branch of the I-V switching characteristics of the various resistive levels provides deeper insights into the underlying switching mechanism, and two major regimes were identified. For higher resistive levels, the transport in both HRS and LRS was found to be interface controlled. For the lower resistive level, the transport diverges from the interface to the core-material controlled mechanism for HRS and LRS, respectively. This study supports the argument that bespoke modification of the interface barrier can be obtained, rendering TiO₂ based RRAM as more suitable and reliable for emerging applications.

See supplementary material for the I-V curve of a pristine (pre-electroformed) device and for the signature plots supporting the conduction mechanisms discussed.

This work was supported by EPSRC Grants (Nos. EP/R024642/1 and EP/K017829/1).

All data supporting this study are openly available from the University of Southampton repository at http://doi.org/10.5258/SOTON/D0657.