A high current density of 1 kA/cm2 is experimentally realized in enhancement-mode Ga2O3 vertical power metal-insulator field-effect transistors with fin-shaped channels. Comparative analysis shows that the more than doubled current density over the prior art arises from a larger transistor channel width; on the other hand, a wider channel also leads to a more severe drain-induced barrier lowering therefore premature transistor breakdown at zero gate-source bias. The observation of a higher current density in a wider channel confirms that charge trapping in the gate dielectric limits the effective field-effect mobility in these transistor channels, which is about 2× smaller than the electron mobility in the Ga2O3 drift layer. The tradeoff between output-current density and breakdown voltage also depends on the trap density. With minimal trap states, the output current density should remain high while breakdown voltage increases with decreasing fin-channel width.
Gallium oxide is one of the most important new semiconductor materials for high-power applications. With an experimentally reported critical electric field up to 5.2 MV/cm,1,2 an electron mobility of 100–150 cm2/V s (Refs. 3–5) and low-cost high-quality substrates6 and epitaxial layers,7–9 β-Ga2O3 promises high-voltage and high-power devices with performance at least comparable to those of SiC and GaN. Ga2O3 device technologies have advanced fast in the past 5 years and various lateral channel Ga2O3 transistors including nano-membrane field-effect transistors (FETs),10,11 FinFETs12 and MOSFETs13 have been developed.
Vertical Ga2O3 power devices including power diodes and transistors have great potential in high-power applications. High-voltage Schottky Barrier Diodes (SBD)14 and heterojunction p-n diodes15 with breakdown voltage (BV) >1000 V have been demonstrated. The first three vertical Ga2O3 transistors were reported in 2017 albeit showing no pinchoff or low BVs.16–18 Very recently, we demonstrated the first kV vertical Ga2O3 transistors employing vertical fin-shaped channels (FinFETs); more importantly, these transistors are normally off, i.e., enhancement-mode (E-mode).19 E-mode operation is a desired feature for power transistors since it allows less complicated circuit designs and fail-safe operation under high voltages. Early successes in demonstrating E-mode Ga2O3 FETs are in lateral devices.11,12,20,21 On the other hand, the vertical-FinFET topology allows strong gate electrostatic control by double gating of the channel; the ungated access region between the gate and source thus the transistor source resistance can be minimized while employing a thick drift layer to sustain high voltages, which in turn enables high output currents and high breakdown voltages simultaneously. Such features have been successfully proven in SiC22 and GaN.23 However, the output current density in our recent demonstration in Ga2O3 is significantly lower than expected.
In this work, we investigate Ga2O3 vertical power FinFETs, i.e., vertical power metal-insulator FETs (MISFETs), with a wider fin channel of 0.44 μm than our previous work (0.33 μm).19 We analyze the tradeoff between the output current density and drain-induced barrier lowering (DIBL) thus premature breakdown in these devices, in particular, the impact on this tradeoff from the dielectric/channel interface states. DIBL, a type of short channel effects, has adverse impacts on threshold voltages (Vth) and high-frequency performance of ultra-scaled transistors.24 High-power transistors usually do not suffer from high DIBL due to relatively large gate length to channel width aspect ratio; thus, device breakdown is induced by channel avalanche or gate leakage. However, under high operation voltages of hundreds to kilos of volts, Vth shifts may be significant, which could lead to Vth roll-off from E-mode to depletion-mode at high Vds. As a result, some E-mode transistors achieve highest BVs under negative gate bias.25–27 In addition, power transistors usually have thick gate dielectrics for suppression of gate leakage currents. The dielectric/channel interface states may lead to extra DIBL that requires carefully analysis.
The wafer structure contains a 10 μm epitaxial layer with a target Si concentration of 2 × 1016 cm−3 grown by halide vapor phase epitaxy (HVPE) on n-type bulk β-Ga2O3 (001) substrates (n ∼ 2 × 1018 cm−3). The schematic device structure is shown in Fig. 1. Key components of the device include n+ ion-implanted top-source and back-drain contacts using Si as donors, a vertical fin-shaped FET channel defined by dry etching, a 30 nm thick Al2O3 gate dielectric deposited by atomic layer deposition (ALD), a 50 nm thick sputtered Cr gate metal, and a 200 nm SiO2 spacer separating the source and gate electrodes. The details of device fabrication can be found in Ref. 17. Devices with a channel width (Wch) of both 0.44 μm and 0.33 μm were fabricated, and the vertical gate length (Lg) for all devices is 0.80 μm, as confirmed by measurements using scanning electron microscope (SEM).
C-V measurements on vertical MIS capacitor structures reveal a charge concentration Nd − Na of 1.2 × 1016 cm−3 in the top ∼1 μm and a gradual transition to ∼1 × 1015 cm−3 in the deeper epitaxial region.19 Devices with a Wch of 0.33 μm show characteristics similar to what were reported in Ref. 19. For the vertical power FinFETs with Wch = 0.44 μm, the Id − Vgs transfer curves in linear and semi-log scales are shown in Fig. 1(b). A high current on/off ratio of ∼109 and an on-current of >1 kA/cm2 (normalized to the area of the source contact) is measured, which is ∼2.5× of that in the 0.33 μm devices.19 The subthreshold slope (SS) is extracted as ∼80 mV/dec near the drain current of 1 mA/cm2. Since the SS of a MOSFET is written as28
where k is the Boltzmann constant, T is the temperature, q is the elementary charge, Cd is the depletion capacitance of the channel (in the sub-threshold region, Cd ∼ 0 in double-gated junctionless MISFETs including FinFETs), Cox is the capacitance per unit area associated with the gate dielectric, and Dit the interface state density. We can thus estimate Dit to be >6 × 1011 cm−2 eV−1. This value is comparable to a few other reports on interface state extraction using Ga2O3 MOS capacitors.29,30Vth extracted by linear extrapolation of the drain current is ∼1.6 V. Alternatively, if we use a criterion of Id = 1 mA/cm2, Vth is determined as ∼0.94 V at Vds = 10 V. For the rest of the discussion, we choose to use the latter Vth criterion for convenience of the DIBL analysis. The peak gm at Vgs = 2.25 V and Vds = 10 V is ∼850 S/cm2.
The family of Id − Vds curves of the same vertical FinFET is shown in Fig. 2. The drain current density reaches ∼750 A/cm2 with a Vgs of 3 V and a Vds of 10 V. This magnitude of Id is lower than that in the transfer I-V due to device self-heating and Dit. The differential on-resistance Ron calculated near Vds = 0 V is ∼7 mΩ cm2. The transistor shows a noticeable output conductance since an aspect ratio 2Lg/Wch of ∼3.6 is not high enough to completely suppress the DIBL effects. In Fig. 3, the transfer I-V of the same device is shown at varied Vds biases. In order to minimize the effect from Dit, Vgs is swept from 0 V to 3 V with the same sweeping rate in all three curves. The DIBL effect, defined as DIBL = ΔVgs/ΔVds, is measured to be 18 mV/V near the current density of 1 mA/cm2.
Figure 4 shows the off-state Id/Ig − Vds characteristics of representative FinFETs with the same Lg/Wch dimensions. At Vgs = 0 V, a BV of ∼560 V is measured. A soft breakdown behavior of the drain current appears at Vds > 380 V while the gate current stays low at the instrumentation limit. This suggests that the transistor breakdown at Vgs = 0 V is limited by DIBL. To further probe this hypothesis, another set of devices were measured under negative gate bias. At Vgs = −1 V, much higher BVs of up to ∼960 V are observed; moreover, both gate and drain currents increase abruptly and simultaneously at breakdown, which is destructive. These observations exclude the likelihood of avalanche breakdown at Vgs = 0 V, thus confirming DIBL is the dominant mechanism.
For double-gated junctionless MISFETs (i.e., FinFETs) with symmetric source and drain where Lg is the distance between the source and drain, which are often found in logic applications, we can derive the dependence of the Vth shift on channel geometry and Vds based on the framework in Ref. 31 as
where for the depletion mode operation, and ϕmin is the minimum central channel potential with respect to the source, determined from 2-D numerical device simulation to be about −0.3 V in the device shown in this work. When the channel thickness Wch is much larger than the oxide thickness tox, it can be seen that the DIBL effect diminishes exponentially with an increasing Lg/Wch ratio. For a fixed Lg, an increment in either oxide thickness or channel width leads to a worse DIBL. Therefore, the aspect ratio 2Lg/Wch can be roughly applied to determine the degree of DIBL. In high voltage transistors, the thick n-drift layer sustains most of the voltage drop, thus effectively screening the gated channel from the high voltage on the drain. Therefore, the DIBL effects are expected to weaken compared to the FinFETs for logic applications, and Eq. (2) no longer gives accurate predictions on DIBL effects. Due to the complexity associated with the thick drift region, edge termination near the gate as well as the interface states, 2-dimensional simulations using Sentaurus are employed for the quantitative analysis of DIBL in these vertical Ga2O3 power FinFETs.
In Fig. 5, simulated DIBL as a function of Vds and Dit using the experimentally determined values of Lg, Wch, and Nd are shown together with the experimental data. In the simulation, uniformly distributed interface states across the energy band gap are assumed, with the charge neutrality level near the mid-gap. All DIBL values are calculated at a drain current level of 1 mA/cm2. It is observed that DIBL decreases and the accumulated Vth shift increases (see Fig. 6) non-linearly [in contrast to the linear prediction in Eq. (2)] with the increase in Vds due to the screening effect of the thick drift layer. The existence of interface states indeed exacerbates DIBL effects, and the experimental data compare favorably with the simulated results assuming Dit ∼ 3× 1012 cm−2 eV−1. The inset shows the DIBL at Vds = 1 V as a function of the channel width Wch with the same gate length. It is worth mentioning that with this level of Dit, the DIBL values are almost doubled compared to the case without interface states. The impact of Dit ∼ 3 × 1012 cm−2 eV−1 on DIBL is equivalent to an increase in channel width from 0.44 μm to ∼0.55 μm.
Figure 6 shows the simulated Vth shift as a function of Vds with and without the impact of interface states. For each curve in this figure, the net Vth shift ΔVth(Vds) is defined as Vgs(Vds) − Vgs(Vds = 1 V) at Id = 1 mA/cm2 From Fig. 3, the experiment data at 1 V, 5 V, and 10 V are extracted from Vgs = 1.093 V, 1.004 V, and 0.935 V at Id = 1 mA/cm2; from Fig. 4, we observe Vds ∼ 446 V at Vgs = 0 V and Id = 1 mA/cm2 thus the net Vth shift can be calculated to be −1.093 V at Vds ∼ 446 V. The comparison between the simulations and experimental results indicate the presence of Dit with a value of ∼3 × 1012 cm−2 eV−1 under the bias conditions considered here, and that the breakdown mechanism in these devices is dominated by DIBL effects exacerbated by Dit. Based on the simulation, it is expected that a MISFET with the same geometry but an optimized interface treatment would have a DIBL-limited BV beyond 1 kV. In addition, it is observed that the Vth shift curve for devices with a Wch of 0.55 μm and zero interface states roughly aligns with the curve for devices with a Wch of 0.44 μm and a Dit of 3 × 1012 cm−2 eV−1 at all voltages. This further confirms that the existence of interface states is equivalent to a wider channel in terms of their impact on DIBL. The simulation also indicates that though DIBL is reduced at higher Vds, the Vth shift (integration of DIBL with respect to Vds) shows no trend of saturation, thus remaining a challenge for high voltage transistor operations.
The impact of the interface states on DIBL is illustrated in the band diagrams in Fig. 7 and intuitively explained in the following. Under a fixed Vgs bias, on the source side [Fig. 7(a)], the electron quasi-Fermi (Efn(s)) level is determined by the source ohmic contact. All the acceptor-like dielectric/channel interface states below the energy Efn are occupied by electrons, hence negatively charged, which is believed to be true in our devices. The built-in potential is expected to be ϕms ∼ 0.5 V between the n-type Ga2O3 and Cr gate; however, the measured Vth is found to be 1.6 V; thus, we infer that a negative sheet charge Qit of −2 × 1012 cm−2 is present at the Al2O3/Ga2O3 interface at Vth. Since this Qit exceeds the total donor density in the channel (∼2.6 × 1011 cm−2), the electric field in the gate oxide points in the opposite direction from that in the channel. Under a high voltage from the drain, the channel closer to the drain [Fig. 7(b)] has a higher potential; therefore, Efn(d) is at a lower energy level with respect to the conduction band. This causes fewer interface states to be occupied near the drain end, thus lowering the negative interface charge density. This results in two effects that exacerbate DIBL: (1) less negative charge on the dielectric/channel interface reduces the energy barrier in the channel; (2) a gradient in the interface charge density exists from the source end to the drain end, which generates an extra electric field parallel to current flow. Since this electric field points from the drain to the source, it lowers the barrier height in the channel (c), hence leading to a stronger DIBL effect. In a long channel FET with a larger Lg/Wch aspect ratio, the gradient of the interface charge density is smaller near the center of the channel; thus, the impact of Dit on DIBL is weakened. The same trend is also observed in the inset of Fig. 5.
Transistor analysis reveals that the existence of dielectric/channel interface states and charge trapping reduces the gate modulation efficiency and prevents the device from operating in the accumulation mode. The presence of trap states is confirmed in this experiment in that transistors with narrower channels show lower maximum output current densities and higher on-resistances than those with wider channels at the same gate overdrive voltage. Using a dielectric/channel interface state density of Dit ∼3 × 1012 cm−2 eV−1, it is estimated that ∼50% of the 0.44-μm wide fin-shaped channel is depleted even at a gate voltage of 3 V. The effective electron field effect mobility in the channel is about 30 cm2/V s, ∼2× smaller than the estimated electron mobility in the HVPE Ga2O3 drift layer, which is in turn extracted from the on-resistance of Schottky barrier diodes on the same wafer. A mobility of 60 cm2/V s in HVPE Ga2O3 with a net dopant concentration ND − NA in the range of 1015–1016 cm−3 is lower than ∼150 cm2/V s reported in bulk Ga2O3.3 It is likely due to the presence of compensating centers, which merits further investigations. Given a large gate length (≫1 μm) is quite challenging to achieve in these vertical power FinFETs, reducing dielectric/channel interface Dit and charge trapping is key to mitigate the tradeoff between on-resistance (i.e., output currents) and DIBL for kV switches.
In conclusion, E-mode vertical Ga2O3 FinFETs with an output current higher than 1 kA/cm2 and a BV near kV are analyzed in this work. A combination of high BV and low Ron leads to a Baliga's figure of merit of 125 MW/cm2, significantly advancing the state-of-the-art Ga2O3 power transistors as shown in Fig. 8. Device simulation and analysis show that a relatively low density of dielectric/channel interface states of ∼1012 cm2 eV−1 leads to nearly doubled DIBL effects in transistors with a Lg/(Wch/2) of 0.8/0.22 μm, which in turn limits the device breakdown as measured in experiments. These trap states also lead to low field-effect mobility in the channel. To this end, it is key to improve the dielectric interface quality; moreover, field plates should be applied to delay premature gate-edge breakdown once the DIBL effects are minimized. The device analysis in this work provides valuable insights on Ga2O3 high-power transistor design and processing in general.
This work was in part supported by AFOSR FA9550-17-1-0048 (Program Manager: Ken Goretta) and NSF DMREF 1534303 (Program Manager: Dr. John Schlueter). This work was performed in part at Cornell NanoScale Facility, an NNCI member supported by NSF Grant No. ECCS-1542081.