Analysis and mitigation of interface losses in trenched superconducting coplanar waveguide resonators Open Access

Dielectric loss associated with two-level systems (TLSs) at material interfaces is a major contributor limiting coherence times and quality factors in superconducting qubit and resonator devices.^1–5 In order to mitigate these losses, previous work has employed a combination of improving materials, optimizing fabrication, and modifying designs.^6–10 Materials and fabrication efforts have focused primarily on lowering the density of TLS defects in bulk materials¹¹ and reducing the presence of TLS-containing dielectrics¹² and chemical residues.¹³ Device geometry and design parameter modifications have in turn been used to reduce device sensitivity to material losses by tailoring the structure's electromagnetic field profile.^14–16 Together, these advances have yielded qubit T₁ times exceeding 50 μs (Refs. 16–18) and resonator internal quality factors (Q_i) reaching 70 million at single photon-excitation powers.¹⁹ 

Despite these remarkable accomplishments, developing a complete understanding of interfacial TLS loss mechanisms has remained a challenge. For example, although materials with reduced TLS losses such as titanium nitride (TiN) have been used to realize high Q_i resonators and long T₁ qubits,²⁰ the results often exhibit poor reproducibility in part due to the metal's sensitivity to ambient oxygen.²¹ Additionally, while improvements in T₁ and Q_i have been demonstrated through the use of substrate trenching to reduce interface participation,^10,22,23 the depth dependence and the degree to which deeper trenching improves device performance remain unclear. Finite-element electromagnetic modeling of dielectric losses can be used to study these effects, but it must be paired with highly controllable and reproducible fabrication processes to make quantitative comparisons between experiment and simulations.

In this work, we present TiN coplanar waveguide (CPW) resonators with quality factors exceeding two million fabricated using a process capable of controlled trenching in the silicon substrate. To analyze losses in these devices, we perform finite-element electromagnetic simulations of a range of resonator geometries in order to analyze interfacial and substrate dielectric losses. We then demonstrate quantitative agreement between measured CPW resonator Q_i values and a model of interface losses. Furthermore, we use this tool to predict the marginal benefits of deep trenching for reducing losses in superconducting CPW resonators. The agreement supports the accuracy of interface participation ratio-based modeling of device losses and indicates future pathways for reducing loss in superconducting devices.

We study superconducting CPW quarter-wave resonators with a center trace width w ranging from 3 μm to 22 μm and gap g to ground ranging from 1.5 μm to 11 μm [see Fig. 1(a)]. The devices were fabricated using a subtractive etch process on high resistivity 200 mm (001) silicon substrates (⁠$≥$ 3500 Ω-cm). Prior to metal deposition, the substrates were prepared using an RCA clean without any oxide removal step in conjunction with megasonication. Without additional oxide removal steps or buffer layers, we reactively sputtered 150 nm of TiN using a titanium target in the presence of argon and nitrogen gas. We patterned the resonators using optical lithography and then etched the metal and underlying substrate using a combination of BCl₃ and Cl₂ gases. The total etch time was adjusted to control the trench depth (d). We then used an in situ oxygen plasma ash followed by an ex situ hydroxylamine-based wet strip to remove the remaining photoresist. Figure 1(b) shows a representative CPW resonator cross-section. With the sole exception of the variable etch time, we use a nominally identical fabrication process for all samples and therefore attribute differences in Q_i to the trench depth and not to changes in the interfacial loss tangents. Further details of the chip design and fabrication process are provided in the supplementary material.

TLS losses in superconducting CPW resonators can be understood by applying an interface participation ratio model similar to those used in Refs. 7, 9, 10, and 14. In this model, the resonator dielectric losses are a linear combination of the loss tangents (⁠$tan δi$⁠) associated with energy absorbing TLSs in each region i, weighted by the fraction of the total electric field energy stored in that region, the participation ratio p_i:

Because each lossy region contains an unknown combination of interface dielectrics and fabrication residues, in our analysis, we assign a unique $tan δi$ to each interface that is exposed to a distinct fabrication process. The participation ratios of the dielectric regions in our devices were calculated using two-dimensional (2D) COMSOL electrostatic simulations.²⁴ We partition the device into the following lossy dielectric regions: the metal-to-silicon (MS, red), substrate-to-air/vacuum (SA, blue), and metal-to-air/vacuum (MA, purple) interfaces and the bulk silicon substrate (Si, green), as depicted by the false coloring in Fig. 1(c). To reduce the computational complexity, the interface participation ratio calculations were performed using 10 nm thick defect layers of a fixed dielectric constant ϵ = 10, despite general uncertainty in the actual interface properties. This results in ambiguity in the resulting values for $tan δi$⁠. However, due to the manner in which participation ratios scale with the thickness and dielectric constant in the limit of a thin layer,¹⁴ we can parameterize $1/QTLS$ in Eq. (1) using scaled participation ratios P_i and “loss factors” x_i that are independent of these quantities and are defined by $∑ipi tan δi=∑iPixi$⁠. For details, see supplementary material. For all resonator geometries, the trench sidewall angle $Φ$ and depth $d$ were determined using cross-sectional scanning electron microscopy in order to accurately model the device electric field distribution. All devices exhibit angled sidewalls with $Φ$ ranging from 93° to 109° depending on the etch time and feature size.

To compare our interface loss simulations with our fabricated device performance, we characterized a series of resonators with a range of geometries by measuring the resonator chip transmission spectrum at 25 mK in a dilution refrigerator. Background ambient magnetic fields were reduced by mounting the package in a superconducting aluminum enclosure surrounded by a high magnetic permeability shield (Cryoperm). In each cooldown, twelve packages each containing a single chip comprising five resonators were measured using two separate measurement chains that incorporated a pair of 1 × 6 microwave switches operating at the base temperature stage of the dilution refrigerator. Each measurement chain included a series of microwave attenuators, filters, and isolators to reduce the samples' exposure to thermal radiation from hotter temperature stages. A broadband traveling wave parametric amplifier,²⁵ a low-noise high-electron-mobility-transistor amplifier, and a room temperature microwave amplifier were used to amplify the transmitted signal before the measurement using a vector network analyzer. Each resonator was measured over a range of internal circulating powers from the single-photon limit up to approximately 10⁶ photons using a non-linear frequency spacing to minimize data acquisition times. Resonator parameters were extracted using the fitting methods presented in Ref. 26. Each device was measured repeatedly in the single-photon limit for approximately five hours, and the results were averaged in order to account for time-dependent Q_i fluctuations. Similarly, multiple copies of the same device were measured to account for device-to-device variations and to establish error bars for each sample set.

Figure 2(a) shows an example of the dependence of Q_i on the number of photons circulating in the resonator. The trend shows the typical saturation behavior of internal losses associated with TLSs. At low internal photon numbers (circulating power), Q_i, which we label Q_LP, is dominated by absorption due to unsaturated TLSs.³ At higher photon numbers, this loss mechanism saturates and Q_i increases until it reaches another limiting value Q_HP. At this power, the losses cease to be dominated by TLSs and are instead dominated by an unknown combination of other mechanisms such as vortices,^27,28 radiation/packaging loss,⁵ and/or non-equilibrium quasiparticles.²⁹ Q_LP and Q_HP shown in Fig. 2(a) are typical of our highest mean Q_i fabrication process with mean Q_i of $2.2×106$ for a sample set of 15 resonators with (w, g, d) = (16 μm, 8 μm, 0.68 μm). Further trenching of these devices was not possible without degrading the etch mask and thinning of the metalization layer. To study the effects of trenching down to a depth of 2.2 μm, we instead fabricate devices using a process similar to the one used for the device set presented in Fig. 2(a) but with a thicker photoresist mask (4 μm vs. 1.1 μm) and a higher temperature post-etch ash. This leads to an approximate and reproducible 15% reduction in mean Q_TLS for a comparable set of devices with this resonator geometry and trench depth. To assess the reproducibility of this fabrication process, for the shallowest trenching shown here (150 nm), we have measured approximately 100 nominally identical resonators and observed that greater than 87% show Q_i values higher than $1×106$ (mean of $1.6×106$⁠).

Although TLSs are generally the dominant source of loss in superconducting CPW resonators at low temperature and circulating power, the losses that persist when TLSs are saturated can still reduce total Q_i and contribute to device-to-device variation. All the resonators we characterized exhibited TLS-saturation behavior similar to the data shown in Fig. 2(a); yet, we observed significant variation in Q_HP. As a result, the differences we observed in mean Q_LP were sometimes dominated by systematic Q_HP variations rather than altered interface participation. This resulted in behavior such as shown in Fig. 2(b) (green points and lines) where no discernible trend in Q_LP vs. trench depth is observed. However, we can independently determine Q_HP by measuring each resonator at a power that produces an internal electric field large enough to saturate all TLSs, effectively “turning off” the Q_TLS contribution to total Q_i. We can then subtract the aggregate loss contribution from these power-independent mechanisms to determine Q_TLS from Q_LP

The blue points and lines in Fig. 2(b) show the Q_TLS values determined from the Q_LP values (green points and lines) vs. trench depth when this correction is performed independently for each device in the set that generates each mean Q_i value. This set of values exhibits the expected monotonic improvement in Q_i as interface participation ratios decrease with increasing trench depths. The need for this correction results from the fact that although the devices were limited by TLS losses at low excitation power, these losses were low enough to be comparable to losses associated with background, power-dependent mechanisms. Separating out the contribution from these high-power mechanisms allows us to probe TLS losses in high Q_i devices despite this variability. See supplementary material for further data and analysis of this process. The error bars represent 95% confidence intervals resulting from measuring 10–15 nominally identical devices for each depth.

In order to develop a quantitative model of interface losses in our devices, we additionally characterized a series of resonator geometries ranging from (w, g) = (3 μm, 1.5 μm) to (w, g) = (22 μm, 11 μm) for trench depths between 0.15 μm and 2.2 μm. Each geometry in this dataset provides a linear equation of the form of Eq. (1) relating device Q_TLS to loss factors associated with each dielectric region. While a single relationship is insufficient to determine each region's losses, multiple geometries with varying combinations of participation ratios form a set of linear equations that can in principle be used to determine each individual loss factor. However, in general, this matrix of participation ratios is very nearly singular for a wide range of planar geometries. This collinearity is readily apparent in the approximate proportionality of the MS and SA interface participation ratios at all depths shown in Fig. 3. As a result, errors associated with the input Q_TLS values and modeling inaccuracy prevent the determination of a unique solution to the system of equations.³⁰ Nevertheless, we can perform a Monte Carlo analysis of the constrained least square optimization solution using our measured Q_TLS values and error bars in order to determine a corresponding distribution of loss factors for the dielectric regions. For comparisons to previously reported loss tangents, see supplementary material. A comparison between the measured Q_TLS and Q_TLS values predicted by this model is shown in Fig. 2(c) with the corresponding error bars for the 19 device geometries that we measured. The dashed green line represents the values where the measured and predicted Q_TLS correspond exactly. The qualitative agreement between the measured and predicted Q_TLS indicates that the range of dielectric losses encompassing this model accurately describes our devices. Furthermore, this indicates that this model can also be used to determine predictive bounds for resonator Q_TLS for devices with similar sets of participation ratios (i.e., planar devices with anisotropic trenching). The region of 95% confidence in this prediction is shown in Fig. 2(b) for (w, g) = (16 μm, 8 μm) devices (pink shaded region) over the range of trench depths we studied. The predicted Q_TLS values agree well with the measured trend, indicating that the interface losses are likely uniform between resonators with different trench depths.

To determine the extent to which Q_TLS can be improved with the increasing trench depth, we simulate the interface participation ratios for depths comparable to those achievable through deep silicon etching²³ for multiple geometries and assuming perpendicular sidewall angles (⁠$Φ$ = 90°). Figures 3(a) and 3(b) show MS (red), SA (blue), MA (purple), and Si (green) participation ratios for two representative coplanar resonator geometries (w, g) = (6 μm, 3 μm) and (16 μm, 8 μm) as a function of trench depth from d = 0.15 μm to d = 80 μm. The interface participation decreases with the trench depth, and it asymptotes beyond a depth that is dependent on the CPW gap. The blue dashed line indicates the depth at which the total bulk and interface participation reaches within 1% of the asymptotic value. In general, we observe that trenching beyond a depth of approximately d = 10g ceases to further reduce the participation ratios in the device interfaces or the silicon substrate. This asymptotic behavior can be contrasted with the logarithmic dependence at 1–10 μm depths simulated in Ref. 10.

In summary, we have demonstrated trenched TiN resonators with a mean Q_i of 2.2 million. Characterization of sets of devices with a range of CPW dimensions and trench depths has enabled us to produce a model of dielectric losses that quantitatively agrees with our measured Q_i values and can be used to predict device performance within the bounds set by the model uncertainty. Furthermore, we have used this form of participation ratio-based device modeling to predict the extent to which deep trenching can improve dielectric losses in superconducting CPW resonators. Altogether, these results indicate that trenching significantly reduces aggregate interface dielectric losses in superconducting CPW resonators and that significant further improvements in total Q_i are possible by mitigating loss contributions from non-TLS related sources. Additionally, it may be possible to combine the analysis method we use to model dielectric losses in our system with more drastic geometry changes in order to more accurately determine interface losses as a tool for process qualification and device improvement. Both approaches would provide essential information for reducing dielectric losses in superconducting quantum devices.

See supplementary material for the details of fabrication methods, experimental hardware, power-independent loss subtraction, and participation ratio-based loss calculations and analysis.

We gratefully acknowledge M. Augeri, J. Birenbaum, P. Baldo, M. Cook, G. Fitch, E. Golden, V. Iaia, K. Magoon, P. Murphy, B. Osadchy, A. Sears, R. Slattery, C. Thoummaraj, and D. Volfson at MIT Lincoln Laboratory for technical assistance. This material is based upon the work supported by the Department of Defense under Air Force Contract Nos. FA8721-05-C-0002 and/or FA8702-15-D-0001. Any opinions, findings, conclusions, or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of the Department of Defense.