Josephson junctions form the essential non-linearity for almost all superconducting qubits. The junction is formed when two superconducting electrodes come within ∼1 nm of each other. Although the capacitance of these electrodes is a small fraction of the total qubit capacitance, the nearby electric fields are more concentrated in dielectric surfaces and can contribute substantially to the total dissipation. We have developed a technique to experimentally investigate the effect of these electrodes on the quality of superconducting devices. We use λ/4 coplanar waveguide resonators to emulate lumped qubit capacitors. We add a variable number of these electrodes to the capacitive end of these resonators and measure how the additional loss scales with the number of electrodes. We then reduce this loss with fabrication techniques that limit the amount of lossy dielectrics. We then use these techniques for the fabrication of Xmon qubits on a silicon substrate to improve their energy relaxation times by a factor of 5.
Josephson junction (JJ) based superconducting qubits are a promising platform for quantum information processing.1–4 Based on current performances, a powerful and error protected processor will require millions of physical qubits.4 This number depends strongly on the error rates of individual physical qubits. The ratio of gate operation time to qubit energy relaxation time (T1) sets a limit on the operation's fidelity. A dominant source of decoherence in superconducting devices is stray coupling to two level states (TLSs) in amorphous dielectrics.5–8 Strong coupling to TLS defects near their resonant frequency also create “holes” in tunable qubit spectra which restrict the frequencies available for control operations.9 Nanofabrication techniques such as photolithography, thin film deposition, and etching tend to leave 1–10 nm thick interfacial dielectric films with loss tangents on the order of , which are difficult to remove.10 Large strides have been made to reduce the energy loss to these surface dielectrics, leading to greatly enhanced T1's in planar and three dimensional superconducting resonators.7,11 While qubit T1's have also improved, they still lag behind those of resonators and appear to be limited by other loss channels.
A key difference between resonators and qubit circuits is the inclusion of JJs. Transmon qubits, in particular, have two main circuit elements: a linear capacitor and a non-linear inductive element typically constructed from one or more Al/AlOx/Al JJs. To create capacitors of the highest quality, planar capacitor fabrication can be separated from JJ fabrication and defined identically to planar resonators with critical dimensions of tens of microns.1,9,12,13 Sub-micron JJs are then shadow evaporated and electrically shorted to the capacitor in a lift-off process. This processing is known to leave behind lossy dielectrics at the surrounding interfaces.10 Furthermore, electrodes that connect to JJs come within close proximity of each other, concentrating electric fields in nearby interfaces and increasing loss.14 Thus, a large amount of loss can come from a relatively small amount of the lossy material.
To quantify the additional loss associated with JJ electrodes, we mimic the fabrication of JJs connected to high quality coplanar waveguide (CPW) resonators. We add small capacitive “lift-off sites”' to the open end of CPW resonators where there is an electric field anti-node. These lift-off sites emulate the electrodes, leading to but not including the pair of JJs in the superconducting quantum interference device (SQUID) at the base of Xmon transmon qubits [Figs. 1(c) and 1(d)]. We measure how loss scales with multiple lift-off sites, effectively amplifying the loss over the background loss of the resonator. We quantify the loss associated with JJ fabrication and use this knowledge to guide improvements in the fabrication leading directly into improvements in Xmon T1's. The most dramatic improvements occur in Xmons fabricated on silicon substrates, where we see an increase in T1 by a factor of 5.
We fabricate these resonators with aluminum base wiring on high resistivity (>10 k cm) intrinsic (100) plane silicon substrates. Prior to loading for deposition, we sonicate bare wafers in acetone and then isopropanol and rinse with deionized (DI) water. We then dip the wafers in a heated piranha solution, followed by DI water, and then buffered HF to remove the native oxide. Immediately after blow drying with nitrogen, we load the wafers into a high vacuum electron beam deposition tool and deposit 100 nm of aluminum. We pattern the coplanar wave guide (CPW) resonators, microwave feedline, and launch pads by optical lithography. We develop the resist in an AZ 300 MIF (2% TMAH in water) developer. We take the advantage of the fact that the developer attacks aluminum to wet etch the pattern in the same step as development.
Next, we use electron beam lithography (EBL) to pattern electrodes which mimic JJs'. First, we optically pattern lift-off gold alignment marks; then, we pattern and develop the JJ electrode sites using EBL.9 We then load the wafer back into the same high vacuum deposition tool used for base aluminum. We use an in-situ 400 V, 0.8 mA/cm2 argon ion mill to etch away the native AlOx to make the DC contact between the etched base wire metal and the lift-off metal.9,10,15 We immediately deposit aluminum at normal incidence leaving a ∼300 nm gap between ground and signal electrodes which mimic the JJ wiring excluding the JJ itself. It is important to note that we do not make the DC electrical contact between the resonator's center trace and the ground plane. This gap and the ion mill redeposited residue are displayed using a scanning electron microscopy (SEM) image in Fig. 1(e). A more complete description of fabrication procedures is given in the supplementary material.
An example of a resonator structure is shown in Fig. 1(a). This resonator is one of ten CPW resonators per chip, each capacitively coupled in parallel to a common feed-line. All resonators are designed with center trace width of m, gap to the ground plane (g) on either side g = w, and resonant frequencies (f0) between 5.5 and 6.0 GHz. We fabricate CPW resonators between zero and seven lift-off sites at the voltage anti-node to test the scaling of the additional loss with number of lift-off sites [Fig. 1(b)]. The additional lift-off site structures [Figs. 1(b)–1(d)] modify the circuit parameters slightly by adding a parallel capacitance to the open end, but this effect is small (∼1% of the total resonator capacitance added per lift-off site; this is described in the supplementary material). We cool these resonators using a heavily filtered16 adiabatic demagnetization refrigerator with a base temperature of 50 mK and extract their internal quality factor, by measuring and fitting the resonators' scattering parameters versus frequency.7,17 In Fig. 2, we plot this measured Qi as a function of average photon occupation in the resonator. The low power plateau (around a single average photon occupation) approximates the loss experienced by qubits which also operate at a single photon.
The low power Qi's of the bare resonators (with no lift-off sites) are within the device-to-device variation of bare resonators fabricated separately (between 2 and 3 million). These witnesses indicate that the fabrication process itself has little effect on the quality of bare resonators that are buried by resist during the lift-off process. Additional base wire “hooks” are used to connect lift-off to base wire aluminum [Fig. 1(c)]. Resonators modified to include these hooks (without performing lift-off) have Qi near the device-to-device variation of the bare resonators as well, indicating little to no added loss from modifying the base wire in this way. However, when lift-off metal is added, the asymptotic value of Qi at low photon occupation scales inversely with the number of lift-off sites, and the additional low power loss () per site is 7.9 . This increase in loss with the number of JJ electrodes indicates that qubits designed with SQUIDs will be twice as sensitive as those designed with single JJs.
The additional loss per lift-off site limits (the total internal quality of the resonator), which is given by
where is the background loss from other sources, pj (the participation) is the ratio of electric field energy stored in the jth volume to the total capacitive energy, and is the dielectric loss of the jth volume. The volume of dielectric between the electrodes is small due to their close proximity, and this small volume may not always contain TLSs sufficiently near resonance to contribute loss.5 In Fig. 2, we see evidence of this effect that when only a single pair of JJ electrodes is added, the extracted single photon Qi varies by over a factor of two between resonators at slightly different frequencies. Adding more sites scales the field energy stored near these electrodes, and thus, loss due to these interfaces approaches a “loss tangent regime” where Eq. (1) is valid. With enough lift-off sites, the total loss of the resonator is dominated by this added loss and will be less dependent on individual TLS fluctuators.
Previous work has shown that aggressive milling of the substrate leads to amorphization and thus added loss at the substrate-metal (SM) and nearby substrate-vacuum (SV) interfaces on sapphire substrates.10 Using similar experiments on a silicon substrate, we found this aggressive ion milled lift-off leaves a roughly 3.9 nm thick interfacial layer underneath the metal. Using cross-sectional finite-element simulations assuming a relative permittivity for this layer, we extract an intrinsic TLS loss tangent .
To avoid creating this lossy interfacial layer while still making DC contact to the base wiring, we break the electrode deposition into two distinct steps: “wiring” and “bandage.” In the wiring step, we use EBL to define the same JJ electrodes as before, but without any in-situ argon mill. We use a downstream oxygen asher to descum the developed resist prior to loading the wafer for deposition. It has been shown that with no in-situ cleaning, a de-scum prior to loading can be used to remove any left-over contamination from the development process18,19 and reduce loss at interfaces.10 After aluminum deposition, we lift-off the resist and unwanted metal in solvents. Second, we use the bandage step to make galvanic contact between the newly deposited lift-off metal and the base wiring. We perform a second round of EBL lift-off, but only expose both metal surfaces (base wiring and JJ electrode). We aggressively ion mill (as detailed earlier) prior to the bandage deposition. The substrate is protected by resist, and the new bandage metal electrically shorts the JJ electrodes to the base wiring [Figs. 3(c) and 3(d)]. The lithography for the bandage metal can also be done optically, and this process has been implemented during the JJ fabrication for Xmon, gmon,20 and fluxmon6 qubits.
To test the improvement in quality from the bandage process, we fabricate resonators with 4 lift-off sites and measure the resulting Qi's [Figs. 4(c) and 4(d)]. The low power Qi's are raised back up to around (a factor of around 5 improvement from the lift-off damaged sites). A typical Xmon capacitor geometry is shown in Fig. 4(a). In Fig. 4(b), we plot Qi corresponding to T1 measurements of qubits that underwent both styles of fabrication (we plot original T1 data in the supplementary material). The average Qi for these qubits is the representative of qubits after these processes. The total capacitances of Xmons and the resonators indicate that resonators with 4 lift-off sites have similar lift-off site participation as qubits, and the magnitude of improvement is consistent with the average of low power internal quality factor measurements of these resonators [Fig. 4(c)].
Although the bandage process improves Qi greatly, there still appears to be residual loss caused by the JJ electrodes limiting Qi below that of the bare resonators, indicating further improvements are possible. There are also sections of the bandaged qubit spectrum where the Qi drops far below its average value. These holes occur as the qubits transition frequency (f10) is tuned through the resonance of a particularly strongly coupled TLS.9 The tunability of the qubit allows for probing loss as a function of frequency while each resonator only probes at a single frequency.
In summary, we modified resonators to use them as a tool to directly measure the added capacitive loss from JJ electrodes necessary for most superconducting qubits. We used this tool to measure different JJ electrode fabrication techniques and found that aggressive ion milling of silicon substrates adds substantial loss. We developed an improved process where we protect the substrate from aggressive ion milling without altering the high coherence capacitor fabrication. We fabricated qubits using this process and measured the average Qi increase by a factor of 5.
See supplementary material for further scaling analysis of loss with the number of liftoff sites, the T1 data for the qubits displayed, the full center-trace liftoff resonator data, the finite element simulation data, calculations comparing participations of the JJ electrodes on qubits and resonators, fabrication details, and a description of how we extract Qi and the average number of photons for the displayed resonator data.
This work was supported by Google. C.Q. and Z.C. acknowledge support from the National Science Foundation Graduate Research Fellowship under Grant No. DGE-1144085. Devices were made at the UC Santa Barbara Nanofabrication Facility, a part of the NSF funded National Nanotechnology Infrastructure Network.