Strained GaN quantum-well FETs on single crystal bulk AlN substrates

The state-of-art gallium nitride based electronic devices have demonstrated excellent performance in high-frequency and high-power applications.^1–5 These devices are on thick GaN buffer layers, most of which are on SiC substrates for efficient thermal dissipation. The heteroepitaxially grown GaN layers inherently incorporate high density of dislocations (typically $∼109$/cm²), which give rise to reliability issues and degrade breakdown characteristics. In this paper, we show that thin strained GaN quantum well (QW) double heterostructures on bulk AlN substrates offer an attractive alternative approach for high-performance nitride electronics.

To meet the scaling requirements for high-speed high-power RF applications, tight electrostatic control and quantum confinement of charge carriers are highly desired. The wide direct band gap of AlN (∼6.2 eV) and its large band offset with GaN offers the maximal vertical confinement of carriers in nitride channels. The large polarization charge of AlN induces high density two-dimensional electron gases (2DEG) in the quantum well, which is desired for high current drive and lateral scaling of gate lengths. The thermal conductivity of AlN, estimated⁶ to be as high as ∼340 W/m · K, can be comparable⁷ to that of SiC ∼370 W/m · K and offers the potential benefit of reducing thermal boundary resistance. Thus, AlN simultaneously satisfies the conflicting requirements of high thermal conductivity and high electrical resistivity for high-power microwave electronics. Importantly, the low dislocation density (⁠$∼104$/cm²) of single-crystal bulk AlN substrates has the potential for defect-free channels and barriers in principle, which is a promising prospective for improving thermal robustness, reliability, breakdown, and noise characteristics of these devices.⁸ The presence of a very thin GaN quantum well active region embedded in the AlN/GaN/AlN double heterostructure also enables selective optical-marker based Raman metrology of strain⁹ present in the active layers.

We recently reported the transport properties and device performance of AlN/GaN/AlN heterostructures, but all those studies were performed on AlN templates on sapphire.^10,11 In those works, a number of unconventional design paradigms enabled by these heterostructures were outlined. In this paper, we demonstrate the binary heterostructures on single crystal bulk AlN substrates. The DC and RF performances of the FETs on bulk AlN are improved from the counterparts on sapphire.

A schematic cross-section of the device structure is shown in Fig. 1(a). The AlN/GaN/AlN heterostructures were grown by RF plasma molecular beam epitaxy (MBE) on ∼400 μm-thick semi-insulating aluminum-polar bulk AlN substrates. Fig. 1(b) shows the bulk AlN crystal. A 380-nm-thick unintentionally doped (UID) AlN buffer was epitaxially grown, followed by a 28 nm GaN quantum well where the 2DEG channel is located. Then, a 6-nm-thick AlN layer was grown on the GaN quantum well as the top barrier and capped with a 1.5-nm-thick GaN layer to protect the AlN surface from oxidation. The Hall effect measurements at room temperature showed a 2DEG density of $ns∼2.8×1013$/cm², a room-temperature electron mobility of $μ∼260$ cm²/V · s, and a corresponding sheet resistance of $Rsh∼835 Ω/◻$⁠, with the indications of defect generation during nucleation. This sample was used for subsequent HEMT fabrication.

The mobility in such heterostructures can be significantly improved with modified nucleation conditions. For example, in a separate 3 nm AlN/ 21 nm GaN/ AlN quantum well heterostructure grown on the same bulk AlN substrate with different nucleation conditions, a 2DEG mobility of 601/1380 cm²/V · s, a sheet charge density of $3.2/2.6×1013$/cm², and a sheet resistance of $327/171 Ω/◻$ at 300/77 K were observed. These are the highest measured mobility and lowest sheet resistance for the AlN/GaN/AlN strained quantum well heterostructures on the AlN platform till date. However, the HEMT fabrication process on this lower sheet resistance sample was not successful because of lithographic misalignment in the processing of this particular sample coupled with the limited supply of bulk AlN substrates. At this stage, we do not completely understand the precise correlation between the nucleation conditions and the 2DEG transport properties. Several mechanisms could be limiting the Hall-effect mobilities in the strained QW channels, such as rough heterointerfaces, Stark-effect scattering,¹² and hole-drag due to a co-existence of a two-dimensional hole gas (2DHG) channel at the bottom GaN/AlN interface.¹⁰ A comprehensive study of transport is ongoing and should help identify the cause of the lower measured electron mobilities in such heterostructures compared to 2DEGs on GaN substrates.

An MBE regrowth process was employed to form the n+ GaN ohmic contacts to the 2DEG channel using a technique similar to what we have reported earlier.^13–15 A ∼200-nm-thick SiO₂ mask was deposited on the nitride heterostructures using plasma-enhanced chemical vapor deposition (PECVD) and then patterned by reactive ion etching (RIE). The nitride regrowth regions were etched for ∼40 nm using low-damage BCl₃/Cl₂ inductively coupled plasma reactive ion etching (ICP-RIE). MBE regrowth of ∼100-nm-thick heavily Si-doped (⁠$ND∼1020$/cm³) n+ GaN was then performed. The polycrystalline GaN deposited on the SiO₂ mask was lifted off selectively. Nonalloyed ohmic contacts were formed by E-beam evaporation of 20/100 nm Ti/Au stacks. Optical lithography was used to pattern and deposit 50/100 nm Ni/Au gates for long channel devices directly on the GaN cap layer, as indicated in Fig. 2(a), as well as on top of the Ti/Au layers as contacts. Before fabricating short gate length transistors, a 5 nm Al₂O₃ layer was deposited by atomic layer deposition (ALD) on the entire sample. The Ni/Au (15/50 nm) gate stacks were defined by electron-beam lithography (EBL) and lift-off for short gate length devices on top of the ALD oxide, as indicated in Fig. 1(a). A scanning electron microscope (SEM) image of a finished device is shown in Fig. 1(c). The whole processed sample on the bulk AlN wafer is also shown in Fig. 1(b). Unlike sapphire, the bulk AlN crystal is not completely transparent due to the presence of point defects.

The processed HEMT structure allowed the mapping of strain in the GaN quantum well channel using the optical marker technique.⁹ Fig. 2(a) indicates the locations where the Raman spectra shown in Fig. 2(b) were measured. Fig. 2(c) shows the source-side cross section of the processed device with a zoomed in image of the strained GaN quantum well under the gate. Because the regrown GaN regions are significantly thicker than the quantum well channel region, the difference in strain should be detectable in the Raman spectroscopy. The measured $E2H$ Raman peaks in the two regions shown in Fig. 2(b) reveal the difference in the biaxial strain between these regions. The GaN quantum well region shows the expected peak at $E2H(QW)=596.9$ cm⁻¹, indicating that the quantum well GaN is compressively strained. The peak frequency and the FWHM of the Raman peaks are similar to the epitaxial heterostructure before the FET device fabrication, indicating the FET device processing preserved the crystal quality in the thin GaN quantum well channel. The thicker n+ GaN regrown region shows a peak at $E2H$ (n+ GaN) = 568.9 cm⁻¹, which is close to the bulk GaN peak of $E2H$ (Bulk GaN) = 567.4 cm⁻¹. The small residual compressive strain (<0.2%) and high relaxation in the n+ regrown GaN regions are expected because the thickness of 100 nm is large enough to relax the lattice mismatch almost completely in the heterostructure.

After the fabrication of the field-effect transistor, a 2DEG density of $ns∼3.4×1013$/cm², an electron mobility of $μ∼180$ cm²/V · s, and a sheet resistance of $Rsh∼1020 Ω/◻$ were extracted by the Hall effect measurement at room temperature. The slight degradation from the as-grown sample may be due to the modification of surface states by the ALD Al₂O₃ layer. A contact resistance of 0.13 $Ω·$ mm and a sheet resistance of 1100 $Ω/◻$ were measured by an independent transmission-line method (TLM); the TLM sheet resistance was in good agreement with the value obtained from the Hall effect measurement.

The measured DC common-source output characteristic current-voltage I–V's of (a) a long channel FET and (b) a short channel AlN/GaN/AlN FET are shown in Fig. 3. The device dimensions are: (a) $Wg/Lg=50/1μ$m, $Lgs/Lsd=1.5/5μ$m and (b) $Wg/Lg=2×50μ$m/65 nm, $Lgs/Lsd=170/850$ nm. At V_gs = +1 V and V_ds = 12 V, the maximum drain current density for the short channel FETs reaches $Idmax∼2.0$ A/mm, which is ∼3 times higher than the 0.6 A/mm measured for the long channel FETs. As shown in Figure 4, a 80-nm-long gate device exhibited drain current density of 2.8 A/mm at V_gs = +3 V and V_ds = 12 V. This higher current than the 65 nm gate length device is due to a shorter gate-source spacing leading to lower source access resistance. Because this device had a half-gate, it did not allow RF measurement of speed and is therefore not discussed further. Thus, the reduction of the device dimensions is seen to dramatically boost the current drive despite the high sheet resistance.

The current drive exceeding 2 A/mm is comparable to the state-of-the-art GaN HEMTs on various other substrate platforms.^1–5 It is a significant improvement from the ∼1.4 A/mm of the similar AlN/GaN/AlN FETs that were demonstrated earlier on an AlN-on-sapphire platform.¹⁰ The on-resistance R_on was extracted to be ∼8.4 $Ω·$ mm and ∼1.8 $Ω·$ mm at V_gs = +1 V for long and short channel FETs, respectively. For the 65-nm-long gate devices, a high output conductance was observed for the 28-nm-thick GaN QW channel due to the short-channel effects. With thinner GaN quantum wells and thinner gate barrier stacks, such short channel effects can be suppressed in the future by the presence of the AlN back barrier.

The on/off transfer characteristics of the long and short channel FETs are shown in Fig. 3(c) in a semi-log scale. The gate leakage current in the long-channel FET indicates that the MBE growth is not optimal yet, and defects have been generated in the epitaxial process. The ALD Al₂O₃ gate dielectric cuts down the leakage, improving the on/off ratio to three orders of magnitude for the short channel devices.

The linear plot of the transistor gain (transconductance) and the transfer characteristics of the 65-nm-long gate device are shown in Fig. 5(a) as a function of the gate voltage. The peak extrinsic transconductance reached is $gmmax∼250$ mS/mm at $Vgs=−6.8$ V and V_ds = 8 V, corresponding to an intrinsic transconductance of 270 mS/mm for a source access resistance $Rs∼$ 0.3 $Ω·$ mm. The threshold voltage V_th = −9.1 V at V_ds = 8 V was obtained by a linear extrapolation of the drain current at the peak transconductance. The negative threshold voltage is close to what is expected for the high 2DEG density (⁠$3.4×1013$/cm²) and the gate capacitance.

The device performance under large-signal drive was investigated by pulsed I–V measurements, as shown in Fig. 5(b). Using a 500-ns pulse width and a 0.5-ms period, the drain current density I_d at V_gs = 0 V cold pulsed from (V_gs, V_ds) = (0 V, 0 V) is observed to be higher than what is measured without pulsing at DC. The drain current drive pulsed from (–10 V, 0 V) and (–10 V, 10 V) showed an ∼18% gate lag and an ∼16% drain lag on the unpassivated devices. The current saturation is not observed in pulsed I–V measurements due to the short channel effects. To improve the large signal performance and enhance environmental robustness, the passivation of surface states is necessary in the future devices.^16,17

The on-wafer device RF measurements were taken using an HP 8510C vector network analyzer in the frequency range from 0.25 to 30 GHz. Fig. 5(c) shows the current gain $|h21|2$ and the unilateral gain $U$ as a function of the frequency for devices biased at peak f_T conditions (V_gs = −7.8 V, V_ds = 8.0 V). A unity current-gain cutoff frequency f_T = 120 GHz was extracted by the extrapolation of $|h21|2$ following the 20-dB/decade slope. Improving the mobility from the current value of ∼180 cm²/V · s will reduce the channel charging delay and enable a higher f_T.¹⁸ An $fT·Lg$ product of 7.8 GHz $·μ$m was obtained, with for a gate-length-to-barrier-thickness aspect ratio of 5.2. For similar AlN/GaN/AlN FETs without a gate dielectric on AlN template on sapphire,¹⁰ the $fT·Lg$ product is 10.4 GHz $·μ$ m with the aspect ratio of 13.3. Due to resistive rectangular gates, the measured low $fmax∼24$ GHz can be enhanced with T-gates¹⁹ in the future embodiments of the device.

In conclusion, this work reports the DC and RF performances of AlN/GaN/AlN quantum well FETs on bulk AlN substrates with regrown ohmic contacts for the first time. By performing Raman spectroscopy with the AlN/GaN/AlN quantum wells as an optical marker, we demonstrate the direct measurement of significant lateral strain variations between the GaN QW channel region and the regrown GaN region in the fabricated FET devices. With a 2DEG density of $3.4×1013$/cm², the devices pinched off and a record high drain current exceeding 2 A/mm was achieved. Despite the low electron mobility, the 65-nm-long gate devices show an $fT∼120$ GHz. As the homoepitaxial material quality improves, boosts in the electron mobility to the level in conventional GaN HEMTs (i.e., ∼1500 cm²/V · s) is possible, which will result in a major boost in the performance of FETs on bulk AlN. The HEMT performance stands to benefit tremendously from the high thermal conductivity of the AlN substrate and by improved lateral and vertical scaling afforded by the AlN substrate platform. By using thicker large bandgap AlN barrier layers and AlGaN channels, FETs on bulk AlN can significantly improve the breakdown characteristics and thermal handling over the existing state-of-the-art and can present a compelling case for high power applications.

This work was supported in part by the Office of Naval Research THz MURI project supported by Dr. Paul Maki and by the Designing Materials to Revolutionize and Engineer Our Future (DMREF) Program under Award No. 1534303, funded by the National Science Foundation.