Chemical vapor deposition of monolayer MoS₂ directly on ultrathin Al₂O₃ for low-power electronics

Recently, two-dimensional (2D) semiconducting materials have attracted significant interest for high-performance electronic applications.^1,2 Among the 2D transition metal dichalcogenides (TMDs), MoS₂^3,4 has been specifically identified as a promising candidate for low-power devices.^5–8 MoS₂ field-effect transistors (FETs) exhibit high room-temperature field-effect mobilities (30–480 cm²/Vs),^9–13 high current on/off ratios (10⁸–10⁹),^14,15 and low sub-threshold swings (SS) (∼70 mV/decade).⁸ Moreover, the realization of large-area synthesis of monolayer MoS₂ via chemical vapor deposition (CVD)^16–18 and metal-organic CVD (MOCVD)¹³ provides a pathway to wafer-scale TMD-based circuitry.

The synthesis and processing of new materials for low-power electronics is guided by key transistor figures of merit such as threshold voltage V_TH, sub-threshold swing SS, and current I_ON/I_OFF ratio.^1,6,19 For modern complementary metal-oxide-semiconductor (CMOS) digital electronics, low power consumption is enabled by enhancement-mode devices that have minimal off-current at zero gate bias (i.e., I_OFF is defined as the current at gate voltage V_G = 0 V).^1,20 The CMOS I_ON/I_OFF ratio is a relevant low-power electronics metric that evaluates device performance while taking into account the standby power consumption. The optimization of CMOS performance metrics is achieved by integrating appropriately doped semiconducting materials with high-κ ultrathin dielectrics. However, this integration remains a challenge for low-dimensional semiconducting TMDs. Thus far, most MoS₂ FETs have been integrated with ultrathin high-κ materials as a top-gate dielectric,^21–24 or by transferring MoS₂ onto dielectric substrates.^8,25 MOCVD growth of MoS₂ on Al₂O₃ and HfO₂ has also been achieved, but this approach requires a large thermal budget with over 20 h of high temperature processing.¹³ Recently, Kim et al. demonstrated MoS₂/high-κ dielectric FETs by transferring micromechanically exfoliated MoS₂ onto 50 nm thick Al₂O₃ grown by atomic layer deposition (ALD), resulting in mobilities >30 cm²/Vs, I_ON/I_OFF ratios >10³, and sub-threshold swings of ∼70 mV/decade.⁸ However, micromechanical exfoliation of MoS₂ is not suited for large-area processing.

Overall, current methods of depositing high-κ materials as a top-gate dielectric on MoS₂ or transferring CVD MoS₂ onto dielectric substrates suffer from several limitations including lack of control over MoS₂ doping, loss of MoS₂ structural integrity, and contamination from transfer residues. For example, the growth of high-κ dielectrics on top of MoS₂ strongly increases electron doping and induces large negative shifts in V_TH, which significantly increase CMOS power consumption.^22,26,27 Meanwhile, transfer processes lead to not only structural defects and wrinkles in MoS₂ but also uncontrolled doping from processing residues.^9,28,29 Thus, while the integration of MoS₂ with high-κ dielectrics has been undertaken in previous work,^30,31 a scalable transfer-free pathway for doping-controlled enhancement-mode devices remains challenging for CVD-grown MoS₂/high-κ dielectric heterostructures.

In this letter, we overcome these issues and report the direct CVD growth of monolayer MoS₂ on 20 nm thick ALD-derived Al₂O₃. The resulting MoS₂/Al₂O₃ heterostructures are characterized with a suite of microscopy and spectroscopy techniques including scanning electron microscopy (SEM), atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), photoluminescence (PL) spectroscopy, and Raman spectroscopy. Furthermore, the integrity of the dielectric following CVD growth is verified with X-ray reflectivity (XRR) and capacitance-voltage (C-V) measurements. The high-quality interface between the MoS₂ and Al₂O₃ results in FETs with a CMOS I_ON/I_OFF ratio up to 10⁴, sub-threshold swing as low as 220 mV/decade, and enhancement-mode threshold voltage of ∼2 V. This overall set of device metrics for transfer-free FETs represents a significant improvement over the literature precedent with direct implications for low-power electronics.

The CVD growth of monolayer MoS₂ on ALD Al₂O₃ was achieved by adapting a procedure previously used for CVD growth on SiO₂/Si substrates.³² Specifically, 20 nm of Al₂O₃ was deposited by ALD at 200 °C on Piranha-cleaned Si, after which the Al₂O₃/Si substrate was placed downstream of the MoO₃ and sulfur source boats under an argon gas flow rate of 25 sccm and a pressure of 150 Torr (see supplementary material for details). Figures 1(a) and 1(b) present SEM and optical images, respectively, of the resulting CVD-grown MoS₂ domains. Most of the MoS₂ domains possess lateral edge lengths of ∼1 to 2 μm with some domains showing edge lengths up to 20 μm. An AFM topography image of a single domain (Figure 1(c)) reveals a step height of 0.72 nm, which is consistent with monolayer MoS₂.³³ A Raman spectrum of the CVD-grown MoS₂ (Figure 1(d)) further corroborates the single-layer thickness of the MoS₂. The MoS₂ in-plane (E¹_2g) and out-of-plane (A_1g) vibrational modes were each fit with a Lorentzian function to determine their spectral locations at 384.7 cm⁻¹ and 404.9 cm⁻¹, respectively. A difference of 20.2 cm⁻¹ between these modes is consistent with monolayer CVD MoS₂.^17,34 The room-temperature PL spectrum of the MoS₂ (Figure 1(e)) exhibits a pronounced peak at ∼669 nm and a minor peak at ∼620 nm corresponding to the excitonic A and B direct-gap optical transitions in monolayer MoS₂, respectively.^33,35,36 Lastly, the chemical composition of the MoS₂ is probed using XPS. The molybdenum core level spectrum is presented in Figure 1(f). The position of the Mo 3d_5/2 peak at ∼230 eV is consistent with the Mo⁴⁺ formal oxidation state of MoS₂, whereas the minor doublet at higher binding energy corresponds to MoO_x.^37,38 The relatively weak intensity of the MoO_x peaks suggests minor MoO_x content, as observed in other MoS₂ CVD studies.^32,39,40 More characterization details are provided in the supplementary material.

The effects of the MoS₂ growth conditions on the electronic quality of the 20 nm Al₂O₃ dielectric were investigated via metal-insulator-semiconductor (MIS) capacitance-voltage (C-V) measurements on an Al₂O₃/Si substrate annealed in a temperature cycle identical to that of the MoS₂ growth process (Figure S1(a) of the supplementary material). For these measurements, 200 μm × 200 μm metal contact pads (5 nm Ti/75 nm Au) were patterned over a ∼1 cm² area of the annealed Al₂O₃/Si substrates via shadow masking. In Figure 2(a), a histogram of the capacitance values at V = 4 V (i.e., accumulation regime for the grounded n-type Si substrate) for 121 devices shows a narrow distribution with an average value of 328 nF/cm². The corresponding effective dielectric constant (κ_eff) is calculated to be 8.45 (effective silicon oxide thickness ∼10.5 nm), which is comparable to as-deposited ALD Al₂O₃.⁴¹ κ_eff was calculated using the Al₂O₃ thickness measured by XRR (21 nm) (see supplementary material) and a 1.8 nm thick native silicon oxide.⁴² Capacitance measurements on an unannealed control substrate of Al₂O₃/Si (Figure S3 of the supplementary material) showed an average capacitance of 332 nF/cm², indicating that the thermal cycling did not significantly affect the dielectric quality (<2% reduction in capacitance). The maximum leakage current density between V = −4 and 4 V was less than 10⁻⁶ A/cm² for >55% of the MIS capacitors on the annealed substrate (Figure S4 of the supplementary material).

The integrity of the Al₂O₃ and Al₂O₃/Si interface was further characterized using XRR (see supplementary material). Previously, XRR has been employed to probe the robustness and thickness of heterogeneous ultrathin dielectric stacks following chemical treatments.^42,43 The depth-dependent electron density profile was extracted by fitting the XRR data with the parameters in Table S1 (supplementary material). Figure 2(b) shows the XRR data collected from a sample of MoS₂ directly grown on Al₂O₃/Si and the corresponding model fit, while the inset shows the depth-dependent electron density profile normalized to the electron density of the Si substrate. From this analysis, the thickness of the Al₂O₃ layer after MoS₂ deposition is found to be 20.0 ± 0.3 nm with the addition of a 1.83 ± 0.08 nm Al₂O₃/Si interfacial layer included to achieve the best fit. The presence of similar interfacial layers has previously been reported in annealed Al₂O₃ systems.^44,45 A control sample of as-deposited ALD Al₂O₃/Si without MoS₂ showed a dielectric thickness of 20.7 ± 0.1 nm (Figure S2(b) of the supplementary material), which agrees well with the sample that underwent MoS₂ growth.

To investigate electronic transport properties, field-effect transistors (FETs) were fabricated on CVD MoS₂ grown on 20 nm ALD Al₂O₃, with the Al₂O₃ serving as the back-gate dielectric (schematic shown in Figure 3(a)). Both two-probe FETs and four-probe van der Pauw devices were studied to determine the effect of contacts on the transport characteristics. The devices were patterned with electron-beam lithography, contact metallization (2.5 nm Ti/ 100 nm Au), and liftoff processes outlined previously.³⁹ All devices were measured at 25 °C and <5 × 10⁻⁵Torr. The output characteristics of a typical two-probe MoS₂-FET (Figure 3(b)) are linear in the low bias range, which is consistent with previous studies of MoS₂ contacted with Ti/Au.^14,46 The transfer characteristics of the same device exhibit a CMOS I_ON/I_OFF ratio >10⁴, sub-threshold swing ∼ 220 mV/decade, and V_TH = 2.1 V (Figure 3(c)). The threshold voltage is defined here as the V_G axis intercept of the extrapolation of the linear region of the transfer curve. The transfer curve of a four-probe device is shown in Figure 3(d). The linear field-effect mobility from the devices was calculated according to the following equation:

where V_G and G_D are the gate voltage and channel conductance, respectively. L and W are the channel length and width, respectively, where the dimensions are defined by the area enclosed by the inner electrodes 2 and 3 for the four-probe devices (inset of Figure (3(d)). C_ox is the area-normalized capacitance of the gate-dielectric (328 nF/cm²). Measurements on two-probe and four-probe devices revealed comparable field-effect mobilities, indicating that the contact resistance does not dominate the overall transistor characteristics. The field-effect mobility of all six measured devices is found to vary from 0.4 to 4.1 cm²/Vs (extracted at V_D ≤ 1 V), in agreement with previous reports for CVD MoS₂ mobility.^39,47,48 The devices also show low hysteresis in comparison to other reports on 2D MoS₂^39,49–51 (see Figure 3(c)) where the sweep direction dependent shift in V_TH is ∼10 mV.

We now consider the specific transistor metrics relevant to low-power digital electronics applications. Figure 4 shows the simultaneous improvement in the CMOS I_ON/I_OFF ratio, sub-threshold swing, and V_TH of the FETs in this work in comparison with the previous literature for directly grown CVD MoS₂ FETs.^{13,15,16,22,28,36,39,47,50,52–68} Unless explicitly reported in the literature, the metrics were extracted from published data using a figure digitizer. The majority of the recent reports of transfer-free CVD MoS₂ FETs were included in this analysis, excluding electrochemically gated devices. In particular, we highlight the CMOS I_ON/I_OFF ratio, where I_ON is the device current at the maximum positive gate voltage reported and I_OFF is the device current at V_G = 0 V. For our devices, the maximum positive gate voltage ranges from 3 V to 4 V (n = 6.2–8.2 × 10¹²cm⁻²), and the resulting CMOS I_ON/I_OFF ratio ranges from 10² to 10⁴, which is a significant improvement over previous work on CVD MoS₂. Furthermore, the low sub-threshold swing of our devices from 220 to 530 mV/decade and the low V_TH from 1.3 to 2.7 V also compare favorably with the literature on CVD MoS₂ FETs.

We attribute the favorable low-power performance of the present devices to the direct growth of the MoS₂ on ALD Al₂O₃. The pristine interface between the two materials minimizes the doping variability of transfer methods while maintaining the low-power advantages of ultrathin high-κ dielectrics. The as-grown doping of monolayer MoS₂ on Al₂O₃ results in enhancement-mode FETs with low-operating voltages. As shown in Figure 4(b), the ALD growth of ultrathin metal oxides on CVD MoS₂ has been reported to achieve low operating voltages in top-gated FET geometries. However, this approach increases n-type MoS₂ doping, often resulting in depletion-mode transistors (V_TH < 0 V) unsuitable for low-power CMOS applications. Thus, optimization of power consumption metrics (i.e., CMOS I_ON/I_OFF ratio, threshold voltage, and sub-threshold swing) in this work is highly relevant to logic applications for circuits based on 2D semiconductors.

In conclusion, we have demonstrated the direct growth of monolayer MoS₂ on 20 nm ALD Al₂O₃ using solid precursor CVD. Both AFM and Raman spectroscopy confirm the growth of monolayer MoS₂. Annealing of the 20 nm ALD Al₂O₃ deposited at 200 °C through a CVD temperature cycle of 800 °C decreases capacitance by <2% in comparison to a control sample of as-deposited Al₂O₃/Si. XRR also confirms that the thickness of the dielectric does not significantly change after MoS₂ deposition. The resulting MoS₂ FETs exhibit high performance in low-power CMOS metrics such as a CMOS I_ON/I_OFF ratio of 10²–10⁴, sub-threshold swing= 220–530 mV/decade, and V_TH = 1.3–2.7 V with negligible hysteresis. The low operating voltage enhancement-mode FETs fabricated from the MoS₂ grown on ALD Al₂O₃ demonstrate promise for the low-power n-type branch of CMOS in integrated circuits. The work presented here thus substantiates the prospect of scalable MoS₂/high-κ structures for low-power electronics.

See supplementary material for details on the deposition of the Al₂O₃ dielectric and MoS₂, additional characterization of the Al₂O₃ dielectric, and experimental methods.

This work was performed under financial assistance award 70NANB14H012 from the U.S. Department of Commerce, National Institute of Standards and Technology, as part of the Center for Hierarchical Materials Design (CHiMaD). H.B. acknowledges support from the NSERC Postgraduate Scholarship-Doctoral Program. V.K.S. acknowledges support from the 2-DARE program (NSF EFRI-1433510). J.J.M. acknowledges support from the National Aeronautics and Space Administration (NASA NSTRF grant NNX12AM44H). G.P.C. acknowledges support from the Materials Research Science and Engineering Center (MRSEC) of Northwestern University (NSF DMR-1121262). I.B. and X.L. acknowledge support from the Office of Naval Research (ONR N00014-14-1-0669). The Raman instrumentation was funded by the Argonne−Northwestern Solar Energy Research (ANSER) Energy Frontier Research Center (DOE DE-SC0001059). This work made use of the EPIC and Keck-II facilities of the NUANCE Center at Northwestern University, which has received support from the Soft and Hybrid Nanotechnology Experimental (SHyNE) Resource (NSF NNCI-1542205); the MRSEC program (NSF DMR-1121262) at the Materials Research Center; the International Institute for Nanotechnology (IIN); the Keck Foundation; and the State of Illinois. The XRR measurements were performed at the Northwestern X-ray Diffraction Facility, which is supported by the MRSEC and SHyNE. The authors thank Dr. K.-S. Chen, Dr. J. Wood, Dr. J. Emery, M. Beck, and S. Wells for valuable discussions.