We demonstrate a transfer-free method for producing 3–5 monolayers, large area MoS2 by pre-oxidation of metallic Mo. The growth temperature was reduced, eliminating free sulfur-induced degradation of the SiO2 gate dielectric in strong accumulation, which suppressed the leakage current at VGS=−3 V by a factor of ≥108, when compared to a single step direct sulfidation method. Back-gated field effect transistors with an accumulation electron mobility of  >80 cm2/Vs, an on/off ratio of  >105, and a subthreshold swing of 84 mV/dec from this MoS2 represent the state-of-the-art on SiO2. In accumulation, current saturation was attributed to charge control rather than velocity saturation. The hysteresis-free transistor characteristics were stable up to a temperature of 500 K.

Since the discovery of graphene, there has been an increase in two-dimensional (2D) materials research for its scalability down to atomic dimensions.1,2 Among the analogs of graphene, transition metal dichalcogenides (TMDs) are attractive due to their exceptional electronic and optoelectronic properties.3 MoS2, a TMD, has several advantages over graphene and the industry workhorse, Si,4 including a thickness-dependent bandgap (1.2–1.9 eV).5 Excellent transistor performance has been reported on small area exfoliated samples, underscoring the promise of this material (Table I). The key obstacle in the commercialization of MoS2 technology is low carrier mobility over large areas for top-down devices. Although there were several early reports on synthesis of atomically thin MoS2 with moderate mobility, transferring large area grown films to a substrate of choice leads to interface charges that degrade mobility (Table I). As a result, a vast majority of the recent reports exhibited results obtained from exfoliated MoS2 or transferred films from some other sources.

TABLE I.

Comparison of device parameters with other works on exfoliated and synthetic MoS2.

WorkThicknessMethod of preparationGateDielectricμ (300 K) cm2/V sns (cm−2)SS (mV/dec)On/Off
This work 3–5 ML CVD-Moa BG SiO2 >80 <1013 84 105 
Kim et al.19  20–80 nm Exfoliated BG Al2O3 100 (ND) 1016 cm−3 80 106 
Chen et al.6  ML-12 nm Exfoliated BG BN/SiO2 90–250 1011–1013 … … 
Radisavljevic et al.22  ML Exfoliated TG HfO2 55 … 74 108 
Fiori et al.18  Few-ML Exfoliated BG SiO2 23–26 2–5 × 1012 850 105 
Lin et al.23  ML Exfoliated TG Polymer 150 … ∼ 60 106 
Zhang et al.24  ML CVD-MoO3 BG SiO2 0.23 … … 105 
Zhan et al.25  ML-few ML CVD-Mo BG SiO2 0.04 … … … 
Lie et al.26  ML-few ML CVD-(NH4)2MoS4 BG SiO2 <10 … … 105 
Laskar et al.27  ML-few ML CVD-Mob … … <10 (ND) 3 × 1020 cm−3  … 
Schmidt et al.8  ML CVD-MoO3 BG SiO2 45 7 × 1012 … >106 
Lee et al.9  ML CVD-MoO3a BG SiO2 0.02 … … >103 
Lin et al.28  2–3 ML CVD-MoO3 BG SiO2 0.8 … … 105 
WorkThicknessMethod of preparationGateDielectricμ (300 K) cm2/V sns (cm−2)SS (mV/dec)On/Off
This work 3–5 ML CVD-Moa BG SiO2 >80 <1013 84 105 
Kim et al.19  20–80 nm Exfoliated BG Al2O3 100 (ND) 1016 cm−3 80 106 
Chen et al.6  ML-12 nm Exfoliated BG BN/SiO2 90–250 1011–1013 … … 
Radisavljevic et al.22  ML Exfoliated TG HfO2 55 … 74 108 
Fiori et al.18  Few-ML Exfoliated BG SiO2 23–26 2–5 × 1012 850 105 
Lin et al.23  ML Exfoliated TG Polymer 150 … ∼ 60 106 
Zhang et al.24  ML CVD-MoO3 BG SiO2 0.23 … … 105 
Zhan et al.25  ML-few ML CVD-Mo BG SiO2 0.04 … … … 
Lie et al.26  ML-few ML CVD-(NH4)2MoS4 BG SiO2 <10 … … 105 
Laskar et al.27  ML-few ML CVD-Mob … … <10 (ND) 3 × 1020 cm−3  … 
Schmidt et al.8  ML CVD-MoO3 BG SiO2 45 7 × 1012 … >106 
Lee et al.9  ML CVD-MoO3a BG SiO2 0.02 … … >103 
Lin et al.28  2–3 ML CVD-MoO3 BG SiO2 0.8 … … 105 
a

Does not involve transfer.

b

Does not involve transfer, grown on sapphire.

In this paper, we present a top-down growth technique for synthesizing large area, few atomic layer thick MoS2 transistors. The process oxidizes patterned metallic Mo to form a mixture of volatile Mo-oxides and thins the resulting film down by partial sublimation at a low temperature. Eventually, sulfur vapor is introduced to the system to sulfidize the volatile oxides to MoS2 at relatively low temperature (<500 °C). One advantage of the low growth temperature is to avoid contamination of SiO2 by diffused sulfur atoms, which allows the as-grown films to be used without transferring to different substrates, while maintaining the state-of-the art transistor characteristics on SiO2.

The high quality MoS2 samples were grown on the 50 nm SiO2/n+-Si commercial substrate. A lithographic process was first performed to open up sub-mm sized rectangular windows on a clean SiO2/Si sample, followed by the electron beam evaporation and lift-off of a 7–10 nm thick layer of Mo. This thick layer, if fully sulfidized, would have led to a >20 ML (monolayers) thick MoS2. However, the 7–10 nm was the minimum thickness required to form a continuous film rather than islands on SiO2, necessitating the post-growth thinning described below. The sample was placed on a quartz boat inside the high temperature region of a two-zone horizontal tube furnace. 10 mg of sulfur powder (Fisher Scientific, 99.99% purity) was placed on a quartz plate in the colder region of the process tube.

The tube was pumped down to rough vacuum and purged with ultra-high purity (UHP) N2 before the growth started. The synthesis process was completed in three steps; a pictorial representation of the process flow is provided in Fig. 1(a). The first step was to oxidize the Mo sample at 350–400 °C for 25–30 min in a low O2 flow (∼5 sccm) before sulfidation to form volatile Mo-oxides, and thin down the Mo-containing film by partial sublimation. In step two, the hot zone temperature was raised to 450–500 °C, and the cold zone temperature was elevated to 125–135 °C to allow the melting of sulfur while the O2 flow was gradually tapered off. No carrier gas was flowed during this step for ∼50 min, during which the sulfur vapor reacted with the MoOx and formed MoS2. In the final step, the cold zone temperature was reduced below the melting point of sulfur to quench the sulfidation, while the hot zone temperature was quickly raised to 625 °C for 10 more minutes, with a high flow of dry N2 to improve the crystal quality, to complete the sulfidation reaction, and to remove the residual sulfur vapor from the reactor. Finally, the entire furnace was slowly cooled down to room temperature (–15 °C/min) in the presence of the same N2 flow. The sample was then taken out from the chamber and was annealed in a separate process tube at 1000 °C in N2 ambient for 30 min to improve crystallinity and electronic property, in agreement with others.1,6 Metal contacts, Ti/Au of 20/80 nm thicknesses formed by lift-off, were sintered at 350–400 °C for 60 min in N2 ambient.

FIG. 1.

(a) Temperature, pressure, and gas flow rates during various stages of the growth of MoS2. The Y-axis is not to scale, and the plots are shifted vertically for clear understanding. (b) Raman spectra of oxidized pre-growth Mo samples showing peaks for various oxides of Mo.7 (c) Raman spectra of MoS2 with E12g peak at 383 cm−1 and A1g peak at 406 cm−1; the separation of the peaks is 23 cm−1, which is generally observed in 3–5 ML MoS2.5 All the peaks from MoOx are undetectable after sulfidation, indicating a total conversion of all such oxides. (d) Tapping mode atomic force microscopy image of MoS2 on SiO2 (inset) with a step height of 1.7 nm along the edge of the MoS2 film, corresponding to ∼3 ML, in agreement with the Raman results.

FIG. 1.

(a) Temperature, pressure, and gas flow rates during various stages of the growth of MoS2. The Y-axis is not to scale, and the plots are shifted vertically for clear understanding. (b) Raman spectra of oxidized pre-growth Mo samples showing peaks for various oxides of Mo.7 (c) Raman spectra of MoS2 with E12g peak at 383 cm−1 and A1g peak at 406 cm−1; the separation of the peaks is 23 cm−1, which is generally observed in 3–5 ML MoS2.5 All the peaks from MoOx are undetectable after sulfidation, indicating a total conversion of all such oxides. (d) Tapping mode atomic force microscopy image of MoS2 on SiO2 (inset) with a step height of 1.7 nm along the edge of the MoS2 film, corresponding to ∼3 ML, in agreement with the Raman results.

Close modal

The initial low temperature baking of the sample in the presence of O2 (first step of the growth process) forms various volatile oxides of Mo, as confirmed by the Raman spectra of a sample that was taken out of the chamber after the initial oxidation phase. The spectra, as shown in Fig. 1(b), indicate characteristic peaks of MoO2, MoO3, and an intermediate Mo-oxide, Mo4O11.7 This was inspired by previous reports on the synthesis of MoS2, directly from either MoO2 or MoO3, since these oxides were shown to sulfidize more readily than the pure Mo metal.8,9 Here, we expand this concept by oxidizing Mo by a very limited O2 flow at a low temperature, which forms poor quality, O-deficient oxides with many chemically active sites at dangling bonds, leading to the formation of mixed oxides.

The Raman spectra of the optimized as-grown MoS2 sample is shown in Fig. 1(c), where the characteristic A1g and E12g peaks are observed to be separated by 23 cm−1, indicating 3–5 ML thick MoS2 (2–3 nm).5 The Mo-oxide peaks shown in Fig. 1(b) disappeared entirely after the sulfidation process, which indicates complete conversion of Mo-oxides to MoS2. The reduction of thickness during the growth process (from 7–10 nm Mo to 3–5 ML MoS2) is attributed to the sublimation of the volatile MoOx during the onset of sulfidation. A tapping mode atomic force microscopy (AFM) image taken on a Veeco DI3000 AFM is also shown in Fig. 1(d) which shows a film thickness of 1.7 nm and root mean square surface roughness of <0.4 nm.

To further demonstrate the usefulness of the proposed multi-step growth process, we compare it with a direct sulfidation method where the first two steps of the growth (oxidation at <400 °C and sulfidation at <500 °C) were skipped and a higher temperature (700–800 °C) was used for the single step sulfidation process instead. Due to the absence of growth-time thinning process, a much thicker MoS2 film was formed with several serious drawbacks: (1) thicker MoS2 had to be thinned and (2) the SiO2 was irreversibly damaged due to the exposure to elemental sulfur vapor at high temperature (Fig. 2(a)). While laser ablation,10 plasma treatment,11 and thermal annealing12 have been shown to effectively thin the MoS2, it would still be unusable until the MoS2 film was transferred to a fresh SiO2/Si substrate due to this degradation. Thus, by reducing the sulfidation temperature through a pre-oxidation step instead of using the direct sulfidation method (longer duration at higher temperature), the gate leakage current was reduced by as much as 108, while simultaneously limiting the thickness to <5ML, with a bandgap of 1.4 eV.13 The gate leakage current is much less than the drain current for all gate voltages (Fig. 3(c)), showing that the gate breakdown has been effectively suppressed. Since both samples shown in Fig. 3(c) had identical substrates at the beginning of the growth, this comparison clearly shows that the proposed method preserves the dielectric quality while the other method does not.

FIG. 2.

(a) Magnitude of gate leakage current through the SiO2 layer at VDS = 0.5 V, using the current three-step recipe and an alternative recipe with one-step direct sulfidation at high temperature. The insulating property of SiO2 is severely compromised during direct sulfidation of Mo. (b) Schematic of the device, showing the electrical test configuration and the pinching-off of the channel by the depletion region at VDS > VDS,sat. (c) Gate capacitance-voltage (C-V) characteristics of a MoS2 FET showing charge accumulation, depletion and inversion with different gate voltage biases and temperatures. The inset shows C-V curves using alternating sweep directions without any sign of hysteresis. (d) Estimation of flat band voltage (VFB) using the 1/C2 vs VGS curve near the knee point of the depletion region. Inset shows the energy band diagram of the MoS2-based MOS capacitor structure at thermal equilibrium at VGS = 0 V, where electrons are pulled near the MoS2/SiO2 interface by the electric field established by the interface charges and the work function difference between Si and MoS2.

FIG. 2.

(a) Magnitude of gate leakage current through the SiO2 layer at VDS = 0.5 V, using the current three-step recipe and an alternative recipe with one-step direct sulfidation at high temperature. The insulating property of SiO2 is severely compromised during direct sulfidation of Mo. (b) Schematic of the device, showing the electrical test configuration and the pinching-off of the channel by the depletion region at VDS > VDS,sat. (c) Gate capacitance-voltage (C-V) characteristics of a MoS2 FET showing charge accumulation, depletion and inversion with different gate voltage biases and temperatures. The inset shows C-V curves using alternating sweep directions without any sign of hysteresis. (d) Estimation of flat band voltage (VFB) using the 1/C2 vs VGS curve near the knee point of the depletion region. Inset shows the energy band diagram of the MoS2-based MOS capacitor structure at thermal equilibrium at VGS = 0 V, where electrons are pulled near the MoS2/SiO2 interface by the electric field established by the interface charges and the work function difference between Si and MoS2.

Close modal
FIG. 3.

(a) Transfer characteristics of MoS2 based FET with W = 20 μm, L = 100 μm, and VDS = 0.5 V, showing drain current as a function of gate voltage at different temperatures. The inset shows the linear ID vs VGS curves for the same data, showing the threshold voltage, VT's. (b) Transfer characteristics with drain voltages from 0.5 V to 2.5 V to show the effect of VDS at T = 300 K. (c) Normalized T = 300 K ID-VDS characteristics of the back-gated MOS2 FET with respect to gate voltage VGS, shown in two distinct regimes. The first one ranges from −8 to 4 V with electrons being the majority carriers. The second regime (dashed curves, VGS = −13–15 V) shows highly non-linear trends in the inversion regime with holes being the majority carriers. (d) Field effect mobility (μFET) and sheet carrier concentration (ns) as a function of VGS, with inset showing the weak temperature-dependence of electron μFET.

FIG. 3.

(a) Transfer characteristics of MoS2 based FET with W = 20 μm, L = 100 μm, and VDS = 0.5 V, showing drain current as a function of gate voltage at different temperatures. The inset shows the linear ID vs VGS curves for the same data, showing the threshold voltage, VT's. (b) Transfer characteristics with drain voltages from 0.5 V to 2.5 V to show the effect of VDS at T = 300 K. (c) Normalized T = 300 K ID-VDS characteristics of the back-gated MOS2 FET with respect to gate voltage VGS, shown in two distinct regimes. The first one ranges from −8 to 4 V with electrons being the majority carriers. The second regime (dashed curves, VGS = −13–15 V) shows highly non-linear trends in the inversion regime with holes being the majority carriers. (d) Field effect mobility (μFET) and sheet carrier concentration (ns) as a function of VGS, with inset showing the weak temperature-dependence of electron μFET.

Close modal

The MoS2 based back-gated FETs were characterized on a probe station with a temperature controlled chuck (300–500 K) to study the effect of temperature on the current-voltage (I-V) characteristics using an Agilent B2902 source measuring unit (SMU) and capacitance-voltage (C-V) characteristics using a HP4284A precision LCR meter. The schematic of the device structure is given in Fig. 2(b).

Fig. 2(c) shows the measured FET capacitance, CFET vs VGS curves for temperatures 300–500 K at 1 kHz, demonstrating the shape of a classical MOS capacitor. For VGS > 0 V, there is an accumulation of electrons, while VGS < 0 V causes the channel to be depleted of free electrons, eventually causing strong inversion below –12 V. CFET in accumulation approaches a value of ∼0.064 μF/cm2, corresponding to an oxide thickness, tox, of about 54 nm, consistent with the nominal value of 50 nm. In inversion, the CFET approaches a value ∼60% smaller because of the series resistance seen by the holes in inversion, which agrees with the limited drain current in inversion (Fig. 3(a)–3(c))), as well as the band structure, and will be discussed further below. The residual Cox for –10.5 V < VGS<–7 V is due to the limits of the measurement setup. The small increase with temperature is due to the contacts becoming more conductive, reducing the series resistance in the circuit, again consistent with the I-V characteristics below. The inset of Fig. 2(c) shows the C-V curves at 300 K with back and forth sweeping of the VGS, where the identical curves for both sweep directions indicate the absence of hysteresis.

We determine VFB using the following relation that relates 1/CG2 with VGS:14 

1CG2=1Cox2+k(VGSVFB),
(1)

where k is a constant depending on the unintentional doping concentration and a dielectric constant of MoS2. In Fig. 2(d), we plot 1/CG2 – 1/Cox2 as a function of VGS and perform a linear fit at the depletion region. The VFB, marked by the X-axis intercept of the fitting line, is estimated to be –4.8 ± 0.2 V. This VFB shows a significant shift from the –1 V value estimated from the work function difference between MoS2 and Si, and as reported by others.1,6 This shift in voltage can be attributed to positive interface charges, the density of which is calculated by nint = ΔVFB Cox/q ≈ 2 × 1012 cm−2. The charges are considered to be fixed charges, and not traps, since no hysteresis was observed in the I-V (supplementary material) or in C-V (Fig. 2(c) inset). This nint is very low for a non-native oxide-semiconductor interface, where even for native interfaces, nint can approach 1013 cm−2 (e.g., see Ref. 15). The corresponding equilibrium band diagram is shown in the inset of Fig. 2(d). These charges are attributed to this transfer-free growth process and are crucial to describing the I-V characteristics below.

Fig. 3(a) shows the transfer characteristic at VDS = 0.5 V, a region in which the FET is in the triode region for all ranges of VGS (Fig. 3(c)). The linear plots of ID, as shown in the inset of Fig. 3(a), were used to determine the threshold voltages (VT). At VGS = 0 V, the transistor is normally on, showing electron conduction in accumulation, with a threshold voltage, VT of about –8.8 V and an ON/OFF ratio of about 105. The accumulation subthreshold swing (SS) is 84 mV/decade which, along with the mobility mentioned below, is among the best for synthetic MoS2 devices, indicating the robustness of the gate dielectric to the growth process. The field effect mobility μFET is estimated from the linear FET characteristics

μFET=gmLWVDSCox,
(2)

where the transconductance gm = ∂ID/∂VGS|VDS=0.5 V, L is the channel length, W is the width of the FET, while Cox is the oxide capacitance per unit area. Here, we use the Cox measured in Fig. 2(c), and some representative gm vs VGS curves are provided in the supplementary material, from which μFET = 84 cm2/V s is estimated at accumulation, which decreases weakly with temperature (Fig. 3(d) inset). The weak temperature dependence is attributed to the canceling of the ionized impurity scattering (μFET increases with T), with phonon scattering (μFET decreases with T), as has been reported by others.6 VT also decreases with temperature at a rate of ∼4 mV/K, consistent with the calculations for thick oxide MOSFETs.16 

Fig 3(b) shows the transfer curves measured at varying VDS at 300 K. As VDS increases from 0.5 V to 2.5 V, the electron mobility increases. Fig. 3(c) shows the ID vs VDS family of curves for –8 V <VGS< 4 V in accumulation, and –13 V <VGS< –15 V in inversion, where the current is normalized by the gate width (20 μm). The first set of curves (solid lines, up to VDS = 5 V) are for VGS > VT, where VT is the threshold voltage of the FET, located at around –8.5 V. These curves have two distinct regions: a typical linear triode regime followed by a saturation regime that varies with VGS. For a channel with only a few atomic layers, this device carries a large amount of current (> 1 mA/mm), limited by the contact resistance of 1–4 kΩ, which was measured by transmission line model (TLM) measurements17 (details in the supplementary material). The maximum electric field in the channel is calculated to be less than 500 V/cm at VDS = 5 V, which is far smaller than the critical field for MoS2 as found in the literature.18 As a result, the drift velocity is calculated out to be ∼104 cm/s, using the carrier concentration obtained from C-V and the extracted μFET (discussed later).

The mobility in saturation under accumulation is extracted from the fit to Fig. 3(d) with

IDS=12WLμFET,satCox(VGSVT)2
(3)

from which a μFET,sat ∼20–25 cm2/V s was obtained for VT ∼−8.5 V, in agreement with the μFET value near pinch-off (Fig. 3(d)). The quadratic dependence of IDS with VGS, along with the low carrier velocity ∼104 cm/s, indicate that current saturation in these FETs is due to charge control and pinch off near the drain-end, as seen in long-channel MOSFETs. This is in contrast to velocity saturation seen in short channel HEMTs, which would exhibit a linear dependence of saturation current on VGS. At large VDS, deep in saturation, there is a region of depletion at the drain-end. However, free carriers injected from the accumulation channel near the source end are swept across the depletion region by the electric field, and the current remains nearly constant.

The second regime of VGS shown in Fig. 3(c) is indicative of the inversion current, i.e., hole transport as opposed to electron transport. A high degree of non-linearity is observed in the ID-VDS curves which is attributed to the large rectifying Schottky barrier (>1 eV) to the hole transport at the D-S contacts (Fig. 4).

FIG. 4.

(a) Energy band diagram of the MoS2 FET at low VDS. At VGS≫VT, thermionic emission (1) is the dominant mechanism of electron injection in the channel, which is facilitated by the low metal-semiconductor barriers at both ends of the channel by the accumulation of electrons in the channel. (b) At VGS ≪ VT, there are several possible mechanisms for hole transport in the valence band: (1) thermionic emission, (2) intra-band hole tunneling at both ends of the channel, and (3) band-to-band tunneling at the drain end.

FIG. 4.

(a) Energy band diagram of the MoS2 FET at low VDS. At VGS≫VT, thermionic emission (1) is the dominant mechanism of electron injection in the channel, which is facilitated by the low metal-semiconductor barriers at both ends of the channel by the accumulation of electrons in the channel. (b) At VGS ≪ VT, there are several possible mechanisms for hole transport in the valence band: (1) thermionic emission, (2) intra-band hole tunneling at both ends of the channel, and (3) band-to-band tunneling at the drain end.

Close modal

In Fig. 3(d), we show μFET as a function of VGS at VDS = 0.5 V. μFET increases with VGS, as the interface charges are screened by the field effect induced electrons in accumulation, increasing from ∼32 cm2/V s near depletion to ∼84 cm2/V s in accumulation with a channel carrier density of <1013 cm−2. The lowered effective mobility in saturation due to the reduced screening of charged impurity scattering at the pinched-off drain-end supports the presence of this mobility-limiting mechanism. The small increase in current with temperature is also consistent with this picture. The values of μFET at VDS = 0.5 V are used to calculate sheet carrier concentration (ns) in Fig. 3(d), using Jt =qnsμEDS, where J is the current density obtained from I-V measurements at VDS = 0.5 V and t is the average thickness of the film. Drain to source electric field is estimated to be ∼50 V/cm at VDS = 0.5 V.

Fig. 4 shows the non-equilibrium energy band diagrams along the transport direction at small VDS for (a) electron transport and (b) hole transport. Since the MoS2 Fermi level is pinned to the metal Fermi level and the contacts are made of annealed Ti/Au, which forms ohmic contacts to MoS2,6,19 at thermal equilibrium, there is a significantly smaller barrier in the conduction band (EC) than in the valence band (EV). Therefore, at ON-state of the device (VGS ≫ VT), electrons are injected/extracted by the source/drain contacts very efficiently. At low VDS (<1 V), band to band tunneling (BTBT) of electrons from the drain contact to the MoS2 EV is unlikely due to the EV being at a lower energy level than the drain Fermi level (Fig. 4(a)); hence, thermionic emission is the only mechanism of carrier injection at this regime, which resulted in the maximum mobility of >80 cm2/V s. The situation changes when VGS becomes significantly lower than VT, and the channel experiences strong inversion; so, there are two tunnel barriers seen by the holes as shown in Fig. 4(b), which limits the hole current significantly. Although the details of the hole transport mechanism is beyond the scope of this work, we indicate the possible hole transport mechanisms as (1) thermionic emission (low probability due to very high barriers), (2) intra-band hole tunneling at the both ends of the channel, and (3) band-to-band tunneling at the drain end. The highly non-linear behavior of the ID-VDS curves at inversion (Fig. 3(c)) also indicates the tunneling based mechanisms to dominate in this regime, as seen by others.20,21 This asymmetrical transport behavior may be useful in developing CMOS TFT circuits using MoS2 FETs, where choosing the right metal contacts could enhance the transport of either type of carrier while suppressing the other one, leading to greater voltage discrimination between logic states.

Table I compares our FET metrics with those of other MoS2 devices reported in the literature, including small area and large area devices, most of which required a transfer to a fresh substrate. It can be seen that our devices represent the state-of-the-art on SiO2 dielectrics in air, with the advantage of a transfer-free process, which is highly desirable for high throughput processing with the high yield.

In summary, we have demonstrated an improved growth technique for synthesizing top-down, large area, transfer-free 3–5 ML thick MoS2 on SiO2, reducing gate leakage by ≥108 compared to a longer duration, direct sulfidation method shown in this work. FETs fabricated from these layers were characterized in accumulation, depletion, and inversion modes to study the complete transfer behavior, which showed a normally-on accumulation mode characteristics with μFET > 80 cm2/Vs, SS < 90 mV/decade, and ON/OFF ratio of >105. The observed temperature stability of FET metrics up to 500 K is due to canceling of ionized impurity scattering and phonon scattering. Asymmetry was observed between the accumulation and inversion modes, which were attributed to the metal/semiconductor Schottky junctions at the source/drain ends.

See supplementary material for the details of the TLM measurement, hysteresis-free transfer curves, and transconductance curves at various drain bias voltages.

The authors acknowledge the financial support from the National Science Foundation (Grants Nos. ECCS 1559711, ECCS 1309466, and CBET 1606882).

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Supplementary Material