High pulsed current density β-Ga₂O₃ MOSFETs verified by an analytical model corrected for interface charge

$β$-Ga₂O₃ has recently emerged as a promising semiconductor for high-power, high-voltage device applications because of its ultra-wide bandgap of ∼4.8 eV and the corresponding expected critical breakdown field of ∼8 MV/cm.^1,2 $β$-Ga₂O₃ also has the advantage of a native substrate that can be synthesized in bulk by melt growth techniques with Sn and compensating Fe and Mg impurity doping.^3–5 Further, homoepitaxial channel conductivity for field effect transistor (FET) device applications has been demonstrated by Sn and Si doping using both molecular beam epitaxy (MBE) and metalorganic vapour phase epitaxy (MOVPE).^6,7 Disadvantages include low thermal conductivity⁸ and high hole effective mass.⁹ Depletion-mode metal-semiconductor FETs and Si-implanted metal-oxide-semiconductor FETs (MOSFETs) have been demonstrated with current densities exceeding 25 and 40 mA/mm, respectively.^2,10 Further, a depletion-mode MOSFET exceeding 750 V with a field plate and an enhancement-mode fin-array MOSFET up to 600 V were recently reported.^11,12 Finally, Green et al measured a lateral gate-drain critical field strength $>$3.8 MV/cm on a $β$-Ga₂O₃ MOSFET surpassing bulk GaN and SiC theoretical limits.¹³ 

While high blocking voltages have been achieved, insight into the high-current density potential of Ga₂O₃ MOSFETs has been largely unexplored. In this letter, we compare n-type $β$-Ga₂O₃ MOSFETs with various Sn channel concentrations and accurately predict the I-V performance using a simple electrostatic model that includes the gate oxide-gallium oxide interface charge voltage. The model which does not include self-heating effects or gate and drain dispersion is validated by isothermal pulsed I-V measurements with quiescent voltages and sweep parameters chosen to minimize dispersion effects. Agreement between measured and theoretical values for knee voltage (V_knee) and saturated drain current (IDSS) over a wide range of Sn doping concentrations is verified. A MOSFET with the highest channel charge-mobility (N_d-$μ$⁠) product achieved a pulsed current density of 478 mA/mm at a gate voltage of +4 V, much higher than previously reported DC values of 60 mA/mm for MOSFETs on homoepitaxial materials¹³ and 90 mA/mm for ion-implanted MOSFETs,¹¹ and second only to nanomembrane devices which achieved 610 mA/mm at a high forward gate bias of +120 V.¹⁴ This indicates the performance of the material system if self-heating due to the low thermal conductivity can be mitigated by cooling techniques or less thermally stressful applications. MOSFETs were fabricated on single crystal $β$-Ga₂O₃ grown by MBE on commercially available Fe-doped (010) semi-insulating substrates.⁶ Sn-doping was performed during the epitaxial growth, and carrier concentrations from 0.7 × 10¹⁸ to 1.6 × 10¹⁸cm⁻³ were measured after growth using electrochemical capacitance-voltage (C-V) measurements. Table I includes these values as N_d As Grown and also summarizes the measured data for all the samples as described further below.

A schematic process flow for the MOSFET is shown in Figure 1. Mesa isolation of the active channel was conducted using a BCl₃ inductively coupled plasma (ICP) dry etch and verified by profilometer measurements. Source and drain ohmic contacts were formed using an evaporated Ti/Al/Ni/Au metal stack and annealed for 60 sec in a nitrogen ambient at 470 °C.¹⁰ All the contacts were ohmic and the contact resistance (R_C) ranged from 10.7 to 80.0 ohm-mm as measured by the circular transfer length method (TLM)¹⁵ and shown in Table I. A 20 nm thick gate dielectric layer of HfO₂ was deposited by plasma-enhanced atomic layer deposition (ALD) at 250 °C without any surface pre-treatment. The gate dielectric was selectively removed in the ohmic pad regions by CF₄ reactive ion etching (RIE). Interconnects and 2-$μ$m long gates were patterned and deposited simultaneously using a 20/480 nm Ti/Au metal stack.

All device electrical testing was conducted on self-isolating ring-type FETs with a gate-source spacing of 0.5 $μ$m and a total source-drain spacing of 15 $μ$m (12.5 $μ$m G-D spacing). The total gate width was 422 $μ$m. All the structures were fabricated on a single 10 × 15 mm sample for each doping level. Figure 2 shows a static log transfer curve (I_D -V_GS) for the highest current density MOSFET with good transistor operation including a high on/off ratio of $>$10⁸ which was typical of all the devices measured regardless of the carrier concentration. Sister devices routinely achieved breakdown voltages >400 V for a 10.5 $μ$m gate-drain spacing and were limited by the failure of the gate dielectric.

Pulsed-IV measurements were conducted on MOSFET devices using an AMCAD system to provide a pulsed drain voltage and a Keysight E5270a to provide static gate bias. The pulse width was 200 ns with a quiescent drain bias of 0 V and a low duty-cycle of 0.001 percent to minimize thermal effects. The pulsed measurement used represents an ideal environment where gate and drain dispersion and self-heating effects can be ignored to evaluate the $β$-Ga₂O₃ MOSFET under ideal conditions and assess the material system. Figure 3 shows a pulsed-IV and static family of curves (I_D -V_DS) for the highest current density device. We extracted the knee voltage, V_knee, and the saturated drain current at V_G = 0 V, IDSS, from the inflection point in the pulsed-IV family of curves as shown in Figure 3. V_knee and IDSS are recorded for all the samples in Table I.

Capacitance-voltage (C-V) measurements were performed on lateral C-V structures with diameters of 75, 100, and 125 $μ$m using a B1505a equipped with a multi-frequency capacitance measurement unit and needle probes. A representative C-V curve for each sample is presented in Figure 4. Measurements were performed at frequencies that provided smooth C-V characteristics (100 kHz or 1 MHz), and measurement differences at frequencies between 1 kHz and 1 MHz were confirmed to have a negligible effect on the experimental results. We used the C-V measurement data to determine the off-state gate voltage, V_off, from the inflection point where the C-V curve (and therefore the available drift carriers) is minimized. This inflection point is shown for one device in Figure 4, and V_off is recorded for all the samples in Table I. The measured V_off is the gate voltage required to deplete the entire active layer:

where $VFB$ is the flat-band voltage, $d$ is the active layer thickness, $q$ is the electron charge, $Nd$ is the average active ionized dopant concentration in the active layer, $ϵsϵ0$ is the static dielectric constant of $β$-Ga₂O₃, and $Cox=ϵoxϵ0tox$ is the oxide capacitance per unit area.

Obtaining exact values for V_FB and N_d from measurements is difficult because of interface trap charges at the Ga₂O₃-HfO₂ interface and non-uniform carrier concentration in the active layer after fabrication as shown in Fig. 5. To simplify our calculations, we use the measured value of V_off from C-V data, substitute the ideal value of the flatband voltage:

where $Φx$ is the work function of the metal or semiconductor, $ϕt$ is the thermal voltage, $χS$ is the electron affinity of Ga₂O₃, and N_C is the effective density of states in the conduction band, and then solve for N_d iteratively starting from the maximum value of $VFB=ΦM−χS$ in (1). The result obtained is an average of N_d through the active layer thickness of each sample, and it is recorded in Table I as N_dPost Process. The difference between the carrier concentration before and after the fabrication results from the depletion of carriers at the epitaxy-substrate interface during processing and surface effects at the gate oxide-gallium oxide interface. The average value extracted from V_off agrees reasonably with average values extracted from post-process C-V profiling (Figure 5); however, C-V profiling is unreliable near the gate oxide-gallium oxide interface.

To verify the MOSFET current density, we used simple electrostatic model equations for the depletion region. We first acknowledge that the $β$-Ga₂O₃ MOSFET never creates a conducting inversion layer. Then, we started with the basic equation for the drain current¹⁶ 

where $v$ is the carrier velocity, W is the gate width, E(y) is the lateral electric field at a point under the gate (y is the direction along the gate length), V is the potential at a point along the channel, and $μ$ is the average carrier mobility. Then, assuming that the total channel charge per unit area, Q, is equal to the charge in the un-depleted portion of the channel and using the depletion approximation where

is the depletion distance and

is the surface potential, we can integrate (3) from source to drain to obtain

where

$A=2ϵsϵ0qNd2Cox$⁠, and V_ox is the voltage drop across the gate oxide. Equation (6) is valid in the depletion region only (⁠$Voff<VGS<VFB$⁠). We also modeled the effect of access resistance in the un-gated regions at the source and drain by implementing (6) in VerilogA in series with source and drain access resistors in the TINA circuit simulator.^17,18 Each access resistor was the sum of the measured R_C and the resistance for the ungated region based on R_SH and lateral device geometry (Figure 1).

The measured value of R_SH was also used with N_d calculated above to determine the effective mobility from the N_d-$μ$ product. This mobility is included in Table I as $μeff$ and agrees with the expected value from sister epitaxial growth. Finally, N_d, V_FB, and $μeff$ are used in (6) to estimate the drain current under isothermal, ideal-interface-state conditions. Additional parameters used in the model are shown in Table II. The modeled value of IDSS using (6) is included in Table I as IDSS_mod.

While our devices operate close to theoretical values under pulsed conditions, the drain current is still reduced by surface potential dependent negative charges at the gate oxide-gallium oxide interface²² that effectively reduce the gate voltage applied by:¹⁶ 

where $ΔQit(VG)$ is the interface charge difference between a device with filled and empty gate oxide-gallium oxide interface traps and C_G (V_G) is the total capacitance seen by the gate at a given gate voltage. In (9), we used the fact that the surface potential in (5) depends only on the gate voltage to replace $ΨS$ with V_G. Based on the assumption that the time constant of traps is slower than the AC signal, and that interface traps are filled and empty for reverse and forward C-V sweeps, respectively, we calculate $ΔVG$ from the charge difference between the two curves in Figure 4 and the measured C_G at every point. We then replace V_GS with V_GS-$ΔVG$ in (6) to obtain the values for IDSS_mod$ΔVG$ and V_knee mod$ΔVG$ in Table I. We also include the accumulation mode by solving (6) with V_GS = V_FB and adding an accumulation current:

In doing so, we note that effects of the normal field on $μeff$ have not been evaluated, and further investigation is required. In our case, where the normal field is very small, however, this addition to our model accurately predicts the I-V curve for V_G = +4 V. The result is shown in Figure 3 for our highest current density device. Similar agreement was observed for all but the lowest doped samples. As the doping level was decreased, the assumption that V_off is not significantly affected by interface trapped charges breaks down, and (1) using the ideal value of V_FB miscalculates N_d. In other words, as the doping concentration (or active layer thickness) is reduced, the magnitude of V_off (⁠$ΨS$⁠) is not sufficient to drive out negative interface trapped charges, and $ΔVG$ affects not only (6) but also (1). N_d calculated from (1) becomes dependent on V_G and transfer characteristics of the analytical model become inaccurate without additional advanced measurement techniques. With thin or lightly doped devices, the interface charge effect on $ΔVG$ and V_FB is significant. In fact, thin enhancement-mode devices have been reported¹⁴ with V_off > +75 V exceeding the band-gap-electron-affinity sum for $β$-Ga₂O₃ and indicating significant thickness of the gate oxide-gallium oxide interface trap layer. In these difficult cases, Hall measurements can be used to determine $μeff$⁠, but techniques must be developed to overcome anomalies at the gate oxide-gallium oxide interface to accurately determine N_d and V_FB.

In conclusion, we have shown the measured and analytically modeled effects on device performance as a function of Sn doping concentration. A $μeff$ of > 50 $cm2V·S$ was maintained for a device with N_d = 7.8 × 10¹⁷ cm⁻³, resulting in record-high pulsed current density for homoepitaxially grown $β$-Ga₂O₃ MOSFETs. The agreement between our simple MOSFET model with a gate-charge correction and the measured data highlights the importance of doping levels and interface optimization for future $β$-Ga₂O₃ MOSFET designs.

The authors would like to acknowledge Novel-Crystal Technology, Inc. for MBE growth.