We describe a method for transferring ultra large-scale chemical vapor deposition-grown graphene sheets. These samples can be fabricated as large as several cm2 and are characterized by magneto-transport measurements on SiO2 substrates. The process we have developed is highly effective and limits damage to the graphene all the way through metal liftoff, as shown in carrier mobility measurements and the observation of the quantum Hall effect. The charge-neutral point is shown to move drastically to near-zero gate voltage after a 2-step post-fabrication annealing process, which also allows for greatly diminished hysteresis.

Graphene is well-known for its desirable electrical properties,1 and with all of the intense focus on research in the material, new applications are being constantly discovered. While graphene is known to have its best electrical properties when it is single-crystalline and suspended,2,3 those attributes are currently not feasible for mass-produced devices. There have been very exciting developments related to improving non-suspended graphene's mobility on more exotic substrates such as hBN,4,5 as well as improving the chemical vapor deposition (CVD) growth process for producing better quality devices with large grain sizes.5–7 However, these developments are currently difficult to scale up and automate.

On the other hand, CVD-grown graphene is still the best way to repeatedly produce large areas of monolayer graphene, and SiO2 is a well-known substrate that is already integrated into many processes from semiconductor physics to MEMS,8,9 and beyond. Previous work has shown how to transfer large areas of CVD-grown graphene onto arbitrary substrates10–13 and remove contaminants.10,14 However, previous devices made with CVD-grown graphene on Si02 do not combine the desirable properties of high enough quality electrical characteristics to display the quantum Hall effect (QHE), a charge neutral point (CNP) near zero gate voltage, and a large device size, with typical finished devices being on the order of 10 μm.15 A large-scale integration of easily manufactured, high-quality graphene devices is desirable in many different applications, such as graphene transistors, broad-band optical modulators,16 and THz antennas.17 

Challenges arise when fabricating high-quality CVD-grown graphene devices, primarily due to the contaminants of all kinds easily attaching to graphene. With each step, much care must be taken to remove any existing organic or inorganic contaminants on the graphene and to prevent new contaminants from being attached. This paper presents a fabrication method that produces devices with CVD-grown graphene on SiO2 that are hundreds of microns in size and display the QHE.

A sheet of copper is supplied with CVD-grown graphene on only one side. Other sources of CVD graphene on copper typically have graphene on both sides of the foil, and in that case, an oxygen plasma can be used to remove the graphene from one side. A wet transfer process is used to place the graphene on the substrate, with cleaning steps to remove the inorganic and organic contaminants from the bottom of the graphene before transfer. These steps are similar to the method detailed by Liang et al., which itself includes a “modified RCA clean” process.10 

It is important to be sure that all the contaminants from the graphene are removed, as any resist residues can act as dopants and scattering centers to degrade electrical performance2,3 and to increase contact resistance.18,19 Acetone or other common solvents are not sufficient to remove the residues from resists such as poly(methyl methacrylate) (PMMA). A common technique to clean small graphene devices is to use current annealing,20 especially when the graphene is suspended, as it can effectively evaporate many contaminants and allow the graphene to self-heal.21 Other cleaning methods include mechanical cleaning with atomic force microscopy,22 exposure to ultra-violet light,23 ozone treatment,18,23 and annealing in vacuum24 or with gas flow.25 In the process detailed in this paper, the graphene is cleaned before transfer to a clean substrate, and then cleaned again after fabrication by a 2-step thermal annealing process.

The size of the graphene/copper foil pieces used here is 1 cm × 1 cm; however, the process can easily be upscaled to sizes of several cm2. PMMA with a molecular weight of 950 K is spun onto the graphene/copper foil and dried by air (Fig. 1(a)). A solution of Fe(NO3)3 is prepared with 5 g/100 ml of deionized (DI) water, and the PMMA/graphene/copper stack is placed to float in the solution with the copper side down and then left for at least 10 h for the copper to etch away (Fig. 1(b)). Subsequently, the graphene stack is transferred to clean DI water at least twice, waiting 5 min after each transfer. Similar to the method by Liang et al., the RCA clean step referred to as Standard Clean 2 is next, with a HCl/H2O2/H2O solution prepared in a 1:1:20 ratio. Once again, the stack is placed on this solution to clean the inorganic contaminants not removed by the Fe(NO3)3, such as oxides, for 15 min (Fig. 1(c)). The stack is once again transferred to clean beakers of DI water at least twice for 5 min each. Finally, the RCA clean step known as Standard Clean 1 (SC-1) is performed with a NH4OH/H2O2/H2O solution in a 1:1:100 ratio for 5 min (Fig. 1(d)) to remove organic contaminants. The cleaning time and chemical concentrations of H2O2 and NH4OH in SC-1 are lower than those reported in the modified RCA clean process in order to avoid bubble formation. The bubbles that get under the graphene stack can lead to the graphene tearing and are very difficult to remove before transfer. After the SC-1 step is complete, the graphene is again transferred to clean beakers of DI-water twice, waiting 5 min after each transfer.

FIG. 1.

Flow diagram of the sample preparation. PMMA is spun onto the graphene copper stack (a), before the copper is etched away (b). The graphene is cleaned in multiple steps removing inorganic (c) and organic (d) contaminants, scooped up with a SiO2 wafer piece (e) and then dried (f). The PMMA layer is removed with acetic acid (g), and the result is shown in (h). For the definition of the Hall contacts, the sample is coated with layers of LOR and photoresist, exposed and developed, before Ni and Au are deposited as adhesion and contact materials, respectively (i). After liftoff (j), the excess graphene is etched away (k), and the sample is mounted in a probe and baked under vacuum (l).

FIG. 1.

Flow diagram of the sample preparation. PMMA is spun onto the graphene copper stack (a), before the copper is etched away (b). The graphene is cleaned in multiple steps removing inorganic (c) and organic (d) contaminants, scooped up with a SiO2 wafer piece (e) and then dried (f). The PMMA layer is removed with acetic acid (g), and the result is shown in (h). For the definition of the Hall contacts, the sample is coated with layers of LOR and photoresist, exposed and developed, before Ni and Au are deposited as adhesion and contact materials, respectively (i). After liftoff (j), the excess graphene is etched away (k), and the sample is mounted in a probe and baked under vacuum (l).

Close modal

Wafers of thermally grown SiO2 on p-doped Si are prepared by carefully cutting into appropriately sized pieces with a diamond scribe. Any contaminants are cleaned off with sonication in acetone and then isopropanol before the wafers are dried with a N2 gun. The SiO2 is then treated with O2 plasma in order to make the surface more hydrophilic,26 so the graphene will stick to it more readily and minimize breakage. Within one minute of the substrate's O2 plasma exposure, the PMMA/graphene stack is scooped up and it is all dried in an oven set to 150 °C for 15 min (Figs. 1(e) and 1(f)). Finally, the PMMA is removed with acetic acid (Fig. 1(g)), which more cleanly removes PMMA residue than acetone, while at the same time not attacking either the graphene or the SiO2 substrate.14 At this point, the graphene is cleanly transferred to the substrate with minimal cracks or tears (Fig. 1(h)), with most defects existing previous to the transfer process. Many other defects can be explained by bumps, folds, or other surface features in the copper foil that the graphene was grown on. These features make it much less likely for the graphene to transfer tear-free, making it very important to keep the copper foil as flat as possible. As shown in Figs. 2(a) and 2(b), Raman spectra at 532 nm were taken in multiple locations to verify the reproducibility of the measurement and uniformity of the graphene monolayer.

FIG. 2.

(a) Optical microscopy image of a large clean area of graphene (dark purple) on a SiO2 substrate (light purple). Inset: Picture of a 1 cm × 1 cm SiO2 wafer with CVD graphene on top (dark blue). (b) Raman spectra with a 532 nm laser taken at the colored and numbered spots shown in (a), displayed with an artificial offset for clarity. The defect peak D is very small in all three measurements, which speaks for a high quality of graphene, and the G* peak is in the expected location. Also, due to the relative height of the G and 2D peaks, which is about one third, we can confirm that we see a monolayer of graphene.28 (c) Optical microscopy image of a 200 μm long and 22 μm wide graphene strip (light blue) on an SiO2 substrate (dark blue) with a contact layout typical for the Hall measurements. (Graphene contrast increased for visual effect in (a) and (c).)

FIG. 2.

(a) Optical microscopy image of a large clean area of graphene (dark purple) on a SiO2 substrate (light purple). Inset: Picture of a 1 cm × 1 cm SiO2 wafer with CVD graphene on top (dark blue). (b) Raman spectra with a 532 nm laser taken at the colored and numbered spots shown in (a), displayed with an artificial offset for clarity. The defect peak D is very small in all three measurements, which speaks for a high quality of graphene, and the G* peak is in the expected location. Also, due to the relative height of the G and 2D peaks, which is about one third, we can confirm that we see a monolayer of graphene.28 (c) Optical microscopy image of a 200 μm long and 22 μm wide graphene strip (light blue) on an SiO2 substrate (dark blue) with a contact layout typical for the Hall measurements. (Graphene contrast increased for visual effect in (a) and (c).)

Close modal

Once the graphene is on the target substrate, it must still have metal contacts deposited and be patterned into whatever shape is desired. Both of these steps must ideally be done without damaging or contaminating the graphene any more than absolutely necessary. The contacts are defined using photolithography, with a layer of Microchem LOR 5 A used between photoresist and graphene. This bi-layer stack tends to remove much more cleanly than photoresist alone,27 and after the removal, it results in high-quality devices. In our observation, it also results in a higher final yield of usable devices due to less undesired graphene removal during liftoff. Without a protective layer of LOR, negative photoresists tended to result in much worse yield than positive resists, possibly due to crosslinking of polymer chains during exposure. After exposure and development, a 5 nm layer of Ni is deposited by physical vapor deposition as an adhesion layer, followed by 50 nm of Au (Fig. 1(i)). Liftoff is then performed in a two-phase process. First, the sample is soaked in a bath of acetone, which removes photoresist and lifts off excess metal. Since an ultrasonic bath will damage the graphene, excess metal is instead gently removed by squeezing a pipette to agitate the acetone. Second, after all excess metal is removed, the LOR layer is removed by soaking it in Microposit Remover 1165 for 5 min. Finally, the sample is rinsed with isopropanol and dried with a N2 gun. The result is shown in Fig. 1(j).

For this sample, excess graphene is removed by using photolithography to cover the areas of graphene to be protected from O2 plasma. Finally, the sample is chemically cleaned with acetone and isopropanol, and then dried with N2. Figs. 1(k) and 2(c) show the result.

The sample is then mounted in a probe with air pumped out and replaced with a small quantity of He as an exchange gas. The longitudinal resistance is measured over a range of applied gate voltages at a temperature of 4.2 K at zero magnetic field. The sample is annealed under vacuum for 16 h at 350 °C to remove all water, including water trapped between graphene and substrate. The sample is then removed from vacuum and quickly mounted in a probe, and once again it is annealed in a tube oven under vacuum (Fig. 1(l)) at 140 °C for 72 h to remove any water absorbed from the atmosphere during mounting. During this time, the 2-point resistance of the Hall bar is observed to steadily increase from approximately 25 kΩ to a new maximum of 57 kΩ. Fig. 3 shows the increase in peak longitudinal resistance along with a dramatic shift of the charge neutral point (CNP) from Vg = 27 V to −4 V before and after annealing, respectively, which is evidential of the concentration of charged impurities being significantly reduced.29 The large peak shift is indicative of the removal of a majority of p-type dopants such as water,30 and the settling of the CNP at a negative gate voltage may be due to doping by the metal contacts or contact doping by SiO2 and any contaminants trapped between the graphene and metal during processing.31,32 When the sample is re-exposed to atmosphere, the CNP drifts toward the prebake value, though performing the baking process once more moves the CNP back to near-zero gate voltage. Thus, a capping layer is necessary to prevent adsorbates from altering the electrical characteristics of the graphene when exposed to air.

FIG. 3.

Longitudinal resistance Rxx of the graphene strip versus gate voltage Vg before (dashed blue line) and after (solid red line) baking out the sample. The measurements were recorded at T = 4.2 K. A possible explanation for the postbake shift of the CNP of over 30 V is the removal of the contaminants on the graphene that act as dopants, originating from resist residues or the atmosphere.

FIG. 3.

Longitudinal resistance Rxx of the graphene strip versus gate voltage Vg before (dashed blue line) and after (solid red line) baking out the sample. The measurements were recorded at T = 4.2 K. A possible explanation for the postbake shift of the CNP of over 30 V is the removal of the contaminants on the graphene that act as dopants, originating from resist residues or the atmosphere.

Close modal

The CNP changes by at most 0.1 V, depending on the direction the gate voltage is swept. When there is still a significant amount of water on the substrate, this hysteresis can easily be on the order of a few or even tens of volts.26 This effect is typical of graphene on SiO2, and the relatively low hysteresis seen in this sample implies that most of the water has been removed by the previous annealing step.33 

The magnetic field is then set to 8 T, and the gate voltage is scanned once more at 4.2 K. Multiple quantum Hall levels for monolayer graphene were seen, as shown in Fig. 4. Clear plateaux for the Hall resistance, Rxy, at filling factors of ν = ±4(n + 1/2) and Landau level index n = 0, 1,…, are seen with corresponding drops in the longitudinal resistance, Rxx.35 Further magnetoresistance measurements were performed to find charge carrier density and mobility at nine different gate voltages with the result shown in Fig. 5. At the CNP, the mobility is measured to be around μCNP = 3760 cm2/(Vs) and the charge carrier density is nCNP = 1.58 × 1011 cm−2. These measurements show that the fabrication method presented here results in a mobility at the charge neutral point that approaches values obtained when using exfoliated graphene on SiO2,36 implying that the graphene is very clean and has been minimally damaged by the sample production process.

FIG. 4.

The longitudinal (solid red line) and the Hall resistance (dashed blue line) versus the gate voltage Vg at fixed magnetic field B = 8 T measured at 4.2 K, obtained through a standard 4-point-measurement approach, show multiple quantum Hall levels with filling factors labeled. Inset: Schematic of the graphene strip and contacts, with a distance between the longitudinal contacts of 100 μm.

FIG. 4.

The longitudinal (solid red line) and the Hall resistance (dashed blue line) versus the gate voltage Vg at fixed magnetic field B = 8 T measured at 4.2 K, obtained through a standard 4-point-measurement approach, show multiple quantum Hall levels with filling factors labeled. Inset: Schematic of the graphene strip and contacts, with a distance between the longitudinal contacts of 100 μm.

Close modal
FIG. 5.

The charge carrier density (solid red line) and mobility (dashed blue line) versus the gate voltage Vg at 4.2 K after the final annealing step. The values were obtained by performing magnetoresistance measurements at the displayed values for Vg. Points are connected by B-spline curves. The charge carrier density is linear with respect to gate voltage away from the CNP, which implies the gate oxide provides the dominant capacitive effect, which is expected due to the oxide thickness.34 The rounding of the charge carrier density graph near the CNP is due to charged electron/hole puddles induced by charged impurities, including those in the substrate.29 

FIG. 5.

The charge carrier density (solid red line) and mobility (dashed blue line) versus the gate voltage Vg at 4.2 K after the final annealing step. The values were obtained by performing magnetoresistance measurements at the displayed values for Vg. Points are connected by B-spline curves. The charge carrier density is linear with respect to gate voltage away from the CNP, which implies the gate oxide provides the dominant capacitive effect, which is expected due to the oxide thickness.34 The rounding of the charge carrier density graph near the CNP is due to charged electron/hole puddles induced by charged impurities, including those in the substrate.29 

Close modal

In summary, we have presented a procedure that results in clean large-area graphene devices of high quality on a SiO2 substrate. The 2-step liftoff aids greatly in unbroken large graphene structures, and the 2-step annealing process, as well as other cleaning steps, results in a realization of near-ideal mobilities and a low hysteresis with observation of the quantum Hall levels. Hence, our processing approach now enables a large-scale integration of high-quality graphene layers in devices such as THz-emitters, thermo-power couplers, and possibly flexible thin-film sensors.

The authors acknowledge the funding support from the MURI'08 of the Air Force Office of Scientific Research (AFOSR; Award No. FA9550-08-1-0337), and the Center for Ultrafast Imaging (CUI) at the University of Hamburg, which is sponsored by the Deutsche Forschungsgemeinschaft (DFG) through grant EXC-1074.

1.
A. C.
Neto
,
F.
Guinea
,
N.
Peres
,
K. S.
Novoselov
, and
A. K.
Geim
,
Rev. Mod. Phys.
81
,
109
(
2009
).
2.
K. I.
Bolotin
,
K.
Sikes
,
Z.
Jiang
,
M.
Klima
,
G.
Fudenberg
,
J.
Hone
,
P.
Kim
, and
H.
Stormer
,
Solid State Commun.
146
,
351
(
2008
).
3.
X.
Du
,
I.
Skachko
,
A.
Barker
, and
E. Y.
Andrei
,
Nat. Nanotechnol.
3
,
491
(
2008
).
4.
C. R.
Dean
,
A. F.
Young
,
I.
Meric
,
C.
Lee
,
L.
Wang
,
S.
Sorgenfrei
,
K.
Watanabe
,
T.
Taniguchi
,
P.
Kim
,
K.
Shepard
 et al,
Nat. Nanotechnol.
5
,
722
(
2010
).
5.
L.
Banszerus
,
M.
Schmitz
,
S.
Engels
,
J.
Dauber
,
M.
Oellers
,
F.
Haupt
,
K.
Watanabe
,
T.
Taniguchi
,
B.
Beschoten
, and
C.
Stampfer
,
Sci. Adv.
1
,
e1500222
(
2015
).
6.
N.
Petrone
,
C. R.
Dean
,
I.
Meric
,
A. M.
van Der Zande
,
P. Y.
Huang
,
L.
Wang
,
D.
Muller
,
K. L.
Shepard
, and
J.
Hone
,
Nano Lett.
12
,
2751
(
2012
).
7.
Z.
Yan
,
J.
Lin
,
Z.
Peng
,
Z.
Sun
,
Y.
Zhu
,
L.
Li
,
C.
Xiang
,
E. L.
Samuel
,
C.
Kittrell
, and
J. M.
Tour
,
ACS Nano
6
,
9110
(
2012
).
8.
J. S.
Bunch
,
A. M.
Van Der Zande
,
S. S.
Verbridge
,
I. W.
Frank
,
D. M.
Tanenbaum
,
J. M.
Parpia
,
H. G.
Craighead
, and
P. L.
McEuen
,
Science
315
,
490
(
2007
).
9.
X.
Zang
,
Q.
Zhou
,
J.
Chang
,
Y.
Liu
, and
L.
Lin
,
Microelectron. Eng.
132
,
192
(
2015
).
10.
X.
Liang
,
B. A.
Sperling
,
I.
Calizo
,
G.
Cheng
,
C. A.
Hacker
,
Q.
Zhang
,
Y.
Obeng
,
K.
Yan
,
H.
Peng
,
Q.
Li
 et al,
ACS Nano
5
,
9144
(
2011
).
11.
J. W.
Suk
,
A.
Kitt
,
C. W.
Magnuson
,
Y.
Hao
,
S.
Ahmed
,
J.
An
,
A. K.
Swan
,
B. B.
Goldberg
, and
R. S.
Ruoff
,
ACS Nano
5
,
6916
(
2011
).
12.
J.
Song
,
F.-Y.
Kam
,
R.-Q.
Png
,
W.-L.
Seah
,
J.-M.
Zhuo
,
G.-K.
Lim
,
P. K.
Ho
, and
L.-L.
Chua
,
Nat. Nanotechnol.
8
,
356
(
2013
).
13.
L. G.
Pimenta
,
Y.
Song
,
T.
Zeng
,
M.
Dresselhaus
,
J.
Kong
, and
P.
Araujo
, in
APS Meeting Abstracts
(
2014
), Vol.
1
, p.
37009
.
14.
M.
Her
,
R.
Beams
, and
L.
Novotny
,
Phys. Lett. A
377
,
1455
(
2013
).
15.
J.
Sun
,
Y.
Nam
,
N.
Lindvall
,
M. T.
Cole
,
K. B.
Teo
,
Y. W.
Park
, and
A.
Yurgens
,
Appl. Phys. Lett.
104
,
152107
(
2014
).
16.
M.
Liu
,
X.
Yin
,
E.
Ulin-Avila
,
B.
Geng
,
T.
Zentgraf
,
L.
Ju
,
F.
Wang
, and
X.
Zhang
,
Nature
474
,
64
(
2011
).
17.
K.
Tantiwanichapan
,
J.
DiMaria
,
S. N.
Melo
, and
R.
Paiella
,
Nanotechnology
24
,
375205
(
2013
).
18.
W.
Li
,
Y.
Liang
,
D.
Yu
,
L.
Peng
,
K. P.
Pernstich
,
T.
Shen
,
A. H.
Walker
,
G.
Cheng
,
C. A.
Hacker
,
C. A.
Richter
 et al,
Appl. Phys. Lett.
102
,
183110
(
2013
).
19.
J.
Lee
,
Y.
Kim
,
H.-J.
Shin
,
C.
Lee
,
D.
Lee
,
C.-Y.
Moon
,
J.
Lim
, and
S. C.
Jun
,
Appl. Phys. Lett.
103
,
103104
(
2013
).
20.
J.
Moser
,
A.
Barreiro
, and
A.
Bachtold
,
Appl. Phys. Lett.
91
,
163513
(
2007
).
21.
A.
Barreiro
,
F.
Börrnert
,
S. M.
Avdoshenko
,
B.
Rellinghaus
,
G.
Cuniberti
,
M. H.
Rümmeli
, and
L. M.
Vandersypen
,
Sci. Rep.
3
,
1115
(
2013
).
22.
A.
Goossens
,
V.
Calado
,
A.
Barreiro
,
K.
Watanabe
,
T.
Taniguchi
, and
L.
Vandersypen
,
Appl. Phys. Lett.
100
,
073110
(
2012
).
23.
C. W.
Chen
,
F.
Ren
,
G.-C.
Chi
,
S.-C.
Hung
,
Y.
Huang
,
J.
Kim
,
I. I.
Kravchenko
, and
S. J.
Pearton
,
J. Vac. Sci. Technol. B
30
,
060604
(
2012
).
24.
A.
Pirkle
,
J.
Chan
,
A.
Venugopal
,
D.
Hinojos
,
C.
Magnuson
,
S.
McDonnell
,
L.
Colombo
,
E.
Vogel
,
R.
Ruoff
, and
R.
Wallace
,
Appl. Phys. Lett.
99
,
122108
(
2011
).
25.
M.
Ishigami
,
J.
Chen
,
W.
Cullen
,
M.
Fuhrer
, and
E.
Williams
,
Nano Lett.
7
,
1643
(
2007
).
26.
K.
Nagashio
,
T.
Yamashita
,
T.
Nishimura
,
K.
Kita
, and
A.
Toriumi
,
J. Appl. Phys.
110
,
024513
(
2011
).
27.
A.
Nath
,
A. D.
Koehler
,
G. G.
Jernigan
,
V. D.
Wheeler
,
J. K.
Hite
,
S. C.
Hernández
,
Z. R.
Robinson
,
N. Y.
Garces
,
R. L.
Myers-Ward
,
C. R.
Eddy
, Jr.
 et al,
Appl. Phys. Lett.
104
,
224102
(
2014
).
28.
A.
Ferrari
,
J.
Meyer
,
V.
Scardaci
,
C.
Casiraghi
,
M.
Lazzeri
,
F.
Mauri
,
S.
Piscanec
,
D.
Jiang
,
K.
Novoselov
,
S.
Roth
 et al,
Phys. Rev. Lett.
97
,
187401
(
2006
).
29.
S.
Adam
,
E.
Hwang
,
V.
Galitski
, and
S. D.
Sarma
,
P. Natl. Acad. Sci. U. S. A.
104
,
18392
(
2007
).
30.
K. S.
Novoselov
,
A. K.
Geim
,
S. V.
Morozov
,
D.
Jiang
,
Y.
Zhang
,
S. V.
Dubonos
,
I. V.
Grigorieva
, and
A. A.
Firsov
,
Science
306
,
666
(
2004
).
31.
G.
Giovannetti
,
P.
Khomyakov
,
G.
Brocks
,
V. V.
Karpan
,
J.
Van den Brink
, and
P.
Kelly
,
Phys. Rev. Lett.
101
,
026803
(
2008
).
32.
K.
Nagashio
and
A.
Toriumi
,
Jpn. J. Appl. Phys., Part 1
50
,
070108
(
2011
).
33.
M.
Lafkioti
,
B.
Krauss
,
T.
Lohmann
,
U.
Zschieschang
,
H.
Klauk
,
K. V.
Klitzing
, and
J. H.
Smet
,
Nano Lett.
10
,
1149
(
2010
).
34.
T.
Fang
,
A.
Konar
,
H.
Xing
, and
D.
Jena
,
Appl. Phys. Lett.
91
,
092109
(
2007
).
35.
Y.
Zhang
,
Y.-W.
Tan
,
H. L.
Stormer
, and
P.
Kim
,
Nature
438
,
201
(
2005
).
36.
Y.
Huang
,
E.
Sutter
,
N. N.
Shi
,
J.
Zheng
,
T.
Yang
,
D.
Englund
,
H.-J.
Gao
, and
P.
Sutter
,
ACS Nano
9
,
10612
(
2015
).