Thermal resistance optimization of GaN/substrate stacks considering thermal boundary resistance and temperature-dependent thermal conductivity

Gallium Nitride (GaN) materials have excellent material properties such as high critical electric field (3.3 MV/cm), high saturation velocity (2.5 × 10⁷ cm/s), and high thermal/chemical/physical stability, making them ideal for high power and high-frequency devices.¹ Substrates on which GaN-based devices are grown vary greatly from conventional sapphire and silicon carbide to emerging silicon and diamond. Nonetheless, the lattice mismatch for GaN device epitaxy of these substrates leads to high-defectivity (≫10⁸ cm⁻²) devices, suffering from not only poor electrical characteristics² but also degraded thermal performance associated with the high thermal boundary resistance (TBR).³ Device thermal resistance, defined as the maximum temperature increase in the device divided by the power dissipation of the device, is dominated by the TBR. Recent works have traced up to 50% of the device thermal resistance back to TBR.⁴ As device lifetime has an exponential dependence on the temperature,^5,6 such high power GaN-devices (e.g., 40 W/mm)⁷ are thermally limited.⁸ Conventional approaches addressing this thermal limitation include switching to high thermal conductivity substrates (such as SiC⁹ and diamond^10,11) and TBR-engineering.¹² Alternatives such as utilizing lattice-matched free-standing GaN substrate which provides low-dislocation density and reduces TBR are also under investigation to enhance electrical and thermal performance of GaN-based devices. More challenging and expensive but effective approaches include convection cooling by flowing liquid and/or vapor through microchannels or nanoporous structures.¹³ 

In this work, through technology computer-aided design TCAD Synopsys,¹⁴ we investigate the effects of substrates {diamond, silicon carbide, silicon, and sapphire}, thermal boundary resistance {10–60 m²K/GW}, heat source lengths {10 nm–20 μm}, and power dissipation levels {1–8 W} on the thermal resistance of GaN/substrate stacks. With respect to available literature,^15,16 we include detailed TBR and temperature-dependent thermal conductivity analysis, which points towards an optimum separation between the heat source and the substrate for an improved thermal management.

The physical model¹⁷ used to calculate the lattice temperature (T) in the TCAD software is described by the equation, −$∇⋅(κ∇T)=S$⁠, where κ is the thermal conductivity and S is the heat source density. For thermally resistive boundary conditions, $κn̂⋅∇T=Text−TRth$ is imposed, where $n̂$ denotes a unit vector in the outer normal direction, T_ext is the external temperature, and R_th is the external thermal resistance. For an ideal case, where the external thermal resistance is zero, $T=Text$ is imposed. Similarly, TBR is treated as a resistive boundary condition at the interface between materials 1 and 2, using the equation, $S→L,2=S→L,1=T2−T1RTB$⁠, where $S→L,1$ and $S→L,2$ are the heat flux density leaving materials 1 and 2, respectively, and R_TB is the TBR.

The schematic of the simulated device structure is shown in Fig. 1 inset (see the supplementary material). The device structure is designed to replicate a GaN HEMT device. However, thermally less significant components such as the source and drain contacts, and the AlGaN layers are excluded for simplicity.¹⁸ The simulated device has a two-layer structure composed of a thickness varying GaN layer on top of a 300-μm-thick substrate. The length and width of the device are fixed to 20 μm and 1 mm, respectively. The substrate is heatsinked ideally, which is kept at 300 K. To make a fair comparison between various substrates, a constant heat flux is supplied through the heat sources (instead of keeping the heat source to a fixed temperature). Throughout this work, unless otherwise specified, 1 W of power is dissipated through GaN on Si, SiC, and diamond substrates. For the GaN-on-sapphire device, however, 0.3 W of power is dissipated to prevent the unrealistic rise in temperature (above 800 K) in the device. Every other face of the device (except the top surface) is taken as adiabatic.

The thermal boundary resistance between GaN and substrates, and temperature-dependent thermal conductivities of GaN and substrates are included in our simulations (Table I). Recent experimental works report differing TBR values from sample to sample¹⁹ and as a function of temperature.²⁰ However, no TBR model yet exists matching the experimental data. Hence, in an effort to represent a wide TBR range, we employed various TBR values {10 to 60 m²K/GW} in our studies (Table I).

Figure 1 shows the thermal resistance across GaN/Si as a function of GaN layer thickness (t_GaN) {from 0.05 to 4 μm}, various heat source lengths (L_HEAT) {0.01, 0.1, 1, 5, 10, and 20 μm}, and TBR {20 and 40 m²K/GW}. We have plotted only the Si substrate in Fig. 1; however, all substrate choices lead to the same representative behavior. Figure 1 suggests that regardless of the heat source length and GaN layer thickness, thermal resistance increases with increasing TBR. This shows that device thermal resistance can be minimized by reducing the TBR. In addition, by observing the thermal resistance–GaN layer thickness curve for L_HEAT = 20 μm case, we see that when the heat source length is comparable to the device length, reducing the GaN layer thickness is helpful in minimizing the thermal resistance. However, as the heat source length decreases (e.g., 0.01 μm), the thermal resistance no longer decreases monotonously with GaN layer thickness, but rather it has a minimum. Another way to express this observation is that if the heat source length is relatively small, shrinking the GaN layer thickness beyond a certain point could lead to a significant increase in the device's thermal resistance.

The existence of a thermal resistance minimum depends strongly on the heat source length and the TBR. For instance, when L_HEAT = 10 μm, thermal resistance–GaN layer thickness curve does not have a minimum when TBR = 20 m²K/GW, whereas it does when TBR = 40 m²K/GW. As the heat source length gets smaller (L_HEAT ≤ 10 μm), minima exist even with small TBRs. When the hotspot is localized, the GaN layer acts as a buffer layer for the heat flux to spread out before going through the highly resistive GaN/substrate interface. If the GaN layer is too thin, the concentrated heat flux coming out from the heat source passes through the interface directly without spreading. This causes the region right under the heat source to heat up significantly, which leads to a high thermal resistance. On the other hand, if the GaN layer is too thick, the thermal resistance originating from the thermal conductivity of the GaN layer increases and also causes the thermal resistance to increase.

Figure 2 shows the thermal resistance of GaN/substrate devices as a function of the GaN layer thickness (see the supplementary material). Here, we investigate the effects of the GaN layer thickness on the thermal resistance with varying TBR on different substrates. The heat source length is fixed to 0.01 μm in the rest of the simulations to represent the hotspot of an operating GaN HEMT.²¹ Similarly, for every GaN/substrate combination, the thermal resistance increases with increasing TBR. Due to the sheer thickness of the substrate, the overall thermal resistance of the device is observed to be dominated by the substrate's thermal conductivity. The symbols on each curve indicate the minimum thermal resistance points. These points show that with increasing TBR, the optimum separation between the heat source and the substrate increases.

Figure 3 plots the minimum thermal resistance as a function of optimal GaN layer thickness for different substrates and different TBR values. For comparison, the thermal resistance calculation results are plotted using both temperature-independent (closed symbols) and temperature-dependent (open symbols) thermal conductivities of GaN and substrate materials. The temperature independent thermal conductivity values are chosen as the temperature-dependent thermal conductivity values at 300 K.

Figure 3 shows that when the temperature-dependent thermal conductivity is used, compared to when the temperature-independent thermal conductivity is used, the minimum thermal resistance of all devices increases. Concurrently, for a given TBR of each substrate, the optimum thickness for the minimum thermal resistance is reduced, and the amount of reduction in the optimum thickness increases as we switch to less thermally conductive substrates. This is primarily attributed to the reduction in thermal conductivity of the GaN layer under elevated temperatures. Since the heat source is located at the top of the device, the thermal conductivity reduction is most substantial in the GaN layer right beneath the heat source. Because of this reduction, the effective heat source length is larger than the actual heat source length. As shown in the analysis of Fig. 1, this heat source length extension causes the optimal GaN layer thickness to decrease.

For instance, Fig. 3 results show that, in the case of the optimized GaN-on-diamond stacks with TBR = 10 m²K/GW, the thermal conductivity near the hotspot drops from 160 W/m·K down to ∼140.5 W/m·K, which is approximately a 12% reduction, whereas, in the case of GaN-on-sapphire stacks with TBR = 10 m²K/GW, GaN thermal conductivity near the hotspot plummets 45%, from 160 W/m·K to ∼85.5 W/m·K.

To quantify the impact of minimizing thermal resistance through GaN layer thickness optimization, the amount of hotspot temperature reduction achieved through a diamond substrate device with an optimized GaN layer thickness compared to a device with a reference thickness (i.e., t_GaN = 4 μm) is plotted under various power dissipation levels (from 1 to 8 W) in Fig. 4. We have limited the dissipated power to 8 W not to exceed hotspot temperature of 800 K for GaN material stability.⁸ As seen in Fig. 4, the temperature reduction increases with dissipated power for all TBR values and is maximized when TBR is smallest (i.e., TBR = 10 m²K/GW). Optimizing the GaN layer thickness has more effect when the TBR is smaller due to the thermal conductivity reduction in GaN and substrate material under elevated temperatures. It is important to note that judging by the steeper slope of the curves for smaller TBRs, setting equally distanced t_GaN points as the reference for each case, would result in the same conclusion. Overall, our work shows that temperature reduction with thickness optimization becomes more prominent as the dissipated power increases as well as it is critical to minimize TBR. Additionally, from the analysis of Fig. 3, we recognize that the optimal GaN layer thickness shrinks as the dissipated power increases and the TBR decreases. For GaN-on-diamond stack (with a heat source length of 10 nm), the optimal GaN layer thickness, under dissipated power level of 8 W and GaN-diamond TBR of 10 m²K/GW, is around 500 nm.

In conclusion, we have studied via TCAD Sentaurus the effects of heat source length, GaN layer thickness, substrate choice, TBR, and dissipated power on the thermal resistance and hotspot temperature of GaN/substrate stacks. The GaN/substrate thermal resistance is shown to have minima when the heat source is localized and a non-zero TBR exists at the GaN/substrate interface. The GaN layer thickness is optimal when it is thick enough to prevent heat crowding and thin enough to keep the thermal resistance small. The temperature-dependent conductivity is shown to be critical in the thermal studies of GaN/substrate stacks. The temperature rise in the GaN layer causes the GaN thermal conductivity to drop (e.g., for optimized GaN-on-sapphire stack with TBR = 10 m²K/GW and 0.3 W of dissipated power, the drop was from 160 W/m·K to ∼85.5 W/m·K) and increases the effective size of the heat source. This increase leads to an optimal GaN layer thickness that is smaller than the value predicted using the temperature-independent thermal conductivity. The high dissipated power through GaN/diamond stacks shows that the effect of GaN layer thickness optimization becomes more significant as the dissipated power increases and TBR decreases. As the dissipated power increases to 8 W, the optimal GaN layer thickness decreases to 500 nm (for TBR = 10 m²K/GW), and by optimization, the heat source temperature can be reduced 50 °C. Overall, pushing the GaN HEMTs towards higher power levels (>40 W/mm) requires engineering of novel architectures composed of submicron-thick GaN layers on high thermal conductivity substrates (e.g., diamond) with a low TBR.

See supplementary material for separate figures of each substrates in Fig. 2, and for comparison of 2-D and 3-D simulations.

This work was supported by the Air Force Office of Scientific Research (AFOSR) through Young Investigator Program Grant No. FA9550-16-1-0224 and was carried out in the Micro and Nanotechnology Laboratory, University of Illinois at Urbana-Champaign, IL, USA.