Large electron concentration modulation using capacitance enhancement in SrTiO₃/SmTiO₃ Fin-field effect transistors

The recent discovery of extremely high electron density 2-dimensional electron gases (2DEGs) at the heterointerface of polar/nonpolar oxides such as LaAlO₃/SrTiO₃, GdTiO₃/SrTiO₃, and SmTiO₃/SrTiO₃ has opened up the area of oxide heterostructure electronics.^1–6 These 2DEG densities are of the order of ½ electron per unit cell corresponding to ∼3.3 × 10¹⁴cm⁻², about one order higher than 2DEG densities found in traditional semiconductor heterostructures like III-Nitrides.^3,7 Because of the high electron density, these 2DEGs are interesting for realizing high power devices and tunable infrared plasmonic devices.⁷ Apart from these traditional applications, large electron concentration modulation in transition metal oxides can also enable functionally different devices based on phase-transitions.^8,9 Because of the strong electron-electron interactions in d-orbital derived bands of transition metal oxides, large carrier concentration changes (∼10¹⁴cm⁻² and more) can significantly change the system energy and hence the stable ground state.^8,9 A major challenge in realizing all these applications is the field-effect modulation of extreme concentrations of mobile electrons, intermediate to the concentrations in semiconductors and metals. Electron concentration modulation approaching ∼10¹⁵cm⁻² has been achieved using ionic liquids in electric double layer transistors (EDLTs).^10–12 Gating of phase transitions in complex oxides has also been demonstrated by this approach.^13–16 This EDLT approach is attractive for exploring properties of various materials as a function of carrier concentration. However, for practical applications, it is necessary to modulate carrier concentrations at high frequencies; EDLTs cannot satisfy this requirement. Because of the large inertia of ions, the high capacitance observed in EDLTs is only limited to low (∼1 kHz) modulation frequencies.¹¹ 

In traditional semiconductor devices, carrier concentration modulation at high frequencies is achieved using high-dielectric constant (high-k) gate oxides such as HfO₂ and Al₂O₃. One of the components in the heterointerfaces hosting extreme density 2DEGs is SrTiO₃, a high-k material with a large dielectric constant of ∼300 at room temperature, which yields large gate capacitances.⁷ Similar to other high-k gate dielectrics, SrTiO₃ dielectric constant remains high till THz frequencies.¹⁷ SrTiO₃ is also expected to have a large breakdown field because of its large energy bandgap of 3.2 eV. Since the charge modulated in a field effect transistor (FET) is proportional to the gate capacitance and voltage applied across it, SrTiO₃ is expected to modulate large carrier concentrations when used as a gate dielectric. Record electron concentration modulations have indeed been demonstrated using SrTiO₃ gate dielectric both in heterostructures hosting 2DEGs and in MESFET devices.^7,18,19

Though SrTiO₃ is a promising gate dielectric for extreme electron concentration modulation, it has limitations. The dielectric constant of SrTiO₃ is strongly dependent on the electric field.²⁰ In bulk SrTiO₃, the dielectric “constant” decreases from 300 at zero field to ∼25 at a field of ∼10 MV/cm.²⁰ This reduction in dielectric constant limits the maximum charge modulation possible using SrTiO₃ as a gate dielectric. Additionally, a low dielectric constant interfacial layer (the so-called “dielectric dead layer”) is usually present at the gate metal/SrTiO₃ interface.^{18,19,21–23} This interfacial layer capacitance acts in series with SrTiO₃ capacitance, thus reducing the net observed gate capacitance and hence, the charge modulation in the FET. To completely modulate the extreme density 2DEGs, we need approaches to reduce interfacial layers,²³ increase the dielectric constant of SrTiO₃,^24,25 or other alternative approaches to increase the gate capacitance in the presence of these two effects. In state-of-the-art complementary metal-oxide-semiconductor (CMOS) FETs, fin shaped channels are being used for superior electrostatic gate control in nanoscale geometries.^26,27 In the fin geometry, the channel carrier concentration is modulated not only from the top but also from the sides as shown in Fig. 1(a). The fin geometry can enhance the gate capacitance even in the presence of the field-dependent dielectric constant and interfacial layer limitations. In this work, we fabricate Au-gated planar FETs and compare them with FinFETS. The FETs are fabricated on hybrid molecular beam epitaxy (hMBE) grown SrTiO₃/SmTiO₃ epilayers hosting extreme density 2DEGs. We demonstrate capacitance enhancement in the FinFETs compared to planar FETs. Further capacitance enhancement is observed as fin widths are scaled down. Using this capacitance enhancement, we show a record electron concentration modulation of ∼2.4 × 10¹⁴cm⁻² using SrTiO₃ gate dielectric.

For fabricating the FETs, 60 nm SrTiO₃/5 nm SmTiO₃ thin films were grown on insulating (001) oriented (LaAlO₃)_0.3(Sr₂AlTaO₆)_0.7 (LSAT) substrates (Fig. 1(b)) using hMBE.^28,29 In this growth technique, Ti and O are provided using the organometallic precursor titanium isopropoxide, while Sr and Sm are provided using an effusion cell. Growth details of such heterostructures by hMBE technique have been reported earlier.^3,5,28,29 Planar FETs (plFET) and FinFETs (fFETs) with different fin widths were then fabricated on two halves of the grown sample. Fins with three different fin widths were fabricated (referred as fFET1, fFET2, and fFET3 henceforth in the order of decreasing fin-widths).

For defining the device mesas and fins, an e-beam evaporated Cr/Pt (20/30 nm) metal stack was used with Pt on top as a mesa etch mask. Mesa etching was performed in an inductively coupled plasma-reactive ion etching (ICP-RIE) system. A BCl₃/Ar plasma (45/5 sccm, 5 mTorr, 1000 W ICP, 97 W RIE) was used for etching to a depth of 120 nm. Cr/Pt metal mask was then lifted-off in a chrome etchant. Subsequently, Al/Ni/Au (40/40/100 nm) ohmic contact metal was deposited using E-beam evaporation. A contact resistance of ∼3.2 Ω mm was extracted at a drain bias of ∼1 V using transmission line measurements. Finally, a Schottky gate of 160 nm Au was deposited by e-beam evaporation on the two samples (plFET and fFET). Prior to the Schottky metal deposition, oxygen plasma treatment (20 sccm, 333 mTorr, 14 W) of the SrTiO₃ surface was performed in a RIE system to reduce the gate leakage and improve rectification.⁷ An electron mobility of ∼8.1 cm²/V s and sheet electron concentration of ∼3.09 × 10¹⁴cm⁻² was measured for the 2DEG at 300 K after the complete fabrication using Hall-effect measurements performed in a mesa isolated Van der Pauw pattern.

For measuring the FET characteristics, a Cascade probe station was used with a Keithley 4200 semiconductor characterization system. The drain current-gate voltage (I_ds–V_gs) transfer characteristics of the fabricated plFET with 50 μm width and of all three fFETs (fFET1, fFET2, and fFET3) are shown in Figs. 2(a)–2(c), respectively. These measurements are taken at a drain bias of 1 V. Maximum reverse gate bias is limited by oxide breakdown. Since gate metal is in direct contact with the SrTiO₃/SmTiO₃ 2DEG, high-gate leakage might be expected. However, the measured gate leakage is low for all devices possibly due to the large dielectric constant of SrTiO₃ and large Schottky barrier height of Au.¹⁹ As observed from Fig. 2(b), the drain current decreases in fFETs as fin widths are scaled down. By comparing the measured drain currents between plFET and fFETs at zero gate bias, we estimate the achieved fin widths in various fFET devices. Such an estimate is shown in Table I. We have been able to vary fin widths from 535 nm in fFET1 down to 192 nm in fFET3. From the Hall-effect measurements the zero gate bias 2DEG density is ∼3.09 × 10¹⁴cm⁻². Assuming that current modulation in FETs is mostly due to carrier concentration change, the calculated 2DEG charge modulation as a function of gate bias will be ∼3.09 × 10¹⁴ × |q| [I_ds (V_gs = 0 V)− I_ds(V_gs)]/I_ds(V_gs = 0 V), where q = −1.6 × 10⁻¹⁹ C, the charge on an electron. This charge modulation value is shown in Fig. 3(a). The slope of charge modulation vs. gate voltage curves in Fig. 3(a) corresponds to apparent gate capacitance $Cap$ obtained in the FET devices. The extracted gate capacitance values near zero bias, shown in Table I, show a clear enhancement of the gate capacitance in fFETs compared to the plFET. The gate capacitance further increases as fFET fin widths are scaled down (Fig. 3(b)).

To verify the fin and device dimensions, we performed cross-sectional and top-view scanning electron microscope (SEM) imaging of the fFETs as shown in Fig. 4. fFET1 and fFET2 fin dimensions as measured from cross-sectional SEM are ∼640 nm and ∼350 nm, respectively, in close agreement to the values we estimated based on drain currents in Table I, whereas fFET3 fin seems much wider. From the SEM images, it is observed that the fFET3 fin is roughly composed of three parallel fins (Figs. 4(c), 4(f), and 4(g)). The left fin is definitely not continuous and does not contribute to the drain current. The right fin is also discontinuous in the gate-drain access region. From the cross-sectional SEM, the central fin-width is ∼160 nm, quite close in value to ∼192 nm fin-width we estimated based on drain current in fFET3. Both the current levels and SEM images therefore suggest that only the central fin is the actual channel for fFET3 device. We note that there is a ∼10%–20% discrepancy in fin-widths estimated from drain current and from cross-sectional SEM. This small discrepancy however has no effect on the conclusions drawn in this letter.

In all the FETs, we are modulating only part of the channel under the gate, with source/drain access regions contributing to a series parasitic resistance independent of gate bias. This access resistance roughly degrades the real capacitance $Cr$ to the apparent capacitance by the relation $Cap∼CrRch/(Rch+Rac)$⁠, where $Rch$ is the channel resistance under the gate and $Rac$ is the total access resistance. Near zero bias, the sheet resistance in the channel and access regions is approximately the same. Therefore, the real capacitance is estimated as $Cr∼Cap(Rch+Rac)/Rch∼Cap(Lg+Lac)/Lg$⁠, where $Lg$ is the gate length (equal to channel length under the gate) and $Lac=Lgs+Lgd$ is the access region length (⁠$Lgs$⁠:gate-source access region length, $Lgd$⁠: gate-drain access region length). These lengths in the plFET device are $Lg$ = 3.27 μm and $Lac$ = 3.66 μm, while values in fFET devices are given in Table I and shown in Figs. 4(d)–4(f). The real capacitance values corrected for this access region effect are also given in Table I. For the plFET device which has no capacitance enhancement, the capacitance value extracted from the FET transfer characteristics is ∼3.37 μF/cm² (Table I). To verify our extraction procedure, we also performed capacitance-voltage (C-V) measurements (frequency 100 kHz, signal amplitude 30 mV) on circular Schottky diodes fabricated on the same sample along with the plFETs. The capacitance value measured at zero gate bias was ∼3.35 μF/cm², quite close to the value we extracted from the transfer characteristics of the plFET. This confirms the accuracy of our capacitance extraction procedure; the access resistance corrected capacitance $Cr$ values in Table I represent the real gate capacitance in plFET and fFET devices. To calculate the capacitance enhancement in fFETs, the ratio of the fFET gate capacitance to plFET capacitance is shown in Table I. In the fFET3 device, we have achieved a geometrical capacitance enhancement of ∼1.94× compared to the planar FET.

In Fig. 3(b), the capacitance enhancement in FinFET devices is compared to a simple gate capacitance model based on a wrap-gate transistor geometry (Fig. 3(b) inset). The capacitance per unit length $L$ for a cylinder is $Ccylindrical/L=2πε0εox/ln(b/a)$⁠, where $ε0$ is the free space permittivity, $εox$ is the dielectric constant of the material between the capacitor plates, and $a$ and $b$ are the inner and outer radius of the capacitor, respectively. For a parallel plate capacitor with width $W$ and length $L$⁠, capacitance per unit length is given as $Cparallel/L=ε0εoxW/tox$⁠, where $tox$ is the distance between the plates (equal to SrTiO₃ thickness in our case). To compare the cylindrical and parallel plate capacitors, we make the assumptions that distance between the plates is same in both cases, $(b−a)∼tox$⁠, and width of the parallel plate capacitor is same as inner circumference of the cylindrical capacitor $2πa∼W$⁠. With these assumptions, the capacitance enhancement of cylindrical geometry will be $Ccylindrical/Cparallel∼2π/[(W/tox)ln(1+2π/(W/tox))]$⁠. In Fig. 3(b), this geometrical capacitance enhancement is plotted as a function of $W/tox$ along with comparison of capacitance enhancement obtained in our FinFET devices (with $tox$ = 60 nm and $W$ as fin-width estimated from drain currents and from cross-sectional SEM). Clearly, the capacitance enhancements we obtained from the measured transfer characteristics of fFETs and those based on the simple model agree quite well. The match is good for both the drain current and cross-sectional SEM fin-width estimations. Fig. 3(b) also suggests that further capacitance enhancements are expected with decreasing fin-width. Therefore, FinFET geometry is a very promising way to increase the gate capacitance and has the potential for complete charge modulation in SrTiO₃/SmTiO₃ extreme density 2DEGs and in other complex oxide systems. The total 2DEG density modulation achieved in plFET and fFET devices can be extracted as ∼3.09 × 10¹⁴ × [I_ds (V_gs = +1.1 V) − I_ds(V_gs = V_br)]/I_ds(V_gs = 0 V), where 3.09 × 10¹⁴ cm⁻² is the zero bias 2DEG density from Hall measurement and V_br is the reverse breakdown voltage of the FET. Among all measured devices, we obtained a maximum 2DEG density modulation of ∼2.4 × 10¹⁴cm⁻² in fFET3 device with a current ON/OFF ratio of ∼3.2. The measured I_ds − V_ds characteristics of this device are shown in Fig. 5. This electron density modulation is highest ever achieved in any solid-state device using approaches other than ionic liquids.

To summarize this work, we fabricated both Au-gated planar FETs and Fin-FETs with varying fin-widths on SrTiO₃/SmTiO₃ thin films hosting extreme density 2DEGs. Compared to planar FETs, we experimentally observe a geometric gate capacitance enhancement in the fabricated FinFETs. We demonstrate further gate capacitance enhancement by scaling down the SrTiO₃/SmTiO₃ fin widths. In the fabricated FinFETs with the narrowest fin-widths, we are able to double the gate capacitance compared to the fabricated planar FETs, leading to a record 2DEG electron concentration modulation of ∼2.4 × 10¹⁴cm⁻². We believe that by further scaling down the fin-widths, complete modulation of the ½ electron per unit cell 2DEG density would be possible. We hope that improvements in large carrier concentration modulation in complex oxides using the FinFET approach will ultimately lead to reversible control of emergent phenomena in these materials.

This work was supported by the Extreme Electron Concentration Devices (EXEDE) MURI program of the Office of Naval Research (ONR) through Grant No. N00014-12-1-0976.