Gate assisted contact-end Kelvin test structures and gate assisted four-probe structures have been designed and fabricated to measure the field effects of current crowding at the source/drain contacts of top-gate MoS2 field effect transistors. The transistors exhibited n-type transistor characteristics. The source/drain contact resistance was measured by using both gate-assisted Kelvin and gate-assisted four-probe structures. The values of contact resistance measured by these two test structures are significantly different. The contact-front contact resistance obtained from the four-probe structure is strongly influenced by field effects on current crowding, while the contact-end resistance obtained from the Kelvin test structure is not. The metal-MoS2 contact current transfer length, LT, can be determined from the comparison between these two measurements. LT was observed to increase linearly with increasing gate voltage. This work indicates that the contact characteristics can be more precisely measured when both gate-assisted test structures are used.

Recently, transition metal dichalcogenides (TMDs), such as MoS2 and WSe2, have attracted intensive attention for applications in future electronics and photonics.1,2 Monolayer and few-layer MoS2 can be considered as two-dimensional (2D) semiconductors. They have an energy bandgap (Eg) ranging from 1.2 eV to 1.8 eV, which depends on the thickness of MoS2.3–5 In particular, monolayer MoS2 has a direct bandgap (Eg = 1.8 eV) which leads to extraordinary electrical and optoelectronic properties.6–12 For the consideration of short channel effects in metal-oxide-semiconductor field effect transistors (MOSFETs), the monolayer MoS2, which has an intrinsic atomically thin body and well-passivated surfaces, represents the ultimate small medium for device scaling.13 In addition, the transparent feature and robust lattice structure in 2D MoS2 are very attractive for flexible electronics.14–16 

MOSFETs are the basic building blocks for electronic circuits. High-performance MoS2 FETs are considered a promising technological thrust for next-generation electronics.1,2 Because the performance of 2D MoS2 FETs is significantly influenced by the properties of source/drain (S/D) contacts, it is critical to fully understand and properly engineer contacts between metals and MoS2. A variety of contact materials and structures have been proposed and studied to achieve effective Ohmic contacts on MoS2.16–27 And recently, the current distribution under the metal contacts has also been considered.28,29 These results are mostly based on bottom-gated FETs where the channel current was not effectively tuned by the gate. This is not the case in top-gate MoS2 FETs. A statistical study of MoS2 transistors30 indicated that top-gated FETs have a larger contact resistance as compared to back-gated ones. Because, unlike back-gated devices, the carrier density in MoS2 under source/drain metal contacts will not change at higher positive gate bias in top-gated transistors. Our previous work has shown that using the gate-assisted test structures is an excellent approach to measure properties of the metal contacts to low-dimensional materials.31 Here, we present a study on current crowding in metal-MoS2 contacts determined by using both gate-assisted Kelvin structures and four-probe structures where the channel current is effectively tuned by a top gate.

We fabricated Ag-contacted bilayer MoS2 transistors with Au/Ti/Al2O3 top gates on SiO2/Si substrate. Our devices show good n-type current-voltage (I-V) characteristics. Then gate assisted Kelvin structure and four-probe method were used to analyze the contacts. The contact resistance extracted from both methods is significantly different because the position where the voltage is sampled is different. By comparing the contact resistance extracted from both methods, we found that the current transfer length (LT) of Ag-contact on MoS2 transistors ranged from 114.3 nm to 128.5 nm, which increased with increasing gate voltage. The channel sheet resistance, which is measured by the four-probe method, is larger than the contact resistance. This indicates that the MoS2 transistors are channel-dominant. Our results have shown that the gate affects not only the channel resistance but also the current crowding at the contacts.

In this work, the MoS2 was grown on a 285 nm SiO2/Si substrate via chemical vapour deposition (CVD). During the CVD of MoS2, MoO3 and sulfur are used as the precursors. In detail, an alumina crucible with 5 mg MoO3 powder was placed in the center a tube furnace. An alumina crucible with abundant amount of sulfur (≈1.5 g) was placed at the entrance location of the furnace. The substrate was placed in the downstream 2 cm away from the MoO3 crucible. During the growth, the CVD furnace was maintained at 800 Torr (about 1.07 × 105 Pa) with 100 sccm ambient Ar as carrier gas. Before heating, the whole system was pumped to 200 mTorr and then flushed with Ar for 3 times. A stable pressure of 800 Torr was achieved before the heating processes. The heating processes included a 30-min ramp up to 850 °C and a hold at 850 °C for 30 min. After heating, the furnace was naturally cooled to room temperature. After growth, MoS2 flakes are found to spread over the SiO2/Si substrates. As shown in the optical image in Fig. 1(a), the MoS2 flakes are typically triangular or hexagonal in shape. Fig. 1(b) shows a Raman map of the same location in Fig. 1(a). Plotted here is the integrated intensity from 340 cm−1 to 430 cm−1 including both the E2g in plane and the A1g out-of-plane modes. The optical contrast and Raman map suggest that the MoS2 flake thickness is quite uniform. Raman spectrum of a representative point on the uniform MoS2 flakes (Fig. 1(c)) shows that the separation between the two major peaks is 21 cm−1, indicating these are two-layer MoS2 flakes.32 

FIG. 1.

MoS2 crystal characterization: (a) Optical image of typical MoS2 flakes grown on SiO2/Si substrate. The scale bar is 5 μm. (b) Raman mapping of the MoS2 flakes in (a). The intensity in the image is the integrated signal intensity from 340 cm−1 to 430 cm−1. (c) Raman spectrum of a representative point on MoS2 flakes, compared to exfoliated 1L MoS2.

FIG. 1.

MoS2 crystal characterization: (a) Optical image of typical MoS2 flakes grown on SiO2/Si substrate. The scale bar is 5 μm. (b) Raman mapping of the MoS2 flakes in (a). The intensity in the image is the integrated signal intensity from 340 cm−1 to 430 cm−1. (c) Raman spectrum of a representative point on MoS2 flakes, compared to exfoliated 1L MoS2.

Close modal

To fabricate MoS2 MOSFETs, first, the MoS2 flakes on the substrate were located with an optical microscope. Conventional lithography processes were then applied to define the device structures. 5 nm Ag/50 nm Au was deposited on MoS2 as the S/D contacts. Ag was chosen because it has been reported for forming a good contact on WSe2,33 which is a similar material to MoS2. And our previous work shows that Ag forms a smooth and solid film on MoS2 which makes the carrier transport efficiently across the contacts.34 Five parallel metal contacts were deposited on a MoS2 triangle flake to form the FETs, gate assisted Kelvin test structures and four-probe structures with the same contacts. Then, a rectangular MoS2 channel was defined by O2 plasma etching. To integrate the gate dielectric, 1 nm Al was deposited on MoS2 and then oxidized in air as a seeding layer before the atomic layer deposition (ALD) of 30 nm Al2O3. This will promote gate dielectric quality.35 The ALD of Al2O3 was performed at 300 °C with trimethylaluminum (TMA) and H2O as precursors. Finally, 5 nm Ti/50 nm Au was deposited as top gate. The top gate covers the whole structure including the channels and five S/D contacts. Therefore, all four channels share a common gate. A schematic of device structure and scanning electron microscopic image of two adjacent channels and three contacts are shown in Figs. 2(a) and 2(b), respectively. The channel length (LG) and width (W) are 370 nm and 4 μm, respectively. And the contact length (LC) is 1.09 μm.

FIG. 2.

Device structure and I-V characterization of a representative MoS2 FET: (a) Schematics of MoS2 FETs. (b) SEM image of a MoS2 transistor. Scale bar in this image is 1 μm. (c) ID-VG, and (d) ID-VD characteristic. The orange arrows indicates the voltage sweeping direction during the measurement and the black arrows pointing to the corresponding scale labels for the data shown in linear and log scale.

FIG. 2.

Device structure and I-V characterization of a representative MoS2 FET: (a) Schematics of MoS2 FETs. (b) SEM image of a MoS2 transistor. Scale bar in this image is 1 μm. (c) ID-VG, and (d) ID-VD characteristic. The orange arrows indicates the voltage sweeping direction during the measurement and the black arrows pointing to the corresponding scale labels for the data shown in linear and log scale.

Close modal

The devices were then measured by a semiconductor parameter analyser (Hewlett-Packard® 4156) in a probe station (Cascade® summit semi-automated probe station) at room temperature. Figs. 2(c) and 2(d) show the I-V characteristics of a typical MoS2 FET with details mentioned above. The channel current is normalized to current per one μm in channel width. The transistor exhibits strong n-type device characteristics which is similar to those reported by other groups.9,15–17 The small hysteresis in IDVG measurement indicates a good quality of Al2O3 which is used as gate dielectric. Also, the On-state current of these FETs is quite large compared to the published results.9,15–17,36,37 The threshold voltage and field effect mobility are extracted from the linear fitting of IDVG curve measured at VD = 50 mV. The threshold voltage is −10.2 V. At a small VDS, the field effect mobility of the transistor can be extracted from the linear mode ID, expressed as

μeff=LW1VDS1CoxIDVGS.
(1)

Here, VGS should be large enough and VDS should be small to keep the transistor working in linear mode. The value of the field effect mobility of our device is 7.8 cm2 V−1 s−1. This value is close to some recent publications using similar device structures.37,38 The linear relationship between drain current (ID) and drain voltage (VD) at low voltage indicates good S/D contacts.

In order to evaluate the metal contacts on MoS2, contact resistance measurements using both gate assisted Kelvin test structure and gated assisted four-probe test structure were performed on these MoS2 FETs. Figs. 3(a)–3(c) show the contact resistance measured by the gate assisted Kelvin test structure. The measurement set-up is illustrated in Fig. 3(a). In the Kelvin test structure, ID is driven through the middle contact by the MoS2 FET on the left. Non-local voltage (V23) was measured between the middle and right electrodes. Since a common gate is applied to the whole test structure, both channels are biased to the same conditions. Because there is no current flowing through the right channel and contact on the right, V23 is measured as the voltage drop at the end edge of MoS2 underneath the middle contact (source of the FET on the left). As shown in Fig. 3(b), the curves of V23 versus ID at different gate voltage are quite linear, indicating an Ohmic contact. The overlap of the V23 curve at different VG shows that the contact resistance obtained by Kelvin test method (RC-K) is not affected by VG. Fig. 3(c) shows the variation of RC-K which is the slope extracted from the linear fitting of V23ID curves. The value of RC-K is only a little more than 20 Ω, which is much lower than the contact resistance extracted from other methods in previous publications.22,28,29

FIG. 3.

Gate assisted contact measurement: (a) Set-up of gate assisted Kelvin measurement; (b) V23-ID measured at different VG in Kelvin test structure; (c) RC-K extracted from the linear fitting of V23 and ID at different VG. (d) Set-up of gate assisted four-probe measurement; (e) Channel sheet resistance at different VG measured by four-probe test structure; (f) Contact resistance (RC) extracted from four-probe measurement.

FIG. 3.

Gate assisted contact measurement: (a) Set-up of gate assisted Kelvin measurement; (b) V23-ID measured at different VG in Kelvin test structure; (c) RC-K extracted from the linear fitting of V23 and ID at different VG. (d) Set-up of gate assisted four-probe measurement; (e) Channel sheet resistance at different VG measured by four-probe test structure; (f) Contact resistance (RC) extracted from four-probe measurement.

Close modal

Then, a gate assisted four-probe measurement was carried out to obtain the contact resistance and further understand the contact behaviour. The measurement set-up is shown in Fig. 3(d). A voltage source was connected to the S/D contacts at the ends to drive the current through the channel under the gate voltage varying from −5 V to 0 V. The ID and the voltage difference between the second and third contacts (V23) are measured at the same time. Based on previous publications, the transfer length (LT) is typically in hundreds of nm scale.28,29 The contact length we used in the two middle contacts is comparably large. So, the voltage distribution across the two middle contacts must be accounted for.39 The voltage drop on the two middle contacts would contribute a resistance of RM to the total resistance we measured. So

R14=2RC+2RM+3Rch,
(2)
R23=RM+Rch.
(3)

R14 and R23 can be extracted by the linear fitting of VD and V23 vs. ID. RC is the contact resistance. RM can be viewed as parallel resistance of 2RC and the resistance of MoS2 under the contact. Theoretically, the sheet resistance of MoS2 under the contacts should not change under different gate bias, because the contact metal shields it from the top gate.30 But, as we will discuss later, it may not be the reality. To simplify the calculation, we assumed that the sheet resistance of MoS2 under the contacts is the same with the one in the channel. So RM and the channel resistance (Rch) can be estimated

RM=2RCLCWRsh2RC+LCWRsh,
(4)
Rch=LGWRsh.
(5)

Combining Eqs. (2)–(5), we can solve RC and Rsh

RC=(1LCLG)(R143R23)+(1LCLG)2(R143R23)2+4LCLG(R143R23)(R142R23)4,
(6)
Rsh=WLG[(R142R23)(1LCLG)(R143R23)+(1LCLG)2(R143R23)2+4LCLG(R143R23)(R142R23)2].
(7)

Figs. 3(e) and 3(f) show the channel sheet resistance and contact resistance varying with gate voltage, respectively. The channel conductance is effectively tuned by the gate (see Fig. 3(e)) as expected. It is quite interesting that the contact resistance is also effectively tuned by the gate (see Fig. 3(f)). Compared to the channel resistance, the contact resistance is higher in these transistors, indicating that these are contact-dominated MoS2 transistors.

It should be noted that RC is much larger than RC-K and strongly depends on the gate voltage. This provides clear evidence of current crowding at metal-MoS2 contacts. According to transmission line model (TLM),40–43 illustrated in Fig. 4, the current transport in a contact is concentrated at the front of the contact. The voltage at the front of the contact is much higher than the voltage at the end of the contact. The voltage distribution in MoS2 under a metal contact can be expressed as40–43 

V(x)=ρCRshcosh((LCx)/LT)Wsinh(LC/LT)ID,
(8)

where ρC is contact resistivity, x is the position on MoS2 where the voltage is samples, LC is the contact length (1.09 μm in our devices), Rsh is the sheet resistance of MoS2 under contact, and LT is current transfer length of MoS2. It is the distance which the current would penetrate into the MoS2 under the metal contact, i.e., the length of MoS2 used as effective contact. In a conventional bulk FET, LT is defined as

LT=ρC/Rsh.
(9)
FIG. 4.

TLM for contact resistance. The positions where the voltage is sampled in Kelvin method and four-probe measurement are pointed.

FIG. 4.

TLM for contact resistance. The positions where the voltage is sampled in Kelvin method and four-probe measurement are pointed.

Close modal

Here we still use Eq. (8) to express the voltage distribution under the contact in our devices. In the Kelvin test structure, the non-local voltage at the middle contact (V23) is measured at the end of the contact (i.e., x = LC), so

RCK=V(LC)ID=ρCRshWsinh(LC/LT).
(10)

However, in the four-probe method, the voltage on the contact is measured at the front of the contact (i.e., x = 0), so

RC=V(0)ID=ρCRshcosh(LC/LT)Wsinh(LC/LT).
(11)

It is clear that the ratio of RC to RC-K can be expressed as

RCRCK=cosh(LC/LT).
(12)

Therefore, the ratio of RC over RC-K is highly dependent on the ratio of the contact length over transfer length. Since RC is much larger than RC-K in our devices, the LC is much larger than LT. The current is concentrated at the front part of the contact. As shown in Fig. 5(a), the LT of the MoS2 devices can be extracted from the ratio of RC over RC-K. The LT is weakly affected by the gate bias: it increases from 114.3 nm when VG equals to −5 V to 128.5 nm for VG equals to 0 V. These values are slightly larger than those in the previous work which also shows LT increased with increasing gate voltage in bottom gated MoS2 transistors.28 

FIG. 5.

(a) Transfer length and contact resistivity of MoS2 transistors: (a) current transfer length and (b) contact resistivity at different VG.

FIG. 5.

(a) Transfer length and contact resistivity of MoS2 transistors: (a) current transfer length and (b) contact resistivity at different VG.

Close modal

In this work, LC is much larger than LT. So, RC can be approximately expressed as

RCρCWLT.
(13)

The contact resistivity ρC can be extracted from Eq. (13). As plotted in Fig. 5(b), ρC sharply decreases with increasing gate voltage. This means that the contact resistivity of the S/D contacts in a MoS2 transistor is strongly dependent on gate voltage. So, the contacts also contribute to the switching of these MoS2 transistors. It may indicate that, in addition to minimizing contact resistance, the gate voltage can also be used to modulate the barrier so that the device performance can be optimized where a barrier at the metal contact is preferred, such as in solar cells and photovoltaic devices. Unlike bulk devices, the band bending in 2D MoS2 transistors takes place along the current transport direction instead of the vertical direction.22 Even though the top-gate would not affect the charge density under the contact,30 it affects the barrier height and width along the edge of the contacts. As the gate bias gets higher, the band in the channel bends downward. However, the energy band of MoS2 under the contact would not change because it is shielded from the top gate by the metal contact. The barrier between the MoS2 under contact and in the channel gets lower and narrower. As a result, the contact resistivity gets lower. Meanwhile, the current transfer length increases a little from 114.3 nm to 128.5 nm. It may be a result of the limited density of state in 2D MoS2. At higher gate bias, the current density is higher. The limited density of state in 2D MoS2 requires a larger area for the carrier injection. Correspondingly, the transfer length increases. In total, the lower contact resistivity and larger transfer length result in a lower contact resistance at higher gate bias.

In summary, n-type MoS2 FETs were fabricated with a conventional lithography process. All MoS2 transistors exhibited good n-type I-V characteristics. The contacts of the MoS2 transistors were analyzed with gate assisted contact measurement structures including Kelvin test structure and four-probe test structure. Contact resistance is smaller than the channel resistance, indicating that these MoS2 transistors are channel-dominant devices. The values of contact resistance extracted from Kelvin test structure and four-probe test structure are significantly different. According to TLM, this difference is due to the current crowding and the different voltage sampling positions in each method. The current transfer length, which is extracted based on the ratio of the contact-front and contact-end resistance obtained by these two methods, increases with increasing the gate voltage. Our result clearly shows that the gate effectively modifies the contact resistivity through the current crowding, which should be taken into consideration during the design and fabrication of 2D semiconductor devices and circuits.

This work was supported in part by the U.S. NIST Grant 60NANB11D148 and U.S. NSF Grant ECCS-1407807.

This research was performed in part at the NIST Center for Nanoscale Science and Technology. We identify certain commercial equipment, instruments, or materials in this article to specify adequately the experimental procedure. In no case does such identification imply recommendation or endorsement by the National Institute of Standards and Technology, nor does it imply that the materials or equipment identified are necessarily the best available for the purpose.

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