Low temperature pulsed laser deposited (PLD) ultrathin boron nitride (BN) on SiO2 was investigated as a dielectric for graphene electronics, and a significant enhancement in electrical transport properties of graphene/PLD BN compared to graphene/SiO2 has been observed. Graphene synthesized by chemical vapor deposition and transferred on PLD deposited and annealed BN exhibited up to three times higher field effect mobility compared to graphene on the SiO2 substrate. Graphene field effect transistor devices fabricated on 5 nm BN/SiO2 (300 nm) yielded maximum hole and electron mobility of 4980 and 4200 cm2/V s, respectively. In addition, significant improvement in carrier homogeneity and reduction in extrinsic doping in graphene on BN has been observed. An average Dirac point of 3.5 V and residual carrier concentration of 7.65 × 1011 cm−2 was observed for graphene transferred on 5 nm BN at ambient condition. The overall performance improvement on PLD BN can be attributed to dielectric screening of charged impurities, similar crystal structure and phonon modes, and reduced substrate induced doping.

Graphene has been subjected to extensive research efforts due to its distinctive properties such as atomically thin structure,1 superior carrier mobility,2 electrically,3 and chemically4,5 tunable work function, and possibility of heterostructure formation with other semiconducting materials as demonstrated recently through formation of vertical6,7 and in-plane heterojunction devices with other two-dimensional (2D) materials.8–10 Through unique combinations of the aforementioned characteristics, graphene based devices are poised to attain functionalities that are not achievable using conventional semiconductors. Especially, the atomically thin nature leads to the confinement of electrons in a 2D system which can be manipulated to develop high performance sensors and next generation electronic devices by forming multilayer heterostructures. However, due to confinement of charges in a ∼0.34 nm (Ref. 11) atomically thin surface the charge transport is easily and significantly influenced by the adjacent media. In addition, due to lack of surface dangling bonds, integration of a suitable dielectric with matching properties is a major challenge for graphene based devices.12 Recently, hexagonal boron nitride (h-BN) has emerged as a promising dielectric improving charge transport in graphene devices due to its similar layered-hexagonal crystal structure, only 1.7% lattice mismatch to graphene,13 a wide bandgap of 5.97 eV,14 and a chemically inert surface free from dangling bonds. Additionally, BN offers excellent thermal conductivity15 for efficient heat dissipation, high energy surface optical phonon modes for reduced phonon scattering12,16 coupled with similar dielectric constant (ε ∼ 4.0) and breakdown voltage (Vbr ∼ 0.7 V/nm) as SiO2.17,18 These attractive properties fueled significant interest in utilizing exfoliated h-BN as a dielectric for graphene, which resulted in very significant improvement in its electrical properties.16 

Common methodologies for large scale h-BN synthesis, such as chemical vapor deposition (CVD) on metal catalysts,19–21 and physical vapor deposition (PVD) techniques, such as reactive sputtering followed by annealing,22 require either high growth or high annealing temperature (∼1000 °C),19–21,23 which is unsuitable for flexible electronics and sensors that often utilizes polymer substrates. Recently, pulsed laser deposition (PLD) has emerged as a promising technique to realize BN layers over a large area due to lower growth temperature enabled by plasma enhanced high atomic mobility of precursors on the substrate surface. Large area stoichiometric synthesis of h-BN at lower temperature (700 °C) on lattice matched graphite, as well as amorphous BN (a-BN) with very high aspect ratio (equivalent to that of crystalline 2D films, i.e., >106 length/thickness) on non-lattice matched sapphire has already been demonstrated using this technique.24,25 In this report, we have investigated the potential of BN, grown by PLD on non-lattice matched SiO2/Si substrate, as a suitable dielectric layer to enhance the electronic properties of graphene. To this end, a systematic study has been performed involving detailed electrical characterization on back-gated field effect transistors (FETs) fabricated using CVD graphene transferred on 5 nm thick BN, which was grown on the SiO2/Si substrate by PLD and annealed in forming gas prior to graphene transfer. We found that annealed PLD BN layer significantly improved carrier mobility in graphene, while reducing carrier inhomogeneity and extrinsic doping compared to graphene transferred on the SiO2/Si substrate.

Graphene was synthesized using CVD method on Cu foil with methane as the precursor gas along with hydrogen, and argon as the carrier gas following an optimized growth process.26 Details of continuous a-BN thin film growth process using PLD has been reported elsewhere.25 5 nm of as grown BN at 200 °C was chosen to evaluate its performance as an ultrathin dielectric layer for graphene. Since PLD grown BN is amorphous in nature, it is likely to have much higher defect density compared to completely inert surface of exfoliated h-BN. Therefore, to reduce the dangling bond density, as-grown BN was annealed at 400 °C for 2 h in forming gas, H2/Ar (200/800 sccm) following recent report on successful phase transformation of a-BN to h-BN by low temperature annealing.27 To study the electrical transport properties, CVD grown graphene on Cu foil was transferred on the annealed BN samples employing widely used PMMA assisted wet transfer method.28 After transfer, the samples were annealed again in forming gas (H2/Ar: 200/800 sccm) for 2 h at 400 °C and at 100 mTorr base pressure to remove the polymer residue and for better adhesion of graphene with the substrate.29 Next, graphene was patterned by photolithography and O2 plasma etch in a reactive ion etch chamber. Finally, Ti/Au (10/80 nm) metallization was done employing the sequential steps of photolithographic patterning, electron beam metal deposition, and subsequent lift-off in resist remover. Highly doped Si (ρ ∼ 0.008 Ω cm) substrate was used to form the back gate for the graphene FET. The structural and morphological properties of the BN films were examined through atomic force microscopy in tapping mode (AFM, Veeco 3100) and Raman spectroscopy (LabRAM Horiba 1B, 632 nm Laser).

Fig. 1(a) shows an AFM morphological image taken on a 5 nm thick BN layer grown on a SiO2/Si substrate and annealed in forming gas. The sample appears to be polycrystalline consisting of grains with diameter varying from 20 to 40 nm, and an rms roughness of 1.9 nm. Fig. 1(b) shows the representative Raman spectra of graphene on BN taken on fabricated devices, which exhibits partial overlap between the graphene D and BN E2g shear mode peaks. Similar spectra have been observed by Nayfeh et al.30 for layer by layer transferred CVD graphene on BN. After subtracting the graphene Raman spectrum, a peak ∼1365 cm−1 was extracted, which corresponds to E2g vibrational mode, a characteristic signature of h-BN. On the other hand, no Raman signal was observed from the as-grown BN on SiO2/Si substrate, which indicates that the as grown BN is amorphous, and phase transformation from a-BN to nanocrystalline h-BN occurred due to annealing at 400 °C. SEM image of graphene on BN [Fig. 1(c)] also clearly shows BN grains covered by graphene. It has been recently reported that annealing free-standing amorphous BN for 30 min at 600 °C transforms it into crystallites with average domain size of 100 nm,27 which is in agreement with our observation of the phase transformation in BN.

FIG. 1.

(a) AFM topographical image of annealed BN showing grains with diameter varying from 20 to 40 nm, (b) Raman spectra of graphene/BN (red) showing overlap of BN E2g shear mode peak and graphene D peak while blue curve is for BN showing the E2g peak, and (c) SEM image of graphene/BN showing BN grains.

FIG. 1.

(a) AFM topographical image of annealed BN showing grains with diameter varying from 20 to 40 nm, (b) Raman spectra of graphene/BN (red) showing overlap of BN E2g shear mode peak and graphene D peak while blue curve is for BN showing the E2g peak, and (c) SEM image of graphene/BN showing BN grains.

Close modal

Fig. 2(a) shows a schematic diagram of the back gated graphene/BN FET used for our measurements. In addition to FETs, transmission line method (TLM) patterns were also fabricated on the same chip to characterize metal-graphene contacts on the BN substrate. Best fit to the measured resistance values averaging over several TLM patterns for different contact pad spacing is shown in Fig. 2(b). The specific contact resistivity and sheet resistance values extracted from the plot in Fig. 2(b) are 3.5 × 10−5 Ω cm−2 and 1903 Ω/□, respectively. The specific contact resistivity is similar to that of graphene on the SiO2/Si substrate, and overall characteristic resistance values are close to that of reported in the literature for CVD31 and epitaxial32 graphene.

FIG. 2.

(a) Graphene FET device schematic on 5 nm BN/SiO2/Si. (b) TLM characterization plot of graphene on 5 nm BN/SiO2. (c) Comparison of graphene transfer characteristics on BN and SiO2/Si fabricated from same growth run, and (d) family ID-VDS plots for graphene on 5 nm BN/SiO2/Si substrate indicating switch in channel carrier type in the voltage range of 0–10 V.

FIG. 2.

(a) Graphene FET device schematic on 5 nm BN/SiO2/Si. (b) TLM characterization plot of graphene on 5 nm BN/SiO2. (c) Comparison of graphene transfer characteristics on BN and SiO2/Si fabricated from same growth run, and (d) family ID-VDS plots for graphene on 5 nm BN/SiO2/Si substrate indicating switch in channel carrier type in the voltage range of 0–10 V.

Close modal

To compare their performances, back-gated FET devices were fabricated on SiO2 (300 nm)/Si as well as BN (5 nm) coated SiO2 (300 nm)/Si substrates using graphene transferred from the same Cu foil used for CVD growth. Representative back-gated transfer characteristics for graphene on SiO2 and BN are shown together in Fig. 2(c). The minimum conductance point or Dirac point for graphene FETs on SiO2 is not clearly observed, but can be estimated to be >60 V which shifted to ∼3.5 V on 5 nm BN, even at ambient condition. Fig. 2(d) shows representative Id–Vd characteristics for five different back gate biases, where current can be seen to decrease as the gate bias increases from a large negative value to 0.0 V, and increase again with further increase in gate bias to 10.0 V, confirming the Dirac point position between 0 and 10.0 V. The significant decrease in the Dirac point from a large positive value towards 0 V signifies the reduction of extrinsic impurity induced doping and charge inhomogeneity in graphene. In addition to the huge Dirac point shift, significant improvement in carrier mobility is also observed. Field effect mobility values were extracted from the relationship, μFET=gmL/WCoxVDS using the left and right side branch of the transfer characteristics for holes and electrons [in Fig. 2(c)], respectively. Here, gm is the transconductance, Cox is the oxide capacitance, L and W are the graphene channel length and width, respectively. From the transfer characteristics of graphene devices on SiO2, the hole mobility is extracted as 1410 cm2/V s, which is typically observed for graphene devices on the SiO2/Si substrate.33 The hole mobility extracted for graphene on BN is 2854 cm2/V s which clearly indicates a 2 fold improvement. The corresponding carrier concentration values determined from the relation p,n = GL/Wqμ (G is the conductance) were 4.44 × 1012 and 6.07 × 1011 cm−2, respectively.

To verify that the observed trend of increased mobility and decreased background carrier concentration (for graphene on BN) are generally valid, graphene hole mobility and corresponding carrier concentration, on the SiO2 and BN substrates for more than thirty devices were determined, and plotted in Fig. 3(a). We observe very clear segregation of data points (corresponding to mobility and carrier concentration values) for graphene on SiO2 and BN clearly highlighting the improved electrical characteristics. The average hole mobility for graphene on BN exhibits more than 2 fold enhancement compared to graphene on the SiO2 substrate (changing from 830 to 1955 cm2/V s) at ambient condition, while the median hole mobility increases from 800 to 1810 cm2/V s. On the other hand, the maximum hole mobility in graphene on BN (5 nm) was found to be 3 times higher, i.e., 4980 cm2/V s compared to the maximum mobility of 1410 cm2/V s observed on SiO2 substrate. Similar improvements in carrier mobility in ambient condition was also reported for graphene and h-BN grown on Cu by CVD and layer transferred on 300 nm SiO2 substrate.34 Notably, the maximum hole mobility for our devices in ambient conditions is significantly higher than the hole mobility of 3100 cm2/V s previously reported for back gated devices (fabricated from layer transferred CVD graphene and h-BN on 300 nm SiO2/Si substrate) characterized under ambient conditions.35 From Fig. 3(a), average carrier concentration for graphene on SiO2 is determined to be 7.96 × 1012  cm−2, which reduces by more than 8 fold to 9.59 × 1011 cm−2 for graphene on BN, with the median carrier concentration also decreasing 8 fold from 7.31 × 1012 to 9.23 × 1011 cm−2. Simultaneous enhancement in carrier mobility and reduction in carrier concentration for graphene on BN can be attributed to the reduction in charged impurity induced Coulomb scattering, and has been reported previously for graphene grown directly on CVD BN.36 Since the current minima on 5 nm BN sample is close to 0 V, the electron mobility can also be extracted easily from the right side branch, unlike graphene on SiO2 where there is no well-defined right side branch over the range of back-gate voltage used. Extracted electron mobility distribution for thirty five devices are shown in Fig. 3(b) from which the maximum and average electron mobility are determined to be 4200 cm2/V s and 1560 cm2/V s, respectively, while the median electron mobility is 1475 cm2/V s.

FIG. 3.

(a) Comparison of graphene field effect hole mobility and corresponding carrier concentration on 5 nm BN/SiO2 and 300 nm SiO2 substrate for thirty five devices, (b) graphene electron mobility and corresponding carrier concentration statistics on 5 nm BN.

FIG. 3.

(a) Comparison of graphene field effect hole mobility and corresponding carrier concentration on 5 nm BN/SiO2 and 300 nm SiO2 substrate for thirty five devices, (b) graphene electron mobility and corresponding carrier concentration statistics on 5 nm BN.

Close modal

Dirac points and corresponding residual carrier concentrations for thirty five devices on 5 nm BN substrate are plotted in Fig. 4(a). The residual carrier concentrations were determined from the constant mobility (μconst) model described by the following equation:37 

RTotal=2RC+LWqμconst(no2+nind2).
(1)
FIG. 4.

(a) Dirac point and residual carrier concentration distribution of thirty five graphene devices on BN (5 nm)/SiO2/Si substrate, (b) comparison between 5 nm BN/SiO2 and 300 nm SiO2 substrates in terms of graphene Dirac point and residual carrier concentration.

FIG. 4.

(a) Dirac point and residual carrier concentration distribution of thirty five graphene devices on BN (5 nm)/SiO2/Si substrate, (b) comparison between 5 nm BN/SiO2 and 300 nm SiO2 substrates in terms of graphene Dirac point and residual carrier concentration.

Close modal

In Equation (1), RTotal is the total resistance of the device, RC is the contact resistance, n0 is the residual carrier concentration, and nind (=CoxVbg/q) is the carrier concentration induced by the back gate voltage, Vbg. The Dirac point can be seen to range from 0.0 to 5.75 V with an average value of 3.5 V, while the residual concentration varied from 3.3 × 1011 cm−2 to 1.64 × 1012 with an average value of 7.65 × 1011 cm−2. Theoretical intrinsic limit for residual carrier concentration in graphene is 1.6 × 1011 cm−2 (Ref. 38) denoted by the blue dashed horizontal line, which is quite close to the minimum concentration obtained for 5 nm BN of 3.3 × 1011 cm−2. Finally, Fig. 4(b) shows the comparison between BN and SiO2 substrates in terms of graphene residual carrier concentration. For SiO2 substrate, the average value of the extracted residual carrier concentration is 4.42 × 1012  cm−2, which is similar to that reported in the literature.39 Using similar fabrication process steps, the average residual carrier concentration of 7.65 × 1011 cm−2 has been achieved on 5 nm BN/SiO2 (300 nm) which is more than 5 times lower compared to 300 nm SiO2 clearly indicating strong influence of the substrate on the residual carrier concentration. Indeed, formation of hydrophilic silanol (SiOH) on the SiO2 surface40–42 leads to bonding with polar molecules, i.e., water, and is believed to lead to p-type doing in graphene.40,43–45 This increase in carrier concentration and accompanying charged impurities result in enhanced Coulomb scattering. Due to its polar nature, SiO2 surface optical phonon induced scattering is another major scattering mechanism in graphene on SiO2.46 Introduction of BN in between graphene and SiO2 reduces the mentioned effects substantially in addition to the possibility of reducing the 1/f noise significantly as recently demonstrated in exfoliated h-BN/graphene/h-BN heterostructure devices,47 although admittedly BN growth itself is in the very early stage of exploration. We would like to emphasize here that although the BN layer is basically polycrystalline, consisting of nanometer (20–40 nm) sized grains, considerable reduction in extrinsic doping and carrier inhomogeneity in graphene is clearly observed due to reduction in Coulomb scattering and high optical phonon energy of BN. The observed improvement in electrical performance of graphene on low temperature synthesized nanocrystalline BN is highly encouraging, as it can enable utilization of the beneficial effects of BN layer in graphene based flexible electronics where high temperature processing (∼1000 °C) is not possible.

In conclusion, we have demonstrated electrical performance enhancement of back-gated graphene transistors on ultrathin BN grown on the SiO2 substrate by low temperature PLD. Field effect hole mobility showed a 3 fold improvement compared to graphene on SiO2 at ambient condition, with maximum hole and electron mobility measured as 4980 and 4200 cm2/V s, respectively. An average Dirac point of 3.5 V and residual carrier concentration of 7.65 × 1011 cm−2 (reduced from >60 V and 4.42 × 1012 cm−2 for graphene on SiO2, respectively) at ambient extracted over large number of devices, also indicates strong reduction in charge inhomogeneity and extrinsic doping. The improvements in electrical characteristics can be attributed to reduced columbic scattering from charged impurities and higher optical phonon energy of BN. Our results clearly highlight the potential of low temperature grown nanocrystalline h-BN as a suitable dielectric in graphene based high performance sensors and electronics on versatile surfaces including flexible substrates.

Financial supports for this work from National Science Foundation (Grant Nos. ECCS-1500007, ECCS-0846898, and ECCS-1512342) are thankfully acknowledged.

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