Polycrystalline CdTe in 12% efficient solar cells has been studied using scanning microwave impedance microscopy (sMIM). The CdS/CdTe junctions were grown on transparent-conducting-oxide-coated soda lime glass using rf sputter deposition. sMIM based capacitance measurements were performed on the exposed surface of CdCl2 treated CdTe adjacent to thermal-evaporation-deposited Cu/Au back contacts. The sMIM instrument was operated at ∼3 GHz, and capacitance measurements were performed as a function of ac and dc voltage biases applied to the tip, with and without sample illumination. Although dc capacitance measurements are affected by sample topography, the differential capacitance measurement was shown to be topography independent. It was found that the grain boundaries exhibit a depleted carrier concentration as compared to the grain bulk. This depletion effect is enhanced under photo-generated carrier separation or under sufficiently large probe tip biases opposite to the majority carrier charge.

CdTe-based solar cells have demonstrated a record efficiency of 21.5%,1 making them very promising candidates in photovoltaic (PV) applications. The highest efficiency devices use polycrystalline CdTe as the active absorber layer. In polycrystalline PV materials, two-dimensional grain boundaries may lead to deterioration of the electrical properties via (a) recombination of photo-generated carriers and hence reduction of the energy conversion efficiency, and (b) localized grain boundary states in the energy bands that lead to charge trapping and obstruction of carrier transport.2 Despite this, polycrystalline CdTe solar cells outperform their single crystal counterparts.3 There have been several investigations of the electrical properties of the grain boundaries in CdTe.3–7 These studies suggest that grain boundaries can provide an electrically active, low resistance conduction channel to the front contact.4 In addition, it is asserted that the segregation of Cl at grain boundaries results in local doping type inversion, resulting in p-doped CdTe grains separated by n-doped grain boundaries.3,7,8 The Cl is introduced in the device by annealing under CdCl2 vapor, which is found to aid recrystallization, increase open-circuit voltage, and increase the grain size of the CdTe.9 

Probing the properties of individual grain boundaries is difficult as most device characterization techniques measure macroscopic areas and hence yield results that are a convolution of the electrical properties of the grain bulk and grain boundaries. Individual grain boundary properties have been investigated via electron beam induced current;5,7,10 scanning capacitance microscopy (SCM), conductive atomic force microscopy (C-AFM), and scanning kelvin probe force microscopy;3,11 near-field optical beam induced current;12 and scanning spreading resistance microscopy.13 These studies showed that the grain boundaries in CdTe are electrically active and provide efficient conduction pathways for electrons. Only SCM is capable of determining the carrier concentrations and type but only a few SCM-based studies have been reported focusing on the grain boundaries in CdTe.3,11 Thus, the electronic properties of grain boundaries in polycrystalline-CdTe and their role in photo-generated charge separation remain topics of wide debate. In addition, all of the above studies have been carried out on CdTe cells grown by closed-space sublimation (CSS). Hence, the role of grain boundaries in CdTe deposited by other methods such as sputter deposition remains unclear. Here, we report electrical characterization of individual grain boundaries in PV-device-quality polycrystalline CdTe deposited via rf sputtering. This was accomplished using scanning microwave impedance microscopy (sMIM), which is a scanning probe technique that enables high-resolution nanoscale spatial mapping of carrier concentration and type and has a number of advantages over SCM.

The CdTe device samples studied here were grown at the University of Toledo on NSG-Pilkington TEC-15 glass substrates coated with a high resistivity SnO2 transparent layer. TEC-15 is a standard soda lime glass coated with a tri-layer of SnO2/SiO2/SnO2:F. CdS and CdTe were sequentially deposited on these substrates by magnetron sputtering at a substrate temperature of 250 °C, an rf power of 200 W, and an Ar pressure of 15/10 mTorr for CdS/CdTe depositions, respectively. The CdS and CdTe thicknesses are 120 nm and 2200 nm, respectively, as monitored in-situ using real time spectroscopic ellipsometry. Following deposition, the samples were CdCl2 heat treated by applying a saturated aqueous solution of CdCl2 to the CdTe film surfaces and annealing in dry air for 30 min at 387 °C. The samples were patterned into 1 cm × 1 cm devices and contacted by 4 mm diameter circular Cu/Au bilayer dots of 3/30 nm thicknesses, followed by subsequent annealing at 150 °C in air for 45 min. This left some of the CdCl2 treated CdTe surface exposed where the sMIM measurements were performed. Additional details of the deposition process may be found in Refs. 14 and 15; however, some growth and device processing parameters were adjusted relative to those in the references, as described above. The devices used for this study exhibited an open circuit voltage of ∼0.8 V, a fill factor of ∼70%, a short circuit current of ∼22 mA/cm2, and an efficiency of ∼12%. For sMIM measurements, a 5 nm thick layer of Al2O3 was grown on the CdTe surface using atomic layer deposition to enhance the capacitance signals.

sMIM, a high-resolution cantilever-based scanning-probe technique, is a versatile variant of an array of recently developed near-field reflective microwave imaging technologies.16–19 It offers the ability to spatially map material permittivity and conductance with high sensitivities and signal-to-noise ratios at resolutions mostly limited by the tip size.20–22 sMIM is based on the reflection of electromagnetic radiation in the microwave wavelength regime at the interface of two materials, which offers insights into the electronic properties of materials.23,24 The high spatial resolution (≈50 nm) is provided due to near-field reflectivity imaging achieved by a high performance transmission line fabricated using a specialized AFM tip with a shielded cantilever probe.25 In the current experiments, a low power rf signal at ∼3 GHz interacts with the sample, resulting in changes in reflection and absorption of the rf power. The reflected signal consists of an in-phase and out-of phase component, which contains information about the local permittivity (capacitance) and conductivity (resistance) of the sample. After proper calibration, using a purely capacitive (dielectric) sample made of Al2O3 dots on top of SiO2/Si, the capacitive and resistive channels are isolated, mapped spatially, and displayed independently. Further details of the microwave electronics, tuning, and calibration procedures can be found in Refs. 20 and 22. sMIM measurements here were performed in an Asylum Research MFP-3D AFM using commercially available cantilevers from PrimeNano, Inc.

In order to separate out the effects of local carrier concentration and sample topography, we performed high frequency differential capacitance (dC/dV) scans as a function of tip voltage and sample illumination. For these measurements, both contacts of the sample were electrically grounded and a dc bias and/or a 20 kHz ac bias were applied to the tip. These measurements were performed in contact mode, with the conductive sMIM tip and the oxide coated sample effectively forming a metal-insulator-semiconductor (MIS) structure. The capacitance change caused by the ac bias was measured using a lock-in amplifier. Figure 1 shows a schematic of the experimental setup and the tip signal used to perform the measurements. The measured capacitance comprises of the capacitances of the oxide and the semiconductor space charge layer connected in series. Since the frequency of the capacitance probe signal is ∼3 GHz, we obtain the high frequency capacitance-voltage (C-V) behavior of the MIS structure in the sMIM capacitance (sMIM-C) channel.26,27 In this regime, for a p-type semiconductor and sufficiently large positive dc tip bias, the sMIM-C channel measures a lower capacitance value because of carrier depletion in the semiconductor induced by the dc bias. Under a negative tip bias, hole accumulation occurs and sMIM-C channel measures a higher capacitance. For the capacitance behavior of an n-type semiconductor MIS structure under a voltage bias, the trends are reversed. For only a dc bias (Vdc) applied to the tip, the capacitance response of the sample at Vdc is probed. Hence, by performing multiple scans while changing Vdc for each scan, we can acquire a C-V map of the sample area being scanned. For a combination of dc and ac bias applied to the tip and a lock-in measurement to the ac bias frequency, we probe the differential capacitance (dC/dV) signal, i.e., the slope of C-V curve at Vdc. The magnitude of change in depletion capacitance resulting from a given change in tip voltage, due to the time varying ac bias, is a function of the carrier concentration of the semiconductor. Hence, we can measure the relative carrier concentration and type by spatially mapping the dC/dV amplitude and phase signal, respectively.27,28 In this configuration, our measurement is similar to open loop SCM imaging, but in SCM the bias is conventionally applied to the sample as opposed to the tip, as in our study. The shielded cantilever probe design used in sMIM greatly reduces parasitic tip-sample coupling that leads to environmental noise pickup,20 hence yielding superior results to SCM.

FIG. 1.

(a) Tip signal consisting of 3 GHz microwave signal superimposed over 20 kHz ac and dc biases, used for probing the electrical properties of the sample (signal frequencies not to scale) (b) Schematic of sMIM setup and electronics used for making measurements in this paper.

FIG. 1.

(a) Tip signal consisting of 3 GHz microwave signal superimposed over 20 kHz ac and dc biases, used for probing the electrical properties of the sample (signal frequencies not to scale) (b) Schematic of sMIM setup and electronics used for making measurements in this paper.

Close modal

Figure 2 shows the simultaneously obtained deflection (derivative of topography) and the sMIM-C channel images of the CdTe surface near the back contact. The probe tip and both the front and back contacts of the sample were electrically grounded for this measurement. The data indicate that the areas of the CdTe surface that correspond to the grain boundaries exhibit higher capacitance than the corresponding grains. This could suggest a higher carrier concentration along grain boundaries as compared to grain bulk as per Refs. 29 and 30. The higher capacitance signal at grain boundaries was reproducible even at other values of Vdc, when the tip was not electrically grounded. This increased capacitance is also observed at all topographical minima for ion-polished CdTe samples, where the depressions in topography are not necessarily located at the positions of grain boundaries. Thus, the higher capacitance at the grain boundaries must be an artifact induced due to local depressions in topography, where the contact area between the tip and sample increases, and is not related to the electronic properties of the grain boundaries. Therefore, we used a different approach to measure the true electronic properties of the grain boundaries.

FIG. 2.

(a) Deflection (derivative of topography) image and (b) corresponding capacitance image for an sMIM scan. For this measurement, the tip and the sample were both electrically grounded. The sample's rms roughness is 22 nm. Sample grain (G) and grain boundary (GB) positions have been marked. Scale bar is 400 nm.

FIG. 2.

(a) Deflection (derivative of topography) image and (b) corresponding capacitance image for an sMIM scan. For this measurement, the tip and the sample were both electrically grounded. The sample's rms roughness is 22 nm. Sample grain (G) and grain boundary (GB) positions have been marked. Scale bar is 400 nm.

Close modal

It was found that in dC/dV measurements the topographical artifacts do not overshadow the electronic properties of the grain boundaries. Fig. 3(a) shows the simultaneously acquired dC/dV amplitude (|dC/dV|) signal overlaid on the AFM topography. The image was acquired with −2 V dc bias and a 1 V ac amplitude bias at 20 kHz applied to the tip (applied ac and dc voltages thus sweeping from −1 to −3 V) and a lock-in was used to measure the dC/dV signal. The AFM system was in a lightproof enclosure such that there was no external light source apart from the AFM tracking laser illuminating the sample. The AFM tracking laser wavelength is 850 nm (1.46 eV), which is slightly lower in energy than the band gap of CdTe (1.48 eV),31 thus no appreciable amount of photo-carriers were generated by that laser. It is seen from Fig. 3(a) that several areas corresponding to the grain boundaries have much higher |dC/dV| signal than the grain bulk. Higher |dC/dV| signal corresponds to a steeper C-V curve, which is a result of lower local carrier concentration.27 Hence, Fig. 3(a) shows that the grain boundaries in CdTe exhibit a lower carrier concentration than the grain bulk. Further, the corresponding dC/dV phase image exhibited a phase variation of at most 29° across the image, which is much less than a phase flip of ∼180° observed in the case of a p-type vs. an n-type semiconductor. This indicates that the grain boundaries are depleted p-type, relative to the p-type grain interiors, rather than inverted (n-type). The topographical invariant nature of this measurement is revealed by Fig. 3(b), where it is seen that the |dC/dV| signal from the same area is washed out when the tip dc bias is changed to +2 V, keeping all other experimental parameters the same. This confirms that the |dC/dV| signal is not a topographical artifact. We note that the exact nature of the electronic properties of the grain boundaries is dependent on the growth process (CSS vs. sputtering) and the nature of CdCl2 annealing, which together determine the amount of Cl incorporated in the material.

FIG. 3.

|dC/dV| signal obtained with (a) −2 V and (b) +2 V dc and 1 V ac bias superposed on top of AFM topography. All scans are 5 μm × 5 μm in area. rms roughness of the region is 22 nm. The contrast in the |dC/dV| signal is washed out by changing the dc bias from −2 V to +2 V. Note: There is a lateral shift in image (a) and (b) due to sample drift in AFM. Corresponding grains (G) and grain boundaries (GB) are marked in both images.

FIG. 3.

|dC/dV| signal obtained with (a) −2 V and (b) +2 V dc and 1 V ac bias superposed on top of AFM topography. All scans are 5 μm × 5 μm in area. rms roughness of the region is 22 nm. The contrast in the |dC/dV| signal is washed out by changing the dc bias from −2 V to +2 V. Note: There is a lateral shift in image (a) and (b) due to sample drift in AFM. Corresponding grains (G) and grain boundaries (GB) are marked in both images.

Close modal

Grain boundary depletion has been suggested as the reason for the high efficiency of polycrystalline CdTe solar cells.3 Li et al.7 demonstrated that the Cl segregates along grain boundaries in polycrystalline CdTe and calculated (using Density Functional Theory) that Cl dopes the grain boundaries n-type and results in band bending along grain boundary-grain interface. This facilitates the separation of photo-generated charge carriers such that electrons move to grain boundaries and holes stay in the grain bulk. Further, the grain boundaries provide a low resistance path for electrons to travel to the front contact.4 This indicates that it is better for CdTe devices to have large columnar grains with grain boundaries running throughout the thickness of the CdTe layer such that the photocurrent does not cross grain boundaries to reach a contact.

Fig. 4(a) shows the |dC/dV| image of an area of the sample, obtained using a 2 V ac amplitude bias (to obtain higher signal to noise ratio) at 20 kHz, with no dc bias or sample illumination. A different area was used here in order to isolate the effects of dc voltage bias from light bias in the event that there was residual trapped charge as a result of the dc bias experiments performed previously. Fig. 4(b) shows the |dC/dV| image of the same area with sample illumination using the built-in AFM optical microscope light. Upon comparison of the |dC/dV| signals between Figs. 4(a) and 4(b), we see that when the sample is illuminated with light, the regions around some of the grain boundaries become brighter and the grains become slightly darker. This is evident from Fig. 4(c), which is a result of subtraction of Fig. 4(a) from Fig. 4(b). In Fig. 4(c), some of the grain boundaries exhibit a higher and grains exhibit a lower |dC/dV| signal. The dC/dV phase images, both with and without sample illumination, exhibited no observable features along grain boundaries with a maximum phase variation of 17° across the image. This suggests that upon illumination the carrier depletion around the grain boundaries increases (less p-type) as a result of collection of photogenerated electrons, while the bulk grains become slightly more p-type as a result of photogenerated hole accumulation. In future experiments, we plan to make a systematic study of this behavior with a better-defined light source of known intensity and wavelength. For the purposes of this study, we simply note that we can observe photo-carrier separation directly between the grains and grain boundaries.

FIG. 4.

|dC/dV| with 2 V ac bias with (a) no sample illumination (b) sample illumination with AFM optical microscope light. Notice the enhanced depletion around grain boundaries when sample is illuminated, as seen by the brighter signals along grain boundaries in (b). All scale bars are 500 nm. Color bar is common for (a) and (b). (c) is a result of subtraction of (a) from (b). Inset: Deflection (derivative of topography) image for the associated area. rms roughness: 24 nm.

FIG. 4.

|dC/dV| with 2 V ac bias with (a) no sample illumination (b) sample illumination with AFM optical microscope light. Notice the enhanced depletion around grain boundaries when sample is illuminated, as seen by the brighter signals along grain boundaries in (b). All scale bars are 500 nm. Color bar is common for (a) and (b). (c) is a result of subtraction of (a) from (b). Inset: Deflection (derivative of topography) image for the associated area. rms roughness: 24 nm.

Close modal

It is also evident from Figures 3 and 4 that not all grain boundaries show similar brightness in |dC/dV| images. This suggests that not all grain boundaries are depleted by equal amounts and hence do not share common electrical properties. Similarly, neither do all grains share the same |dC/dV| signal, suggesting that there is a variation of carrier concentration from one grain to another. Further, there is a gradual decrease in the carrier concentration from the center of the grain to the areas near the grain boundaries. These effects are best observed in Figure 4. This suggests that grains of a certain crystallographic orientation/size and the associated grain boundaries are more electrically active than others. If the interpretation of grain boundaries as channels for conduction of electrons to the front contact is correct then grain boundaries that show less depletion may also be poor electron conduction channels. Future studies may clarify this and should try to determine if it limits the overall device performance. Likewise, the smaller change in signal in individual grains may indicate weaker photo-generated carrier concentrations in those grains, again potentially resulting in poorer device performance.

In conclusion, we have shown that even though the topography dominates the sMIM capacitance measurements on the surface of polycrystalline CdTe, we can still employ dC/dV measurements to determine the electronic properties and associated relative carrier density at grain boundaries with respect to the grain bulk. We found evidence of a depletion region existing around the grain boundaries and hence we confirm the hypothesis of grain boundary depletion, likely caused by Cl segregation there. This creates band bending along grain-grain boundary interface, which facilitates photo-generated carrier separation. We have directly observed this separation by observation of the relative carrier concentrations with and without light exposure on the sample. Also, there is evidence that the crystallographic orientation/size of grains affects the electronic properties of the surrounding grain boundaries and their role in carrier separation. Further studies are required to ascertain the crystal orientation/size of grains that facilitate PV action in polycrystalline CdTe.

The authors are thankful for the financial support from the U.S. Department of Energy, Office of Energy Efficiency and Renewable Energy (Contract No. DE-EE0005405). The authors are also grateful to Dr. David Strickler of NSG-Pilkington for supplying the TEC-15/HRT substrate materials. This work was carried out in part in the Frederick Seitz Materials Research Laboratory Central Research Facilities, University of Illinois.

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