Multi-layered nanocomposite dielectrics for high density organic memory devices

Organic memory devices have been of great interests due to their simple structure, light weight, flexibility, and large-area and low-cost processability.^1–5 Nano-floating gate memory is one of the representative organic memory devices which use nanocrystals (e.g., gold nanoparticles; Au NPs) embedded in a transistor dielectric layer as a charge-trapping element.^5–12 In this device, transconductance of semiconductor channel is controlled by stored charge carriers in the nanocrystals via application of external gate field. Charge trapping can be manipulated by metal species, size, and spatial density of the NPs. To this end, there has been extensive research on metal nano-floating gates by adjusting species, size, and distribution of NPs in dielectric layers in order to obtain high performance memory devices.^13–16 Au NPs are typically used as charge trapping sites deposited via sputtering⁵ or solution process^15–17 which induced reproducible and reliable threshold voltage (V_th) shift both in positive and negative direction depending on the polarity of charge carriers. Spatially distributed large size copper NPs showed very long charge retention time approaching 10 years.¹⁸ Although there has been a remarkable progress in organic memory devices based on metal NPs, it should be further improved to be available in commercial products in terms of memory capacity, retention time, reliability, and low-cost processability.

Here, we report on an organic flash memory element with high memory capacity by using multi-stacked block copolymer (BCP) dielectrics. Block copolymers which contain both hydrophilic and hydrophobic blocks in a chain can simply form specific nanostructures (e.g., sphere, lamellar, or cylindrical morphology) via self-assembly as a function of volume fraction of each block.¹⁷ Using this property, Au NPs can only be localized within one phase of the BCP matrix due to the attractive interaction between the Au NPs and a BCP phase. The size and density of Au NPs can be controlled by varying the volume fraction of each block or the loading ratio of the Au NP precursors.¹⁹ Nanostructured BCP matrix prevents the aggregation of Au NPs in the dielectric, so that it affords a high degree of Au NPs arrangement and induces spatial confinement of trapped charges.^20–22 Furthermore, multi-stacked BCP-based dielectric layers with 3D patterned Au NPs were achieved by employing photo-crosslinking layer between each BCP layers. The vertically stacked Au NPs could remarkably increase the number of charge carriers per unit area stored in metallic nano-floating-gates, resulting in large memory window for multi-level memory.^22,23

Fig. 1 shows a schematic of organic memory devices. The organic memory with double layers of Au NPs (D-OM) was fabricated on a p⁺⁺ Si (for a control gate electrode) wafer with thermally grown 100 nm thick SiO₂ layer (as a charge blocking dielectric). Substrates (2.0 cm × 2.0 cm) were cleaned by bath sonication sequentially in acetone (10 min) and isopropyl alcohol (10 min), followed by O₂ plasma for 1 min. A solution of polystyrene-block-poly-2-vinylpridine (PS-b-P2VP) (0.5 wt. %; PS₅₀-b-P2VP_16.5, Polymer Source) in toluene was spin-coated onto the substrate at 2000 rpm. Next, the substrate was immersed in aqueous solution of 1:1 HAuCl₄/HCl mixture (0.01 M for each) for 20 min to pattern Au salt on the BCP surface. After metal salt deposition, the substrate was washed with DI water to remove loosely bound salts from the BCP surface. Then, the substrate was dipped into freshly prepared aqueous solution of NaBH₄ (3.75 mg/mL) for 30 s to reduce HAuCl₄ to Au NPs (HAuCl₄ + 4 NaBH₄ + 12 H₂O → Au + 4 B(OH)₃ + 4 NaCl + 29 H⁺). Fig. 2(a) shows the scanning electron microscopy (SEM) image of well-patterned Au NPs on the BCP layer. The size and spatial density of the Au NPs were calculated to be around 12 nm and 7.5–8.2 × 10¹⁰cm⁻², respectively. After forming the first nanocomposite layer, photo-crosslinker (4,4′-diazido-2,2′-stilbene disulfonic acid disodium salt tetrahydrate, Aldrich) in ethanol solution (1 wt. %) was dropped onto the substrate, kept for 3 min, and then spin-coated at 6000 rpm for 30 s. The photo-crosslinking was performed under ultraviolet (UV) light (λ = 254 nm) irradiation for 10 min. Second BCP layer was formed onto the first layer following the same procedure as described above. The spatial density of Au NPs on the second layer (2.4–4.4 × 10¹⁰cm⁻², see Fig. 2(b)) was slightly lower than that of the first layer but had a similar NP size. Thereafter, a PS (M_w = 280 000 g/mol, Aldrich) charge tunneling layer was deposited onto the multi-stacked charge storage layers by spin-coating (3 mg/ml in toluene, 5000 rpm) to ensure smooth surface roughness which is favorable for a highly ordered semiconductor deposition as well as to prevent from undesirable trapping of mobile holes at the interface.^23–26 The root-mean-square roughness of the resulting surface was 1.3–2.2 nm. Each layer (BCP, photocrosslinker, and PS layer) was annealed in vacuum oven at 40 °C for over 12 h. Pentacene layer was deposited by thermal evaporation (40 nm thickness, 0.04 nm/s deposition rate). The Au source/drain electrodes were finally defined by using metal shadow mask with channel length (L) and width (W) of 100 and 2000 μm, respectively. The memory device characteristics were measured using Keithley 4200-SCS in ambient air.

Fig. 3 shows the transfer characteristics (drain current I_DS vs gate voltage V_G) of organic memory devices with various dielectrics; (i) double layers of Au NPs (denoted as D-OM), (ii) a single layer of Au NPs (S-OM), and (iii) without Au NPs (N-OM), and obtained device parameters are summarized in Table I. The charge storage properties of the Au NPs were verified via dual sweeps of V_G from +20 to −40 V and reversed from −40 V to +20 V at a gate voltage sweep rate of 2 V/s with constant drain voltage (V_DS) of −60 V. By application of high negative gate bias, holes from pentacene active channel can transfer through the thin tunneling layer and be trapped at the Au NPs in the dielectrics. As shown in Fig. 3(a), N-OM device exhibited little hysteresis. On the other hand, S-OM and D-OM showed significant counter-clockwise hysteresis with a memory window (defined as the maximum difference of the threshold voltage shift (ΔV_th) in the bi-directional V_G sweeps) of 19.1 V and 30.3 V, respectively (see Figs. 3(b) and 3(c)). From the values of memory windows, the amount of stored charges (Q_t) in the dielectric was calculated by employing the equation

where C_i is the total dielectric layer capacitance per unit area and ΔV_th is the memory window. The total stored charges per unit area were 3.63 × 10⁻⁷ C/cm² for S-OM and 5.82 × 10⁻⁷ C/cm² for D-OM, respectively. Hence, the numbers of trapped charge per Au NP were calculated to be 51.6–94.6 for S-OM and 28.8–36.7 for D-OM, respectively.²³ It reveals that the memory windows of organic memory devices were proportional to the spatial density of Au NPs in multi-stacked charge trapping layers. Therefore, memory capacity of organic memory devices could be remarkably increased by vertically stacking of a BCP layer with metal NPs and an insulating layer. Furthermore, as can be seen in Fig. 4, our memory devices have excellent durability, as tested by monitoring the on- and off-state I_DS and ΔV_th at each sweep cycles (up to 100 cycles).

In conclusion, we fabricated organic memory devices with multi-layered nanocomposite dielectrics formed by patterned Au NPs on a BCP layer. When bi-directional V_G sweeps were applied, the organic transistor devices exhibited counter-clockwise hysteresis, indicating that the memory characteristics were originated from hole trapping at the Au NPs. Organic memory devices with double nanocomposite dielectric layers showed a large memory window as well as excellent durability under repeated memory cycles. The bias hysteresis was increased in proportion to the total number of Au NPs in charge trapping dielectrics. Therefore, memory capacity could be significantly increased by vertical stacking of the alternating BCP layer with metal nano-floating-gates and photo-crosslinking dielectric layer. This can be a promising methodology for developing printed and flexible multi-level flash memory with large data storage capacity.

This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (NRF-2014R1A1A1A05002158), and by the Center for Advanced Soft Electronics under the Global Frontier Research Program of the Ministry of Science, ICT & Future Planning, Korea (Code No. 2013M3A6A5073175). K.C. and D.H.K. acknowledge the financial support by Mid-career Researcher Program through NRF grant funded by the MEST (2014R1A2A1A09005656).