Characterizing the effects of free carriers in fully etched, dielectric-clad silicon waveguides

In the ongoing effort to realize low-loss, high-energy efficiency, and high-bandwidth active device components in nanoscale waveguides, one of the most direct ways to control the propagation of a guided mode is through the application of a capacitive bias electric field. In particular, materials such as lithium niobate or electro-optic polymers have been shown to exhibit large second-order nonlinear susceptibilities, making them desirable materials for the realization of on-chip nonlinear devices. More recently, strained silicon has emerged as another candidate for similar applications, despite its comparatively low nonlinear coefficients, due to its CMOS compatibility.^1–7 However, emerging research suggests that the analysis of semiconductor waveguides subjected to a DC electric field may be more complex than originally anticipated.^8,9 In particular, band-bending and consequent redistribution of carriers at silicon-dielectric interfaces are anticipated to change both the real and the imaginary parts of silicon's refractive index. Additionally, large electric fields may be present in such waveguides, even in the absence of an applied bias, due to fixed interface charges in the dielectric films. Although these effects are gradually gaining attention within the framework of integrated photonics, more work still needs to be done to decouple free-carrier effects from other distinct properties of silicon waveguides.

In this manuscript, we theoretically quantify the aforementioned changes in lightly doped p-type silicon waveguides, assuming that they have been clad with either silicon dioxide, silicon nitride, or aluminum oxide. In addition to possessing distinct indices of refraction, each of the considered cladding materials is known to have different densities of (1) fixed charge and (2) interface trap states at interfaces with (100) silicon.¹⁰ Through our analysis, we find that these differences lead to large changes in the concentration of holes and electrons within the waveguide, even in the absence of a bias electric field. The different changes in carrier concentration are then found to have unique and noteworthy impacts on the modes supported by each of the waveguides under consideration. Furthermore, we show that the changes in carrier concentration in these waveguides in response to externally applied bias electric fields are dominant in determining the value of the field within the waveguide. This last point is particularly important to bear in mind in the characterization of active, capacitively driven silicon modulators.

When a semiconductor comes into contact with a dielectric, the semiconductor's valence and conduction band energies may locally deviate from their natural values, leading to perturbations away from the material's bulk carrier concentrations.¹¹ To determine the extent to which this basic effect occurs, two non-idealities to consider are the concentration of fixed charges within the dielectric and the density of interface trap states. Whereas the former may shift the semiconductor's response to an externally applied bias voltage one way or the other, the latter may reduce the magnitude of this response altogether. In a silicon waveguide, any changes in the guiding material's carrier concentrations will produce a change in its optical properties, so it is vital to take these effects into consideration.

To determine the fixed charge present at a semiconductor-dielectric interface, the most common technique is to analyze a capacitance-voltage (C-V) measurement for a MOS structure consisting of the materials of interest. Because the fixed charge itself has a biasing effect on the carriers within the semiconductor, it tends to offset the response of the MOS structure to external voltages. By observing the experimental flat-band voltage of the device and comparing it to the theoretical value, the concentration of fixed charge in the dielectric may be calculated as¹² 

where C_dielectric is the dielectric capacitance per unit area, Δφ_ms is the difference in work function between the metal and the semiconductor (and therefore the flat-band voltage in the absence of any dielectric non-idealities), and V_FB is the measured flat-band voltage. It is important to note that the total fixed charge within the dielectric may change with the applied voltage due to bulk charge traps within the dielectric, potentially leading to hysteresis in the C-V measurement. But because we are only interested in order-of-magnitude analyses of the previously outlined effects of free carriers, and additionally, because we are not considering the application of voltages large enough to induce appreciable hysteresis, we may neglect this complication.

In comparison to fixed charge, interface trap states are not necessarily charged, but rather may become positively or negatively charged in response to any field present at the semiconductor interface. Acceptor-type trap states may take an electron from the semiconductor and thus become negatively charged, and similarly donor-type trap states may give an electron to the semiconductor and become positively charged. The magnitude and sign of interface charge is therefore dependent upon the voltage applied across the MOS structure, as well as the type of interface state present. Because interface states have long response times, their effects will not affect high-frequency capacitance measurements. As a result, at the bias voltage corresponding to the minimum low-frequency capacitance, the interface state density may be calculated as¹³ 

where q is the electron charge, C_LF is the low-frequency capacitance per unit area of the total MOS structure, and C_HF is the corresponding high-frequency term.

To obtain these values for silicon dioxide and silicon nitride, we fabricated two MOS structures, one consisting of each material. Using an Oxford Plasma-Enhanced Chemical Vapor Depositor (PECVD), we deposited 150 nm of silicon dioxide and 180 nm of silicon nitride, respectively, on two silicon wafers doped with boron at a concentration of 1e15 cm⁻³. PECVD was the chosen deposition technique both because of its prevalence in most waveguide fabrication processes and its CMOS compatibility. It should be noted that the target thickness was 150 nm for both dielectric layers, and that the variation exhibited by the silicon nitride layer resulted from fabrication imprecision. Following the deposition, we carried out a rapid thermal anneal (RTA) on both samples at a temperature of 300 °C for 15 min in a forming gas (N₂/H₂: 90%/10%) ambient to reduce the density of interface trap states and improve film quality. Finally, we fabricated 200 nm-thick aluminum contacts on top of the dielectrics via photolithography and electron beam evaporation. It should be noted that annealing processes such as the one employed here are commonly used in the field of strained silicon photonics both to increase the stress within the dielectric and to improve its electrical and optical properties. Once fabrication was complete, we carried out low- and high-frequency C-V measurements using an Agilent B1500A Semiconductor Device Analyzer.¹⁴ The C-V curves, generated by scanning from a negative to positive voltage, are shown for the two materials in Figs. 1(a) and 1(b). For the case of aluminum oxide, as well as the buried silicon dioxide, the values of interest were taken from the literature.¹⁰ Specific properties of the interface traps such as the electron and hole recombination lifetimes were taken from the literature as well.^15,16 The fixed charge and interface state densities for each of the materials under consideration are listed in Table I.

It is important to mention that in the fabrication and characterizaton of MOS structures, the quality of the interface is of paramount importance. If the surface cleaning is not perfect, a lossy dielectric layer will form between the semiconductor surface and the deposited film.¹⁷ One of the more well-known results of this nonideality is a frequency dependent capacitance, specifically in the accumulation region, as is observed in the reported C-V measurements of the silicon nitride film. This, however, impacts neither the determination of fixed nor interface trap charges.¹⁰ 

Based on the obtained experimental and theoretical values, we created two-dimensional models using the semiconductor physics tool Silvaco to determine the concentration of holes and electrons across a 250 nm-tall, 500 nm-wide silicon waveguide clad with each of the aforementioned dielectrics.¹⁸ A cladding thickness of 1 μm was chosen in order to eliminate metallic optical absorption, and a vertical electrode configuration was assumed, because it is a common technique in the characterization of strained silicon and other electro-optic materials.^1,5 By changing the bias voltage applied vertically across the simulation space, we were further able to observe how free carriers affected the electric fields induced within the waveguides. Cross-sectional plots of the electron (minority carrier) concentrations are shown in Figs. 2(a)–2(f) for both the negatively and positively biased cases, and for each of the materials under consideration. Also, Fig. 2(g) shows the geometry assumed in the model. For the waveguides with either silicon dioxide or silicon nitride cladding, the positive fixed interface charges push the silicon into depletion, whereas the negative fixed charge inherent to the aluminum oxide leads to accumulation. Moreover, although the voltages applied across the waveguide lead to changes in carrier concentration, the sign and magnitude of this change are largely governed by the fixed charge density, as will be subsequently discussed in greater detail.

To further consider the interaction between silicon's free carriers and the electric field in the waveguides, we additionally observed the electrostatic behavior of the waveguide clad with silicon nitride. Our results, shown in Fig. 3, highlight the shielding effect provided by the carriers. When applying a bias of 10 V, the average and the peak value of the electric field (plotted along a y-slice at the center of the waveguide in Fig. 3) show minimal changes from their no-bias value, despite the large field values present just beyond the waveguide's boundaries. This illustrates how well free carriers may reduce the interaction of silicon with capacitively applied bias fields.

Following this result, we also investigate the effect of free carriers in silicon on the optical properties of the same set of waveguides. The free-carrier concentrations were translated to spatially dependent deviations away from the unperturbed real and imaginary parts of silicon's index of refraction, given phenomenologically as¹⁹ 

where ΔN_e is the perturbation in the concentration of free electrons and ΔN_h is the corresponding value for holes. We then used the modified values of refractive index with our FDTD solver, the multiphysics software Lumerical, to observe the effect of the carriers on the supported modes of the silicon waveguides.²⁰ Note that this entire analysis was performed assuming an optical wavelength of 1.55 μm. Our results for both the fundamental TE- and TM-like modes are shown in Figs. 4(a)–4(c). It is evident that the changes in the complex effective index due to plasma dispersion are different for each of the three dielectrics. Aluminum oxide, for example, exhibits deviations in the real part of the effective index as large as 2 × 10⁻⁵ for a 10 V bias, whereas the effect is much smaller in waveguides clad with silicon dioxide. It is also interesting to note that, for each effect, the slope of the curve is opposite in sign for the waveguide clad with aluminum oxide, due to the negative value of the cladding's fixed charge.

The net attenuation of the optical mode is dependent not only on the changes in carrier concentration but also on the extent to which the areas of change overlap with the electromagnetic fields of the mode itself. We hypothesize that because the optical mode supported by the waveguide clad with silicon nitride is highly asymmetric as compared to the other cases, the complex relationship between the optical mode and the free carriers is nonlinear in nature, leading to the observed kink in the plots of its parameters.

In conclusion, we have shown that silicon waveguides with dielectric claddings exhibit strong spatial deviations in carrier concentration, even in the absence of capacitively applied bias voltages, and that these changes affect the real and imaginary parts of the effective indices of the guided modes. Additionally, we have shown that the same free-carrier effects impact the waveguides' apparent electro-optic effects in response to driving voltages, both because of the changes in local carrier concentration and because of the effects the carriers have on the electric field ultimately induced across the waveguide. The authors stress that the purpose of this work is to demonstrate a means by which capacitive free-carrier effects may be approximately quantified in silicon waveguides. The changes in effective index shown here are comparable in magnitude to those seen in strained silicon waveguides, but because no optical devices were experimentally characterized, we cannot—at this point—comment on the nonlinear optical properties of strained silicon. In future research efforts, however, we are confident that the characterization method demonstrated here may be explored as a tool for decoupling the nonlinear effects present in such materials. We assert that these free-carrier effects are important to be taken into consideration in the characterization of both active and passive device components based on silicon waveguides.

This work was supported by the Defense Advanced Research Projects Agency (DARPA), the National Science Foundation (NSF), the NSF ERC CIAN, the Office of Naval Research (ONR), the Multidisciplinary University Research Initiative (MURI), and the Cymer Corporation. Sample fabrication was performed at the UCSD Nano3 cleanroom facility.