Barrier reduction via implementation of InGaN interlayer in wafer-bonded current aperture vertical electron transistors consisting of InGaAs channel and N-polar GaN drain

Decades of extensive research and development efforts in heteroepitaxy are accountable for remarkable advances made so far in the state-of-the-art electronic and photonic devices. Examples include high electron mobility transistors (HEMTs),^1,2 heterojunction bipolar transistors (HBTs),³ as well as heterojunction-based lasers,⁴ and light-emitting diodes (LEDs),⁵ where the use of heterojunctions has revolutionized the device performance and efficiency. However, heteroepitaxy offers limited choices in materials, only allowing for realizations of either lattice-matched or pseudomorphic heterostructures.

On the other hand, heterostructures consisting of heteroepitaxy-incompatible materials can be fabricated by direct wafer-bonding, through which strong bonds can be formed, by thermo-compression, between dissimilar yet high-quality materials with clean surfaces.^6,7 It has given birth to numerous successful inventions including silicon-on-insulators (SOI),⁸ AlGaInP/GaP LEDs,⁹ hybrid III-V/silicon lasers,¹⁰ etc. Likewise, direct wafer-bonding has been used to form electrically active heterojunctions, in which carriers flow across the wafer-bonded interface (WBI) from one material to another. For instance, HBTs^11,12 and vertical field effect transistors (FETs)^13–15 have been fabricated based on wafer-bonded heterojunctions of III-As (with excellent carrier injection efficiency) and III-N (with high breakdown field), aiming to obtain both the high-speed and high-power characteristics in a single device.

In order to maximize the benefits offered by III-As/III-N heterojunctions, transistors based on them should be designed such that the carriers injected from the III-As source flow freely through the WBI and are collected in the III-N drain. This arrangement sets two important boundary conditions in their design: (1) a “direct” bonding of the two semiconductors (i.e., without any intermediate material, such as oxide or metal, which may block or redirect the current)⁷ and (2) a vertical topology (i.e., with a very low- or ideally zero-barrier to carrier transport across the WBI).

These two conditions are readily satisfied in the design of current aperture vertical electron transistors (CAVETs).¹⁶ In a III-N-based CAVET depicted in Figure 1(a), the electrons injected from the sources flow through the two-dimensional electron gas (2DEG) formed in the regrown AlGaN/GaN channel and then toward the current aperture region (labeled L_ap in Figure 1(a)), which is defined by fully insulating current-blocking layer (CBL). It is noted that the CBL is typically formed either by ion implantation^16,17 or p-type GaN.¹⁸ The electrons are modulated in the overlap regions (labeled L_go in Figure 1(a)) between the gate metal and CBL underneath, drift vertically through the aperture, and are subsequently collected at the drain contact on n⁺-GaN.

Similarly, a BAVET (wafer-bonded current aperture vertical electron transistor), depicted in Figure 1(b), can be fabricated by wafer-bonding an InGaAs channel material to a III-N drift region template,^13–15 instead of regrowing an AlGaN/GaN channel as for a conventional CAVET. Because (1) the electrons are injected from the InGaAs with superior electron transport properties and (2) the high electric field region is buried in the thick GaN with very high breakdown field, the BAVET design has potential to achieve both the high-speed and high-breakdown characteristics, which are optimal features for power switching applications.

In a BAVET, electrons originating from the InGaAs sources must flow through the WBI (solid red line in Figure 1(b)) in order to reach the GaN drain. Therefore, the WBI can be considered as the most critical region of the device. Both the (1) quality (e.g., low interfacial defect density) and (2) design (e.g., absence of any electron-blocking barrier) of the WBI would play a vital role in determining the device performance. Based on a previously optimized wafer-bonding process, wafer-bonded GaAs/N-polar GaN p-n diodes with well-behaved I-V and C-V characteristics have been demonstrated.¹⁹ Hence, the study presented in this letter focuses on reducing the inherent electron barrier that likely exists at the WBI located in the vertical electron path of InGaAs/GaN BAVETs, while fabricating all devices based on the already optimized wafer-bonding process.

Based on theoretical works involving semiconductor energy band alignments,^20,21 a positive conduction band offset (ΔE_C) of roughly 0.82 eV is predicted at the WBI between In_0.53Ga_0.47As and GaN as illustrated in Figure 2(a). One way to reduce the inherent ΔE_C (i.e., effective electron barrier) is to introduce an In_xGa_1−xN (x > 0) interlayer between In_0.53Ga_0.47As and GaN, as illustrated in Figure 2(b), since the position of the conduction band (E_C) of an In_xGa_1−xN alloy drops with respect to that of GaN with increasing indium content, x,²² with a strong bowing effect especially at low indium contents.²³ Thus, the shape and height of the overall barrier would be strongly dependent on the design parameters of the InGaN interlayer.

In this light, as illustrated in Figures 2(b) and 2(c), wafer-bonding of InGaAs and N-polar GaN with an InGaN interlayer would offer a three-fold benefit: (1) a small reduction in the first barrier at the WBI (ΔE_C,WBI); (2) the absence of the second electron barrier at the InGaN/GaN interface (ΔE_C,III-N) due to its 2DEG that formed naturally to compensate for the positive fixed polar charge; and (3) the steep downward band bending in InGaN, as depicted in Figure 2(c), which allows the barrier to be more “transparent” to tunneling electrons. Taking these design considerations into account, the BAVETs, reported in this letter, are fabricated based on wafer-bonded heterojunctions consisting of InGaAs and N-polar III-N with an InGaN interlayer with varied thicknesses (0 nm–25 nm).

The III-As layers used for this study were grown fully lattice-matched on a semi-insulating (S.I.) (100) InP substrate by molecular beam epitaxy. The layers consisted of 100 nm-thick i-InP buffer, 100 nm-thick InGaAs, 20 nm-thick InP etch-stop layers, 10 nm-thick n⁺-InGaAs cap, 50 nm-thick i-InAlAs gate barrier, and 150 nm-thick n-InGaAs ([Si] = 2 × 10¹⁷cm⁻³) channel layer. The N-polar (⁠$0001¯$⁠) III-N drift region template series was grown on misoriented sapphire substrates by metal organic chemical vapor deposition (MOCVD). The layers consisted of 900 nm-thick S.I. GaN, 200 nm-thick unintentionally doped (UID) GaN, 1.5 μm-thick n⁺-GaN ([Si] = 5 × 10¹⁸cm⁻³), 700 nm-thick UID GaN, 300 nm-thick n-GaN ([Si] = 3 $×$ 10¹⁷cm⁻³), and finally 0 nm-, 5 nm-, 10 nm-, 15 nm-, or 25 nm-thick low indium content (∼5%) n-InGaN ([Si] = 5 × 10¹⁷cm⁻³) to serve as the interlayer at the WBI. All BAVETs were fabricated based on a process flow described in Ref. 14.

The measured output characteristics of BAVETs with an InGaN interlayer of 0 nm-, 5 nm-, 10 nm-, 15 nm-, or 25 nm-thick are shown in Figures 3(a)–3(e), respectively. The gate-overlap length (L_go) of all BAVETs is 2 μm, which is a dimension equivalent to the gate length (L_g) of lateral FETs. The source-current (I_S), along with the drain-current (I_D), has been plotted simultaneously for a better understanding of intrinsic behaviors (such as pinch-off) because of the high gate-drain leakage, where the differences between I_D (grey) and I_S (blue) curves for the same V_GS represent the total gate leakage (I_G) in the device. Parallel investigations on the materials design and processing are underway to reduce the high gate leakage observed in BAVETs.

Figure 3(a) shows the output characteristic of a BAVET without any InGaN interlayer. The current is extremely suppressed such that I_D is only ∼135 mA/mm at V_GS = 0 V and high applied V_DS of 12 V. The overall device conductance is very poor. As comparing it with the rest of the BAVETs, as shown in Figures 3(b)–3(e), it is observed that the implementation of the InGaN interlayer is beneficial to improving the BAVET on-state performance as a transistor, which is in agreement with the effective barrier reduction predicted in the discussion of Figures 2(a)–2(c).

Despite the on-state improvements seen by the addition of the InGaN interlayers, the BAVETs suffer from a non-zero “turn-on voltage,” which is a finite amount V_DS that must be applied to turn on the transistor (labeled in Figure 3(e)). It is noted that such finite turn-on voltages in output characteristics have also been observed in previously reported BAVETs based on InGaAs/Ga-polar III-N^14,24 and in the AlGaAs/GaAs/GaN-based wafer-bonded HBTs.^11,12 Since BAVETs with zero aperture (i.e., fully current-blocking underneath) when biased as a lateral FET (i.e., one of the source contacts biased as drain) do not exhibit any turn-on voltage in their output characteristics (not shown), the observed turn-on voltages are most likely associated with the non-ideal electron transport across the WBI.

Figure 4 plots the BAVET turn-on voltages and I_D values extrapolated at V_DS = 8 V and V_GS = 0 V from Figures 3(a)–3(e) as a function of the InGaN thickness. In the BAVET without any InGaN interlayer, the turn-on voltage is ∼8 V and thus is much greater than the predicted ΔE_C,WBI/q. This implies that the electron transport in this BAVET is impeded either by an extremely large electron barrier and/or strong non-ideal factors such as the formation of interfacial defects or interlayers.^7,12,19 Conversely, BAVETs with finite thicknesses of the InGaN interlayer show much lower resistance (i.e., lower turn-on voltage, higher I_D), with the BAVET with a 10 nm-thick InGaN interlayer exhibiting the lowest overall resistance.

Figure 5 plots the positions of E_C as a function of the distance away from the WBI toward the drain for structures with 0 nm- to 25 nm-thick InGaN interlayers. These band diagrams were simulated by a one-dimensional Poisson-Schrödinger solver with built-in polarization.²⁵ The calculated conduction band pinning positions of 0.7 eV and 0.82 eV above the Fermi-level (E_F) were applied for the InGaN with 5% indium content and for the GaN, respectively.^20–22 The simulated results show that the effective barrier encountered by the electrons entering from the InGaAs channel varies significantly by the thickness of InGaN interlayer. In the structure without any InGaN interlayer (grey line + circles in Figure 5), the effective barrier to electrons is much larger than in the structures with an InGaN interlayer. Since the indium content is the same in all of the InGaN layers, the magnitudes of the fixed polar charge at the InGaN/GaN interface must be identical. However, for a 5 nm-thick InGaN (orange line + squares), the interlayer is not thick enough to fully induce a 2DEG at the InGaN/GaN interface, therefore causing a “secondary” barrier to arise for the electrons entering from the InGaAs channel. It is clear from Figure 5 that a 10 nm-thick InGaN interlayer (magenta line + triangles) yields the smallest effective tunneling barrier to the electrons. Once the InGaN interlayer thickness is greater than the minimum thickness required to induce a full 2DEG, the tunneling probability for electrons only decreases with increasing thickness, thus resulting in a larger resistance.

The main attributes of the simulated conduction band diagrams in Figure 5 are well aligned with the experimental observations summarized in Figure 4. This suggests that the energy bands of the N-polar InGaN interlayer bend downward beyond the WBI, which cause the barrier to become thinner and more transparent to the tunneling electrons, hence resulting in a reduced resistance in BAVETs. It is also reasonable to postulate thermionic-field emission across the WBI as the main carrier transport mechanism.

By reducing the inherent barrier to electrons via the implementation of the InGaN interlayer, fully functional wafer-bonded vertical transistors consisting of an InGaAs channel and GaN drain are demonstrated, exhibiting I_D of nearly 600 mA/mm at V_GS = 0 V and L_go = 2 μm. The results show that the carrier transport properties in wafer-bonded devices are tunable based on theoretical predictions, which also implies that the impact of non-idealities likely existing at the WBI can be managed. In conclusion, this study proves the validity in pursuing direct wafer-bonding for fabricating heterojunction devices that require active carrier transport across the two materials and thus show promise in further expanding the design space currently limited by heteroepitaxy.

The authors gratefully acknowledge the support from Dr. J. Hwang and Dr. K. Goretta under the Terahertz Electronics Program of the Air Force Office of Scientific Research (Grant No.: FA9550-10-1-0069).