We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increase in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.

The ultimate end of CMOS scaling was predicted almost immediately after the now ubiquitous technology was invented by Frank Wanlass^{1} in 1963. Indeed, many possible limitations to downscaling were discussed in the 1970s, 1980s, and 1990s, as summarized in Ref. 2. Since then, there have been many studies^{2–4} discussing the likely end of CMOS scaling due to lithographical, power-thermal, material, and other *technological*, as opposed to *fundamental physical*, limitations. Despite the aforementioned predictions, however, CMOS has famously survived, albeit with adaptations (high-k gate dielectrics, revival of metal gates, etc.). Furthermore, the immense increase in the understanding of semiconductor physics since the 1960s has resulted in a plethora of alternative CMOS technologies that are generally field effect transistor (FET) based. Arguments are frequently made that III-V-, carbon-nanotube-, or 2D-material-based FETs have the potential to someday replace present Si FETs due to their superior mobilities and ultra-scale manufacturing capability. However, proponents of these devices have also made it evident that such devices are not yet ready to compete with state-of-the-art Si CMOS for high performance computing applications. In fact, ITRS now projects^{5} that the emerging trend of Si Multi-Gate FET (MuGFET) technology should allow Moore's law to continue for at least another decade until 6-nm gate length is reached (see Fig. 1, black diamonds).

The question of how small the CMOS/FET devices can become remains an active subject of research and debate. In 2003, Zhirnov *et al.*^{6} estimated that the minimal feature size of a “binary logic switch” is given by $xmin=\u210f/2meEs=\u210f/2mekBTln2\u22481.5$ nm at T = 300 K. This estimation is based on the Heisenberg uncertainty ($\Delta x\Delta p\u2265\u210f$) and the Landauer principle^{7} which states that the switching energy, *E _{s}*, of a binary switch must be higher than $kBTln2$ for irreversible computing. It is obvious, however, that the estimate is only applicable to the Landauer switching energy limit. On the other hand, it has been shown

^{8}that modern CMOS architectures cannot operate at such low switching energies due to prohibitively high expenses associated with the necessity to compensate for thermally induced errors. In fact, the minimal switching energy of a realistic FET transistor that guarantees error-free lifetime circuit operation is on the order of $Es=100kBT$.

^{8–10}Thus, for realistic transistors that operate sufficiently far from the Landauer limit, Zhirnov's estimate is not relevant, since $xmin=\u210f/2mekBT100\u22480.12$ nm at 300 K, which is on the order of atomic size.

We have initiated this study by utilizing the recent ITRS projections^{5} for CMOS technology downscaling and characteristics to compute the device switching energy, $Es=CgVg2$, where *C _{g}* is the gate capacitance and

*V*is the gate voltage needed to turn on a FET device. We note that this concept of switching energy applies to all FETs, including MOSFETs, MuGFETs, TFETs, SpinFETs, and SETs, but is not applicable to non-FET devices, such as memristors. While the specific numerical figures presented in ITRS reports tend to be revised in each new edition, representative data of the continuing downscaling trend for switching energy have been obtained,

_{g}^{11}shown as red curve in Fig. 1. The downscaling projection of the switching energy leads to an interesting observation that, as the gate length scales down to sub-10 nm values, the switching energy rapidly approaches the $100kBT$ value, making the device susceptible to thermal fluctuations. Hence, according to ITRS projections, scaling of the FET technology is likely capable of continuing for another 15 years, provided that the UV lithography, gate dielectric/work function engineering, and other significant technological challenges could be addressed in one way or another. However, by the year 2030, downscaling will reach a fundamental limit, when the switching energy becomes less than $100kBT$, below which reliable FET-based logic operations would not be possible due to thermal fluctuations and the consequent logic errors. In this analysis, we do not consider possibilities for hardware or software error correction that could somewhat soften this limit; we note, however, that due to the exponential increase of the thermally induced error rates with reducing switching energy,

^{7}such error correction would become impractical for sub-5 nm gate lengths. Though the projection data are estimated for Si FETs, in the following we will demonstrate that this fundamental thermal fluctuation limit also holds true for FETs with alternative (e.g., Ge, III-V) channel (and/or source-drain) materials. Moreover, the same analysis remains valid for other FET-based technologies, such as TFETs. Indeed, from basic geometry considerations, the gate capacitance of a TFET is the same or smaller than that of a CMOS transistor of the corresponding size; while the operating gate voltage of the TFET could be much lower than that for CMOS, due to the much steeper turn-on characteristics of TFETs. It is therefore easy to see that this power-saving advantage of TFETs could become detrimental at smaller nodes, as illustrated by the dashed green line in Fig. 1.

To investigate the validity of the projected switching energy in relation to the thermal fluctuation limit, we employed our fully 3D charge-self-consistent quantum transport simulator, CBR3D, to simulate and optimize the electrical performances of MuGFETs at gate lengths of 6-, 5-, and 4-nm. The CBR3D simulator is based on a numerical method called Contact Block Reduction (CBR),^{12,13} which provides an efficient implementation of the Keldysh Non-Equilibrium Greens Function (NEGF) formalism^{14} for open-system quantum transport. The CBR quantum transport is self-consistently coupled with the Poisson equation in the CBR3D simulator to satisfy the charge self-consistency. The self-consistent convergence is achieved by adopting the predictor-corrector algorithm^{15} to open systems.^{13,16} Surface and interface roughness are included with the real-space treatment,^{17} inelastic scattering processes are emulated with an analog of relaxation time approximation or “Buttiker probes.”^{18} We note, however, that in this study the emulation of inelastic scattering only affected the on-current values (about 10% reduction compared with the case of elastic scattering only) and practically did not affect the capacitance and the switching energy values. The CBR3D simulator shows a linear scaling with the number of grid points (i.e., problem size) and a nearly linear speed-up with the number of CPUs as shown in Fig. 2. This linear scaling allowed us to simulate a large number of MuGFET devices with different geometry parameters and doping profiles to perform device optimization at different gate lengths.

We first simulated and analyzed a number of MuGFET structures consisting of Si(100)/[001] channels, state-of-the-art HfSiON/SiO_{2} gate dielectrics, and TaN metal gates, at gate lengths of 6-, 5-, and 4-nm. Figure 3 shows the schematics of a representative MuGFET structure that was simulated. We obtained an optimized device at each gate length by varying the geometry dimensions (e.g., fin width and fin height) and doping profiles (e.g., step versus Gaussian doping shape at the source/channel junction). Figure 4 shows the drain current versus gate voltage characteristics obtained from our CBR3D simulator for optimized 6-, 5-, and 4-nm Si MuGFETs. For the 6-nm node, the device was optimized to closely match the ITRS specifications, including off- and on-current values.^{5} For the 5- and 4-nm nodes, we optimized the devices such that their drain off- and on-currents are close to the values obtained by extrapolating the ITRS specifications^{5} to smaller gate lengths. The appreciable leakage current for $Vg<0.2$ V is due to source-drain band-to-band tunneling, which becomes more dominant at the 4-nm node due to a shorter gate length.

Once an optimized device geometry and doping profile were determined for a given gate length, we extracted the effective gate capacitance *C _{g}* using the quasi-static approximation: the induced charge distribution $\Delta Q(r)$ has been calculated as $\Delta Q(r)=q[non(r)\u2212noff(r)]$, where $non(r)$ and $noff(r)$ are the electron density profiles when the device is in the on- and off-states, respectively. The induced charges in the source-channel-drain region and the gate region are equal in magnitude and opposite in signs, so that the integration over the entire device volume is zero to satisfy the total charge neutrality condition in the device. The capacitance is computed as $Cg=\u222b\Delta Q(r)>0\Delta Q(r)dr/Vg$, from which the switching energy

*E*is calculated as $Es=CgVg2$.

_{s}Figure 5 shows three orthogonal projections of the on-state ($Vg=0.5$ V) electron density (left column) and the corresponding induced charge distribution (right column) for the optimized 6-nm MuGFET device. Similar electron density and induced charge profiles were also obtained for the optimized 5- and 4-nm devices. From the electron density in the left column, two important effects can be observed: (i) the electronic channel is located in the center of the intrinsic silicon region, instead of in the surface region close to the gate, due to the full volume inversion achievable at sub-10 nm gate lengths;^{21} (ii) the electron densities in the source, channel, drain, and *gate* regions are all set back from the surfaces, due to quantum confinement. The induced charge distribution in (d) shows that its maximum density is located not in the channel, but near the source/drain-channel junction regions (blue color), implying that at 6-nm gate lengths, the gate capacitance is dominated by fringing effects. This is different from an optimized 10-nm FinFET device in Ref. 21, where the induced charge density is still peaked in the channel, as expected for MOSFET and larger MuGFET devices. Another important feature of the capacitive charge distribution is that the induced positive charge in the Π-shaped gate region has a complex spatial distribution, which exhibits highest densities (red color) near the surfaces that are close to the source, drain, and channel, because of stronger interactions of the gate with these regions. Capture of this complex interactions in CBR3D simulator was made possible, because electron transport in the TaN gate was modeled using the same quantum mechanical approach as the body, assuming TaN as a highly doped semiconductor with an electron effective mass equal to that of free electron and an effective “doping level” determined by fitting simulations to the tunneling current measurements in HfSiON/TaN systems.^{22} We note that these interactions between the gate and the source/drain/channel regions would be lost, if one used a standard gate treatment (e.g., Ref. 23), which neglects electron transport and quantum confinement effects and assumes equipotential boundary condition in the gate.

The switching energies have been extracted for the optimized MuGFET devices at the 6-, 5-, and 4-nm gate lengths, and are plotted as filled blue circles in the inset of Fig. 1. The switching energies obtained from the CBR3D simulator are about 10% smaller than the values calculated using ITRS projection data, likely because CBR3D captures the effects of quantum confinement which effectively reduces the gate capacitance. Our CBR3D quantum transport simulation results clearly indicate that the switching energy of an optimized MuGFET at the 5-nm node crosses the threshold of $100kBT$ and it becomes even smaller at the 4-nm node. This confirms our initial observation, based on ITRS data, that Si MuGFET devices would reach a fundamental downscaling limit around 5 nm, below which the switching energy required to turn a FET device on/off becomes sufficiently close to the energy of thermal fluctuations, preventing the device from performing suitably reliable logic operations.

To investigate how the switching energy downscaling limit may be affected by the channel material, crystallographic wafer/channel orientations, and gate dielectric, we performed CBR3D simulations on a group of other MuGFET devices, which source/drain/channel regions were made of Si(110)/[001], Si(110)/$[11\xaf0]$, Ge(100)/[001], Ge(111)/$[2\xaf11]$, and GaAs, respectively, using gate dielectric of HfSiON with the dielectric constant of 14.0 from Ref. 22 and a yet unknown material with the dielectric constant of 20.0 assumed in the most recent edition of ITRS report.^{24} The switching energies were extracted for all these devices and are plotted in Fig. 6 in unit of $100kBT$. At the 6-nm gate length, the switching energy for MuGFETs using Si channel is still sufficiently above the $100kBT$ switching threshold and has little dependence on the crystallographic orientation. As the gate length approaches 5 and 4 nm, the switching energy becomes less than the $100kBT$ threshold, and still shows insignificant dependence on the crystallographic orientation. On the other hand, the channel material and gate dielectric show discernible effect on the switching energy. As seen from Fig. 6, using Ge channel leads to higher switching energy than Si channel, because Ge has a higher dielectric constant of 16.0 compared to 12.0 of Si, which results in—nearly proportionally—higher gate capacitance. At the same time, the switching energy of a GaAs MuGFET, is much smaller than that of Si MuGFET. This effect is due to much lower electron density of states in ultra-scaled, thin channel devices with low effective mass: the corresponding number of electrons in the channel in on-state is reduced compared with the Si channel, thus decreasing the gate capacitance.

In conclusion, we outline three possibilities for the industry after the thermal fluctuation limit is reached and the density of FETs will be impossible or impractical to increase for room temperature operation: (A) accept the end of Moore's law and concentrate efforts on reducing power dissipation with the adiabatic or reversible computing; (B) use non-FET alternatives: memristors, super-conducting logic, etc.; (C) continue Moore's law using single-electron transistors (see, e.g., Ref. 25 and references therein): their switching energy trend vs. gate/island capacitance is opposite to that of all other FETs, which may allow their downscaling to sub-5 nm gate lengths.

This work was supported by the Laboratory Directed Research and Development program at Sandia National Laboratories. Sandia is a multiprogram laboratory operated by Sandia Corporation, a Lockheed Martin Company, for the United States Department of Energy's National Nuclear Security Administration under Contract No. DE-AC04-94AL85000.