Microwave noise characterization of graphene field effect transistors Open Access

Graphene¹ is promising as a channel material in high frequency and low noise field effect transistors (FETs). This is a consequence of the unique conical dispersion,² with superior mobility $(105 cm2/V s)$ for both type of carriers and intrinsic saturation velocity approaching the Fermi velocity (10⁸ cm/s).³ Since the realization of the first top-gated⁴ graphene field effect transistor (GFET) considerable effort has been exerted to push it towards higher frequencies. Nevertheless, issues such as mobility degradation caused by the gate dielectric and underlying substrate⁵ or high metal to graphene contact resistance⁶ still remain. Hence, only after de-embedding, the highest intrinsic f_max and f_T values reported till date for a GFET are 70 GHz (Ref. 7) and 427 GHz,⁸ respectively.

In addition to enhancing operating frequencies for envisioned future graphene electronics, it is important to understand the various noise processes in graphene devices. In certain applications, such as direct detectors, graphene benefits directly from its low levels of low frequency 1/f noise.⁹ On the other hand, when GFETs operate at microwave frequencies in amplifiers, 1/f noise is less important and thermally generated noise dominates. In this regime, the performance is quantified by the minimum noise temperature (T_min), for high frequency operation a figure-of-merit equally important to f_T and f_max. Thus, T_min requires to be determined with highest possible accuracy, preferably from device level noise measurements, which provide all four transistor noise parameters.¹⁰ Importantly for device optimization, this enables accurate modeling which separates the thermal noise contributions within the device, intrinsic and extrinsic, contributing to T_min. Moreover, it allows the de-embedding of measured noise temperature using correlation matrices.¹¹ To date, only noise characterization of an amplifier¹² and a resistive subharmonic mixer¹³ utilizing GFETs have been reported. The T_min of 1 μm GFET made from exfoliated graphene¹² was predicted¹⁰ to be ∼330 K and ∼75 K at 1 GHz for the extrinsic and intrinsic devices, respectively.

In this paper, results obtained from noise parameter measurements of GFETs using graphene grown by chemical vapor deposition (CVD) are presented. Additionally, noise models of the GFET gate and drain noise, excluding¹⁰ and including¹⁴ correlation, are validated and the results are related to channel carrier transport.

Graphene in this work was grown on copper foil in a cold-wall low-pressure CVD system (Black Magic, AIXTRON Nanoinstruments Ltd.) with CH₄ as precursor gas according to an established recipe.¹⁵ After the deposition, graphene was transferred onto a SiO₂ (300 nm)/Si substrate following a bubbling transfer procedure.¹⁶ The schematic diagram of GFET fabrication steps is shown in Fig. 1. Starting with graphene on the intended substrate (Fig. 1(a)), the GFET patterning was performed using electron beam (e-beam) lithography in four steps. In the first step, source/drain contacts were patterned, 1 nm Ti/15 nm Pd/100 nm Au was evaporated by electron beam and lifted off (Fig. 1(b)). Subsequently, two 1 nm thick Al layers were deposited and oxidized on a hotplate at 170 °C for 5 min (Fig. 1(c)). Mesas were patterned in the next e-beam step. Oxide and graphene were etched around the mesas by HCl and O₂ plasma, respectively (Fig. 1(d)), so that graphene remained only in the active device region. This alignment is crucial to minimize gate leakage current (I_G) and also for drain-source current (I_DS) to flow only through the channel and in turn increase transconductance (g_m). The 1 nm Al evaporation and oxidation step was repeated five times for a total thickness of ∼10 nm for the Al₂O₃ gate oxide. In the subsequent e-beam step, gate fingers were patterned and 10 nm Ti/300 nm Au was evaporated and lifted off (Fig. 1(e)). In the last e-beam step, larger source/drain/gate pads for probing were patterned and oxide was etched from the overlap area of the smaller contacts using HCl. Finally, 10 nm Ti/305 nm Au was evaporated and lifted off (Fig. 1(f)). The gate length was L = 1 μm and the device width was W = 2 × 30 μm. A relatively long channel length was chosen to achieve efficient gate modulation. The access length between gate fingers and source/drain contact was L_a = 100 nm. The SEM image of a final device is shown in Fig. 1(g). The small signal equivalent circuit of the device is shown in Fig. 2, which is similar to a standard FET equivalent circuit. The gate and drain pad resistances, R_pg and R_pd, arise from the insufficiently insulating substrate. The intrinsic part of the device is marked by a dashed rectangle in Fig. 2.

The measurements were performed in the 2-8 GHz range using an automated ATN electronic tuner system. The S- and noise parameters were measured at room temperature with an Anritsu 3797C vector network analyzer (VNA) and an Agilent N8975A noise figure analyzer (NFA), respectively, using a multiple impedance configuration. An optimum gate voltage, V_GS = 0.08 V, yielding the highest possible g_m at a drain bias of V_DS = −1.5 V and I_DS = 22 mA was used. The high drain bias results in a difference between the gate source and gate drain voltages, as opposed to a back gate configuration. Still, the bias point is sufficient to the negative side of the minimum conductivity point to result in a majority of hole carriers, unipolar conduction, throughout the GFET channel.¹⁷ The bias is essential to obtain a high enough gain, reducing the uncertainty in the noise measurement. Operating at comparatively lower or higher drain bias either increased the uncertainty or degraded the GFETs by exerting electrical stress. The gate leakage current was $IG≈100 pA$⁠, which is beneficial for a minimum level of shot noise $(igs2¯=2qIGΔf)$ and thus negligible contribution at the measured noise level.

The extrinsic f_T (from short circuit current gain $|h21|=1$⁠) and f_max (Mason's unilateral gain U = 1) of the GFETs calculated from as-measured S-parameters were on the order of 10.5 GHz and 13 GHz, respectively. The measured and modeled S-parameters of a representative GFET are shown in Fig. 3.

The high frequency noise of a two-port network, such as a FET, is expressed through the noise temperature, T_n. It depends on the source reflection coefficient, $Γs$⁠, presented to the device input according to

where Z₀ is the reference impedance and T₀ = 290 K. The noise parameters defined in Eq. (1) are the minimum noise temperature (T_min), optimum source reflection coefficient $(Γopt)$⁠, where T_n = T_min is attained, and the noise resistance (R_n) quantifying the sensitivity to increased noise temperature with $Γs≠Γopt$⁠. The measured noise parameters, as well as the calculated intrinsic device counterparts after de-embedding device parasitics, are shown in Figs. 4–6, respectively.

The extracted values of the parasitic components of the GFET and the corresponding intrinsic device parameters are listed in Table I. The source and drain contact resistances are expressed as $Rs=Rd=Ra+Rm−g$⁠, where $Ra=RsheetLaW$ is the resistance coming from the access region unaffected by the top gate and $Rm−g=ρc/W$ is the metal to graphene contact resistance. R_s and R_d are considered to be equal due to the symmetric device layout. To obtain R_s and R_d, the sheet resistance of graphene, $Rsheet=583 Ω/◻$⁠, and contact resistivity, $ρc=76 Ωμm$⁠, were extracted via transfer length method (TLM) measurements.¹⁸ Although R_sheet is considerably higher than the values of highly doped III–V cap layers in HEMTs, the final value $Rs=Rd=135 Ωμm$ is comparable to state-of-the-art HEMT technology. The gate resistance was obtained to be $54 Ω/mm$ from DC end-to-end measurement, i.e., measuring the DC resistance of the gate metalization stack and accounting for the small-signal operation according to R_g,RF = R_g,DC/3. The remaining parasitic components of the GFET were extracted using separately fabricated open and short structures. From the extrinsic GFET, the parasitics were de-embedded to obtain the intrinsic device parameters using two-port parameter manipulations.¹⁹ Subsequently, the intrinsic noise parameters were obtained by the noise correlation matrix approach.¹¹ The noise current sources for the drain and induced gate noise are shown in Fig. 2. In the Pospieszalski model,¹⁰ these are described by uncorrelated temperatures T_d of R_ds and T_g of R_i. On the other hand, P and R of the PRC model have an imaginary correlation factor jC.¹⁴ The parasitics contribute thermal noise characterized by the ambient temperature, T_a.

Also shown in Figs. 4–6 are the model fits with T_d = 1950 K and T_g = 700 K, corresponding to P = 4, R = 0.7, and C = 0.4. Ideally in a FET, fluctuations in the drain current and gate voltage are perfectly correlated, $C→1$⁠, which is closely fulfilled in HEMTs under low noise bias.²⁰ The comparably low correlation in the GFET, despite the excellent aspect ratio $(tAl2O3/Lg)$⁠, indicates degraded electrostatics possibly due to traps in the gate oxide. High quality gate stacks are thus essential to increase the cancellation of gate and drain noise²⁰ and improve the GFET microwave noise level. At the relatively high drain current used, the power dissipation creates an electron temperature above ambient.²¹ This is reflected in a gate temperature $Tg>Ta$⁠. The measured noise parameters obey the relation $1≤4GoptRnT0/Tmin<2$⁠, where $Gopt=Re[Yopt]$ and Y_opt is the source admittance when T_n = T_min. Thus, the use of the noise models¹⁰ is validated. The difference between extrinsic and intrinsic T_min lies mainly in R_pg, which is related to the insufficiently insulating Si substrate, rather than an inherent limitation of GFETs. A related issue is the modeled minimum extrinsic noise temperature (T_min,ex), which does not go through 0 K at zero frequency (Fig. 4). De-embedding of R_pg results in minimum intrinsic noise temperature (T_min,in) identical 0 K at zero frequency for the GFET. In addition to T_n, also the transistor gain is affected by the input impedance. For comparison, the source reflection coefficient for maximum stable gain (G_MSG) is also plotted in Fig. 5. It is apparent that the required $Γs$ for maximum gain is close to $Γopt$ for minimum noise.

To compare the noise performance of GFETs with other technologies, an appropriate frequency, f = 2 GHz, is chosen considering the GFETs' f_T and f_max. For mature technologies, the device gate lengths are shorter and reported measurement frequencies in the literature are generally higher. Consequently, the normalized figure of merit T_min/f/L (K/GHz/μm) is used to enable a more equitable comparison. The comparison of f_T, T_min, and T_min/f/L of microwave FET technologies with GFETs at T_a = 300 K is presented in Table II. In the case of GFETs, T_min = T_min,in is used in the comparison. For mature technologies, the intrinsic and extrinsic noise temperatures are similar and T_min = T_min,ex is used.

For GFETs at 2 GHz, T_min,ex = 210 K and T_min,in = 100 K (from the model trend in Fig. 4) with G_a = 10.6 dB, i.e., the associated gain with the input matched for minimum noise, $Γs=Γopt$⁠. In comparison to the recent 45 nm Si CMOS technology node²² using strained silicon and metal gates with corresponding reduction in T_min, GFETs show similar performance in terms of noise judging from the T_min/f/L values keeping in mind that the improvement in T_min saturates at short gate lengths. This requires a successful scaling of the gate length with maintained performance for the GFET. Subtracting the pad noise, the GFET is not yet comparable to GaAs MESFETs²³ or III-V HEMT technologies.^24,25

A limiting factor for the microwave noise is the reduced carrier mobility in GFETs, in this case the hole mobility μ_p = 450 cm²/Vs. The mobility indicates device operation in a linear regime, rather than velocity saturation, despite the high average field in the channel ∼1.4 V/μm.¹⁷ An upper limit estimate for the carrier velocity is set by the minimum carrier density, n₀ = 2 × 10¹² cm⁻², from thermal generation² and substrate impurities,¹⁷ i.e., $v<IDS/(Wqn0)∼1×107 cm/s$⁠. This is in reasonable agreement with $vsat=1−2×107 cm/s$ at T_a = 300 K ambient with n = 2–10× 10¹² cm⁻² as limited by low energy SiO₂ phonons.¹⁷ This is in contrast to optimum low noise bias for III-V transistors, where V_DS and V_GS are set for velocity saturation and low I_DS, respectively.

An observed mobility increase at cryogenic temperatures in suspended graphene is likely to provide reduced noise temperature, due to the decay of scattering from acoustic phonons. Nevertheless, on SiO₂ substrate mobility is mainly limited by Coulomb scattering from charged impurities with little temperature dependence.²⁶ Thus, also at cryogenic temperature, the noise performance will be limited by the substrate. Opposed to outer noise limiting mechanisms, inherently graphene has a low density of states close to the Dirac point.² This limits g_m for a certain Fermi level shift, with disadvantageous effect on $Tmin∝1/fT∝1/gm$⁠.¹⁰ Opening of $Eg>0$ by a nanoribbon channel² could boost f_T and thus T_min further.

In summary, the device level noise characterization of a GFET at microwave frequencies is reported in this paper. The presented results are comparable with Si CMOS. A key step to improve the noise level is to enhance the channel mobility and reach saturated carrier transport. The substrate is then critical for v_sat to be limited only by highly energetic phonons like in suspended graphene.²⁷ Achieving gain for a wider range of biases enables a more complete study with enhanced measurement accuracy.

This work was supported by the Swedish Foundation of Strategic Research (SSF) and the Knut and Alice Wallenberg Foundation (KAW).