Electromagnetic simulation modeling of silicon substrate for 60 GHz on-chip differential-feed dipole antenna Open Access

Millimeter-wave complementary metal oxide semiconductor (CMOS) radio frequency (RF) circuits have been received substantial attention by the advanced CMOS process technology.^1,2 In the millimeter-wave band, the connection, such as wire bonding or flip chip bonding, between the RF circuit and off-chip antenna is not an easy task because of the radiation leakage and/or adding parasitic components. To overcome this problem, on-chip antennas, which do not suffer from connection problems, have been studied by many researchers.^3–5 However, the agreement between the simulation and measurement was poor in such a high 60 GHz frequency band. Accurate and realistic modeling in electromagnetic (EM) simulation is very important to obtain agreement with measurement. The authors have investigated appropriate excitation modeling in the EM simulation.⁶ 

In this letter, a 60 GHz on-chip differential-feed dipole antenna integrated in a 65 nm CMOS technology is investigated by simulation and measurement. A ground-signal-signal-ground (GSSG) pad on the chip, as well as the whole chip, is modeled in the EM simulation. It is very difficult to know complete material properties of the CMOS chip because there are many complicated structures, such as field effect transistors (FETs) and active dummies. EM simulation enables it to be possible to estimate equivalent material properties. Modeling of lossy thin layer, which is considered to be well, on the surface of CMOS substrate was found to be important by EM simulation.⁷ Simulated frequency characteristic of S-parameters agreed well with the measured one by considering the lossy layer. The simulated radiation efficiency was 3.4% at 60 GHz. Low radiation efficiency is due to the existence of the lossy layer on the surface of CMOS chip. Improvement of radiation efficiency is considered by changing the conductivity of CMOS substrate by EM simulation.

A micrograph of a fabricated chip is shown in Fig. 1. The chip is 2.1 mm² and 65 nm CMOS process was used. Figure 2 shows the configuration of an on-chip differential-feed dipole antenna. The dipole is fed by two microstrip lines (MSLs). Top metal layer is used for dipole elements and signal lines of MSLs. The first metal layer (M1) is used for the ground plane of the MSL. The MSL is excited by a 100 μm-pitch GSSG probe through the GSSG pad. Metal walls near the GSSG pad compose of all metal layers and vias. Rectangular well prohibit region exists around the dipole antenna.

The thickness of the silicon substrate (⁠$εr=12$⁠, $ρ=10$ $Ω cm$⁠) is 320 μm. Lossy layer, or well, exists between the surface of the silicon substrate and insulator. The conductivity and thickness of the layer had been estimated by EM simulation in the previous work,⁷ and it was found that the layer with conductivity of 10⁵ S/m and thickness of 1 μm represents behavior of measurement very well.

Figure 3 shows the simulation model of the on-chip differential-feed dipole antenna in the finite element method (FEM) based EM simulator HFSS ver.11. GSSG pads are excited by using lumped ports with 50 Ω impedance. Validation of the excitation model is detailed in Ref. 6. The side and top faces of an enclosing air box are radiation boundary. The bottom face is modeled with the perfect electric conductor (PEC) because the chip is placed on the metal surface in measurement. Dummy metal fills are neglected in simulation. The lossy layer on the surface of the silicon substrate outside the rectangular region is modeled by a layer with conductivity of 10⁵ S/m and 1 μm-thick as suggested in Ref. 7.

Figure 4 shows frequency characteristic of S-parameters. Ports 1 and 2 correspond to lumped ports in the simulation as shown in Fig. 3(b). Three simulated values, indicated by “cal,” are results of models shown in Fig. 5. In these models, the coverage region where lossy layer exists is different. Partially lossy layer is modeled in Fig. 5(a), which is considered to be the best model representing the real measured structure. Lossy layer is modeled all over the chip in Fig. 5(b), while the lossy layer is neglected in Fig. 5(c). Because the structure is symmetric, $S11$ is identical to $S22$⁠, which is confirmed in simulation and measurement. The simulated frequency characteristic of the reflection coefficient $S11(=S22)$ agrees very well with the measured one. In the transmission coefficient $S12(=S21)$⁠, the agreement between the simulation and measurement is good. The relative bandwidth of the measured $S11$ less than −5 dB is about 41%, which is wider than we expected. Large losses due to the silicon substrate and other material make the quality factor lower, which cause wide bandwidth by appearance. Figure 6 shows frequency characteristic of Z-parameters which are calculated from Fig. 4. It is observed that $Z11$ approaches 50 Ω around 60 GHz. Figure 7 shows the frequency characteristic of reflection coefficient $Γ$ with differential feed. It was calculated by S-parameters in Fig. 4 as $Γ=S11−S12$⁠.⁶ Measured results agreed well with the simulation model in Fig. 5(a) while it has relatively large discrepancy with simulation models in Figs. 5(b) and 5(c). Figure 8 shows calculated E-plane (yz) and H-plane (xz) gain patterns of the dipole antenna in Fig. 5(a). The maximum gain is −10.3 dBi at $θ=0°$⁠.

Table I shows calculated radiation efficiency, directivity, and peak gain for three models in Fig. 5. Calculated radiation efficiency and peak gain of the on-chip differential-feed antenna were 3.4% and −10.3 dBi, respectively. The order of the calculated radiation efficiency is in the reasonable range with measured data reported by other groups (3%–10%).^8,9 If the lossy layer (well) exists all over the chip, especially under the antenna, the radiation efficiency and peak gain become very low of 0.1% and −23.7 dBi, respectively. If the lossy layer were removed, the radiation efficiency and peak gain would be improved to 23.6% and −0.5 dBi, respectively.

Table II shows estimated loss factor by EM simulation for the model in Fig. 5(a). Losses due to the conductor, lossy layer, and Si substrate were 6%, 20.6%, and 70%, respectively.

Figure 9 shows calculated radiation efficiency as a function of conductivity of Si CMOS substrate for the model in Fig. 5(c) (w/o lossy layer). It could be estimated that the radiation efficiency can be improved to more than 90% if the conductivity of the Si substrate became less than 0.1 S/m (resistivity of 1 kΩ cm).

In summary, a 60 GHz on-chip differential-feed dipole antenna integrated in a 65 nm CMOS technology was investigated by simulation and measurement. Frequency characteristic of S-parameters showed good agreement between simulation and measurement. It was found that it is important to model lossy thin layer with conductivity of 10⁵ S/m and thickness of 1 μm, which is considered to be well, on the surface of CMOS substrate. The simulated radiation efficiency and peak gain were 3.4% and −10.3 dBi at 60 GHz, respectively. The loss factor was estimated by EM simulation, and it was found that low radiation efficiency was mainly due to the existence of the lossy layer and high conductivity of 10 S/m of Si substrate. It is suggested that the radiation efficiency can be improved to more than 90% if the lossy layer is removed and the conductivity of the Si substrate became less than 0.1 S/m (resistivity of 1 kΩ cm).

This work was partly supported by Semiconductor Technology Academic Research Center (STARC) and MEXT/JSPS KAKENHI Grant No. 24760291. The chip in this study has been fabricated in the chip fabrication program of VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with eShuttle, Inc., and Fujitsu Semiconductor, Ltd. The authors would like to express their deepest gratitude to Osamu Kobayashi of STARC, Toshiakira Ando of PANASONIC, and Ryuichi Fujimoto of TOSHIBA for their fruitful discussion. The chip fabrication and measurements were supported by Ning Li, Bu Qing Hong, Tatsuya Yamaguchi, and Yuuki Seo of Tokyo Institute of Technology.