Graphene technology has made great strides since the material was isolated more than a decade ago. However, despite improvements in growth quality and numerous “hero” devices, challenges of uniformity remain, restricting the large-scale development of graphene-based technologies. Here, we investigate and reduce the variability of graphene transistors by studying the effects of contact metals (with and without a Ti layer), resist, and yttrium (Y) sacrificial layers during the fabrication of hundreds of devices. We find that with optical photolithography, residual resist and process contamination are unavoidable, ultimately limiting the device performance and yield. However, using Y sacrificial layers to isolate the graphene from processing conditions improves the yield (from 73% to 97%), the average device performance (three-fold increase of mobility and 58% lower contact resistance), and the device-to-device variability (standard deviation of Dirac voltage reduced by 20%). In contrast to other sacrificial layer techniques, the removal of the Y sacrificial layer with dilute HCl does not harm surrounding materials, simplifying large-scale graphene fabrication.

Since the first experimental demonstration of monolayer graphene in 2004,1 academic and industrial research labs have extensively explored applications that leverage the unique electrical, mechanical, and thermal properties of this material. To date, these efforts have yielded promising results for chemical sensors,2 transparent and flexible electronics,3 and analog circuits.4 Rapid advances in large-scale production of graphene via chemical vapor deposition (CVD) have also accelerated the development and mass-production of graphene towards practical applications.5 

While unique physical properties motivate research in graphene electronics, the device yield and spatial variability will ultimately dictate the industrial impact. To this end, many works have focused on improving the quality and cost of large-scale CVD graphene growth and transfers,6,7 but fewer have attempted to quantify and reduce the detrimental effects of subsequent device fabrication, which may lead to inconsistencies in reported results. Optical photolithography—critical for large-scale fabrication—is particularly problematic as photoresist (PR) residues on the graphene surface negatively impact the device performance.8 Additionally, post-fabrication residue removal methods, such as non-selective physical etches with CO2,9 are difficult to reproduce in a controlled manner and may damage graphene by inducing tears and wrinkles.

In contrast to post-fabrication cleaning methods, modifying and optimizing a process flow to protect graphene from its interaction with PR is a more suitable approach. The semiconductor industry has employed native SiO2 as a sacrificial protection layer for Si during integrated circuit fabrication. However, since graphene has no equivalent native oxide, thin aluminum (Al) and titanium (Ti) layers have been introduced as sacrificial layers.10–12 Subsequent removal is nontrivial and can affect the graphene and surrounding materials (i.e., substrates, insulators, and PR) during fabrication. For example, Al removal via the AZ422 developer12 lengthens resist development times, potentially leading to the overdevelopment and reduced yield of small features. For Ti removal,10 hydrofluoric (HF) acid is utilized. However, HF can etch underneath the graphene and delaminate devices from the substrate, lowering the device yield on oxide substrates such as SiO2.

In this work, we introduce the use of yttrium (Y) sacrificial layers to protect graphene. Y is an ideal material for this purpose, as it (1) readily forms a sub-stoichiometric oxide that does not degrade electrical transport13 and (2) is etched in dilute hydrochloric acid (HCl), which is safe for both SiO2 and PR. The latter point greatly simplifies fabrication, resulting in higher device yield, and differentiates the Y-sacrificial method from existing alternatives. We fabricate and measure hundreds of devices, employing transport models and materials analysis to physically quantify the cause of fabrication-induced degradation. We then introduce the use of Y-sacrificial layers to alleviate degradation, reduce variability, increase performance (three-fold intrinsic mobility improvement and 58% decrease in contact resistance), and improve our device yield up to 97%.

Figure 1 outlines the process flow used, including the implementation of the Y-sacrificial layer. Complete fabrication details are given in the supplementary material, and we outline here the material characterization relevant to Y-sacrificial layer processing. Monolayer graphene is first grown on Cu foils by chemical vapor deposition at 1000 °C, using isopropyl alcohol (IPA) or a CH4 carbon source (additional details are given in the supplementary material). The graphene is then transferred onto 90 nm SiO2 on p+ Si (<0.005 Ω cm) substrates with a poly(methyl methacrylate) (PMMA) support scaffold14 [Fig. 1(a)], applying a modified RCA cleaning process7 to minimize wrinkles and impurities (i.e., Fe, Cl, and Cu). Immediately after transfer and prior to device fabrication, the samples are coated with ∼5 nm of Y via electron-beam evaporation at a base pressure of ∼10−7 Torr to isolate and protect the underlying graphene [Fig. 1(b)]. The Y-coated samples are not metallic, indicating that the Y film is oxidized upon exposure to air after deposition.

To characterize the effects of process conditions on device quality, we fabricate back-gated graphene field-effect transistors (GFETs) by ultraviolet (UV) photolithography, as shown in Figs. 1(c)–1(h). During Y deposition, a glass slide raised by silicon spacers shields half of each sample to yield control regions where the graphene and subsequent devices are fully exposed to process conditions. This approach leads to two types of devices, as shown in Fig. 1(e): “bare” GFETs with potential PR residue and/or processing damage in the channel and under the contacts, and “Y-protected” devices.

We also repeat GFET fabrication (with and without Y protection) using pure palladium (Pd) contacts instead of Ti/Pd contact stacks (where Ti serves as the adhesion layer) and polymethylglutarimide/Shipley 3612 (PMGI/SPR3612) instead of lift-off layer 2000/Shipley 3612 (LOL2000/SPR3612) bilayer PR stacks. By eliminating the Ti adhesion layer that can oxidize, the Pd contacted devices should exhibit cleaner, more ideal contact interfaces and lower contact resistance.15 Derived from the same chemistry, PMGI and LOL2000 differ only in that LOL2000 contains additional contrast-enhancing dye. Thus, the use of PMGI may lower the amount of residual PR. These process splits allow us to compare improvements from complete graphene protection with Y-sacrificial layers vs. other common process variations.

The Y-sacrificial layer is etched in DI:HCl in the ratio of 10:1 after resist exposure and development to expose the underlying graphene when necessary, such as prior to contact metallization [Fig. 1(c)], channel definition [Fig. 1(f)], and final device definition [Fig. 1(h)]. Contact metals for all devices remained intact, despite the total of three HCl baths necessary for back-gated GFET fabrication, with no optically visible delamination or lateral removal of metals. Atomic force microscopy (AFM) measurements show ∼1 to 1.5 nm contact metal reduction after a single 15 s bath (Fig. S3 in the supplementary material), yielding an HCl etch selectivity of ∼3:1 of Y to the contact metal (here 1.5 nm Ti capped with 40 nm Pd). Processing with sacrificial Y should not affect the device yield for contact metals of typical thickness (>40 nm) since Y layers are thin (<5 nm) and etch times are short (at most 60 s).

Auger spectroscopy results shown in Fig. 2(b) and Fig. S2 in the supplementary material confirm Y removal in desired regions, and the ∼1736 eV peak present only over the channel is indicative of a protective, partially oxidized Y layer.16 Raman spectroscopy of graphene after Y removal also indicates that no graphene damage is induced (Fig. S4 in the supplementary material). To assess sample cleanliness, we conduct atomic force microscopy (AFM) of graphene in the “open” contact regions [Figs. 2(c) and 2(d)] after PR exposure, development, and Y etching but prior to metal deposition. The root mean square (RMS) surface roughness decreases by a factor of two (from 1.29 to 0.69 nm) with the use of a Y-sacrificial layer, consistent with a cleaner surface.

Figure 3 displays a summary of electrical data for the subset of 44 bare and 56 Y-protected devices fabricated using Ti/Pd contacts and LOL2000 resist, and the arrows display the changes between them. Electrical measurements are taken in vacuum (T = 294 K, P ≈ 10−5 Torr) following an in situ vacuum anneal at 200 °C for 1 h, which also reverses remnant HCl-induced doping (Figs. S5 and S6 in the supplementary material). ID vs. VBG measurements (at VDS = 50 mV) as in Fig. 3(a) are then fit to our charge transport model17,18 using a least-squares method to extract contact resistance (RC), carrier puddle density (n*), and intrinsic mobility (μ). The total device resistance is R = (L/W)RS+ 2RC + Rseries, where RS = [(n + p)]−1 is the graphene sheet resistance, q is the elementary charge, and (n + p) is the total carrier concentration which depends on VBG [reaching a minimum at n + p = 2n0 when VBG = V0, the charge neutrality point (CNP)].17,18 We note that n0 = [(n*/2)2+ nth2]1/2, where n* is the carrier puddle density generated by ionized impurities, and nth are the thermally generated carriers.17,18 Thus, at a given temperature, lower n0 means lower graphene impurity density. RC follows a transfer-length method (TLM) model,17 and both this and the mobility are listed at a carrier density of 5 × 1012 cm−2 in the remainder of this work. Rseries = 12 Ω is our total parasitic pad, lead, and cable resistance.

Figure 3(a) shows much improved transport in Y-protected samples, which nevertheless exhibit electron-hole asymmetry due to cleaner metal-graphene contact interfaces. (A p-n junction appears at the metal-graphene interface, increasing the contact resistance for electrons at positive VBG – V0.19) Figure 3(b) reveals that the Y-sacrificial process decreases the estimated puddle carrier density n* from 4.6 × 1011 to 2.2 × 1011 cm−2, which is indicative of a cleaner graphene surface. In fact, the puddle carrier density of the Y-protected CVD graphene samples is comparable to that of previous studies on exfoliated graphene on SiO2.17,18 This is an important device metric, as it sets a limit on the minimum GFET current and therefore on the maximum achievable on/off current ratio. In the ideal case of impurity-free graphene, the minimum carrier density would be given only by thermally generated carriers, 2n0 = 2nth ≈ 1.6 × 1011 cm−2 at 300 K.18 (Thus, an on/off ratio of >100 could be achieved in ultra-clean GFETs at room temperature, assuming a maximum carrier density of >1013 cm−2 achieved by strong gating and negligible contact resistance. To date, the highest GFET on/off ratios we are aware of are ∼24 at 300 K and ∼35 at 250 K, for graphene samples encapsulated by h-BN.20)

In addition, Figs. 3(c) and 3(d) show that average RC and μ improve by factors of ∼2.5× and ∼3×, respectively (RC decreases from 4.67 to 1.92 kΩ μm, while μ increases from ∼1200 to ∼3100 cm2 V−1 s−1). While these values are for holes, similar improvements in RC and μ are also observed for electron transport (Fig. S7 in the supplementary material). Table I summarizes the electrical properties and a yield of 227 measured devices using atmospheric-pressure CVD graphene, which includes those fabricated with pure-Pd contacts and using PMGI lift-off resist as well. We use a conservative definition of yield, i.e., the percentage of devices with a well-defined, single charge neutrality point (CNP) V0 and an on/off ratio of >3, where on-current is measured at maximum negative gate bias (VBG = −30 V) and off-current is measured at the CNP. This expresses the yield in terms of electrically “well-behaved” devices, which is a better indicator of useful devices than simply the proportion of electrically active devices.

When comparing the device splits processed without the Y-protective layer (Table I, LOL2000 resist and Ti/Pd contacts vs. PMGI resist and Pd contacts), only the yield improves as the number of devices with single CNP increases for the PMGI process. Since multiple CNPs signify the presence of charged interface traps,21 the improvement in the yield is indicative of cleaner graphene interfaces with the use of PMGI vs. LOL2000, where the contrast-enhancing dye may leave surface residue. However, despite a more ideal metal-graphene interface with Pd-only contacts, the lack of average device performance improvement suggests that another mechanism is suppressing device performance. This hypothesis is supported by analyzing the Y-sacrificial layer devices, which exhibit mobility, impurity density, and contact resistance improvement over “bare” devices, regardless of the metal and/or resist used (Table I). This indicates that process-induced contamination ultimately limits the performance of graphene devices, and attempts to reduce residue are insufficient. In other words, graphene must be fully shielded from fabrication conditions in order to obtain optimal device performance.

To demonstrate the wide applicability of our approach, we fabricate and measure additional devices using graphene from various academic and commercial sources (our atmospheric vs. low-pressure CVD growth vs. Graphene Supermarket, see details in the supplementary material). The extracted average values of mobility, contact resistance, and carrier puddle density (Table S1 in the supplementary material) show a clear improvement for all GFETs fabricated with Y-sacrificial layers, underscoring the effectiveness of the technique. To further quantify the variability reduction, we extract the CNP, also known as the Dirac voltage V0, for all measured devices (Fig. S8 in the supplementary material). The average V0 is reduced from 1.22 to 0.89 V, and the standard deviation decreased from 3.19 to 2.54 V with the Y-sacrificial process. Given that our test devices are using 90 nm SiO2 as the back-gate dielectric, the equivalent V0 for 1 nm thin SiO2 would be 0.01 ± 0.028 V, very close to the true charge neutrality, signifying that the Y-sacrificial layer technique does not induce additional doping.

The impact of process-induced contamination on large-scale GFET fabrication is also evident from the measured on/off ratios of the subset of atmospheric-pressure derived graphene devices, as shown in Fig. 4(a). Regardless of the PR stack or the contact metal, bare devices (without a Y-sacrificial layer) have higher RC due to process-induced contamination, yielding a lower on/off ratio at shorter channel lengths, as RC begins to dominate. This problem is alleviated with the use of Y-sacrificial layers, which enable cleaner contacts and preserve the on/off ratio down to the shortest channel lengths used in this study (L = 3 μm). In Fig. 4(b), we also quantify a simple analog device metric, the maximum ratio of transconductance to current, max(gm/ID), extracted from ID vs. VBG sweeps. The Y-sacrificial layers improve average max(gm/ID) by ∼60%, reflecting an improvement in the channel quality as the max(gm/ID) is obtained at biases near V0, where the channel dominates device transport. Since the oxide is the same for both types of samples, the improvement is solely from the Y-sacrificial layer technique, reinforcing the notion that graphene must be protected from PR during processing to maximize the device performance.

In summary, we introduced a simple and practical method to improve the graphene device quality through the use of Y-protective layers during processing. By electrically characterizing hundreds of graphene devices fabricated under various conditions, we identify through physical, quantitative analysis that PR residue restricts device variability and performance. Unlike existing methods, the Y-sacrificial technique protects the graphene without affecting surrounding materials, leading to increased device performance, reduced variability, and increased yield (here up to 97%). Although demonstrated for GFETs on SiO2, the Y-sacrificial technique is applicable to other HCl-compatible two-dimensional materials and substrates, where process contamination could be a concern.

See supplementary material for further details and the analysis of the yttrium sacrificial layer process and additional electrical data.

This work was supported in part by Systems on Nanoscale Information Fabrics (SONIC), one of the six SRC STARnet Centers sponsored by MARCO and DARPA, by the Air Force Office of Scientific Research (AFOSR) under Grant No. FA9550-14-1-0251, in part by the National Science Foundation (NSF) EFRI 2-DARE under Grant No. 1542883, and by the Stanford SystemX Alliance. We thank Ling Li and Professor H.-S. P. Wong for providing the CVD graphene samples from Graphene Supermarket. We also thank Sam Vaziri for helpful comments during the manuscript preparation process.

1.
K. S.
Novoselov
,
A. K.
Geim
,
S. V.
Morozov
,
D.
Jiang
,
Y.
Zhang
,
S. V.
Dubonos
,
I. V.
Grigorieva
, and
A. A.
Firsov
,
Science
306
,
666
(
2004
).
2.
P.
Yasaei
,
B.
Kumar
,
R.
Hantehzadeh
,
M.
Kayyalha
,
A.
Baskin
,
N.
Repnin
,
C.
Wang
,
R. F.
Klie
,
Y. P.
Chen
,
P.
Král
 et al,
Nat. Commun.
5
,
4911
(
2014
);
[PubMed]
A.
Salehi-Khojin
,
D.
Estrada
,
K. Y.
Lin
,
K.
Ran
,
R. T.
Haasch
,
J. M.
Zuo
,
E.
Pop
, and
R. I.
Masel
,
Appl. Phys. Lett.
100
,
033111
(
2012
).
3.
S.
Lee
,
K.
Lee
,
C.-H.
Liu
,
G. S.
Kulkarni
, and
Z.
Zhong
,
Nat. Commun.
3
,
1018
(
2012
);
[PubMed]
R.-H.
Kim
,
M.-H.
Bae
,
D. G.
Kim
,
H.
Cheng
,
B. H.
Kim
,
D.-H.
Kim
,
M.
Li
,
J.
Wu
,
F.
Du
,
H.-S.
Kim
,
S.
Kim
,
D.
Estrada
,
S. W.
Hong
,
Y.
Huang
,
E.
Pop
, and
J. A.
Rogers
,
Nano Lett.
11
,
3881
(
2011
).
[PubMed]
4.
N. C.
Wang
,
S. K.
Gonugondla
,
I.
Nahlus
,
N. R.
Shanbhag
, and
E.
Pop
, in
IEEE Symposium on VLSI Technology
(
2016
);
S.-J.
Han
,
A. V.
Garcia
,
S.
Oida
,
K. A.
Jenkins
, and
W.
Haensch
,
Nat. Commun.
5
,
3086
(
2014
).
[PubMed]
5.
A. C.
Ferrari
,
F.
Bonaccorso
,
V.
Falko
,
K. S.
Novoselov
,
S.
Roche
,
P.
Bøggild
,
S.
Borini
,
F.
Koppens
,
V.
Palermo
,
N.
Pugno
 et al,
Nanoscale
7
,
4598
(
2015
).
6.
Y.
Hao
,
M. S.
Bharathi
,
L.
Wang
,
Y.
Liu
,
H.
Chen
,
S.
Nie
,
X.
Wang
,
H.
Chou
,
C.
Tan
,
B.
Fallahazad
 et al,
Science
342
(
6159
),
720
(
2013
);
[PubMed]
S.
Rahimi
,
L.
Tao
,
S. F.
Chowdhury
,
S.
Park
,
A.
Jouvray
,
S.
Buttress
,
N.
Rupesinghe
,
K.
Teo
, and
D.
Akinwande
,
ACS Nano
8
(
10
),
10471
(
2014
).
[PubMed]
7.
X.
Liang
,
B. A.
Sperling
,
I.
Calizo
,
G.
Cheng
,
C. A.
Hacker
,
Q.
Zhang
,
Y.
Obeng
,
K.
Yan
,
H.
Peng
,
Q.
Li
 et al,
ACS Nano
5
,
9144
(
2011
).
8.
R.
Shi
,
H.
Xu
,
B.
Chen
,
Z.
Zhang
, and
L. M.
Peng
,
Appl. Phys. Lett.
102
,
113102
(
2013
).
9.
S.
Gahng
,
C. H.
Ra
,
Y. J.
Cho
,
J. A.
Kim
,
T.
Kim
, and
W. J.
Yoo
,
Appl. Phys. Lett.
104
(
22
),
223110
(
2014
).
10.
C. A.
Joiner
,
T.
Roy
,
Z. R.
Hesabi
,
B.
Chakrabarti
, and
E. M.
Vogel
,
Appl. Phys. Lett.
104
,
223109
(
2014
).
11.
S.
Mzali
,
A.
Montanaro
,
S.
Xavier
,
B.
Servet
,
J.-P.
Mazellier
,
O.
Bezencenet
,
P.
Legagneux
,
M.
Piquemal-Banci
,
R.
Galceran
,
B.
Dlubak
 et al,
Appl. Phys. Lett.
109
(
25
),
253110
(
2016
).
12.
A.
Hsu
,
H.
Wang
,
K. K.
Kim
,
J.
Kong
, and
T.
Palacios
,
IEEE Electron Device Lett.
32
,
1008
(
2011
).
13.
L.
Wang
,
X.
Chen
,
Y.
Wang
,
Z.
Wu
,
W.
Li
,
Y.
Han
,
M.
Zhang
,
Y.
He
,
C.
Zhu
,
K. K.
Fung
 et al,
Nanoscale
5
(
3
),
1116
(
2013
).
14.
J. D.
Wood
,
G. P.
Doidge
,
E. A.
Carrion
,
J. C.
Koepke
,
J. A.
Kaitz
,
I.
Datye
,
A.
Behnam
,
J.
Hewaparakrama
,
B.
Aruin
,
Y.
Chen
 et al,
Nanotechnology
26
(
5
),
055302
(
2015
).
15.
E.
Guerriero
,
L.
Polloni
,
M.
Bianchi
,
A.
Behnam
,
E.
Carrion
,
L. G.
Rizzi
,
E.
Pop
, and
R.
Sordan
,
ACS Nano
7
(
6
),
5588
(
2013
).
16.
J. M.
Baker
and
J. L.
McNatt
,
J. Vac. Sci. Technol.
9
,
792
(
1972
).
17.
M.-H.
Bae
,
S.
Islam
,
V. E.
Dorgan
, and
E.
Pop
,
ACS Nano
5
,
7936
(
2011
).
18.
V. E.
Dorgan
,
M.-H.
Bae
, and
E.
Pop
,
Appl. Phys. Lett.
97
(
8
),
082112
(
2010
).
19.
K.
Nagashio
and
A.
Toriumi
,
Jpn. J. Appl. Phys.
50
,
070108
(
2011
);
B.
Huard
,
N.
Stander
,
J. A.
Sulpizio
, and
D.
Goldhaber-Gordon
,
Phys. Rev. B
78
(
12
),
121402
(
2008
).
20.
L.
Wang
,
I.
Meric
,
P. Y.
Huang
,
Q.
Gao
,
Y.
Gao
,
H.
Tran
,
T.
Taniguchi
,
K.
Watanabe
,
L. M.
Campos
,
D. A.
Muller
 et al,
Science
342
(
6158
),
614
(
2013
);
[PubMed]
A. V.
Kretinin
,
Y.
Cao
,
J. S.
Tu
,
G. L.
Yu
,
R.
Jalil
,
K. S.
Novoselov
,
S. J.
Haigh
,
A.
Gholinia
,
A.
Mishchenko
,
M.
Lozada
 et al,
Nano Lett.
14
(
6
),
3270
(
2014
).
[PubMed]
21.
A.
Di Bartolomeo
,
F.
Giubileo
,
S.
Santandrea
,
F.
Romeo
,
R.
Citro
,
T.
Schroeder
, and
G.
Lupina
,
Nanotechnology
22
(
27
),
275702
(
2011
).

Supplementary Material