Lower-temperature fabrication of airbridges by grayscale lithography to increase yield of nanowire transmons in circuit QED quantum processors

Quantum hardware based on circuit quantum electrodynamics makes extensive use of airbridges to suppress unwanted modes of wave propagation in coplanar-waveguide transmission lines. Airbridges also provide an interconnect enabling transmission lines to cross. Traditional airbridge fabrication produces a curved profile by reflowing resist at elevated temperature prior to metallization. The elevated temperature can affect the coupling energy and even yield of pre-fabricated Josephson elements of superconducting qubits, tuneable couplers and resonators. We employ grayscale lithography in place of reflow to reduce the peak airbridge processing temperature from $200$ to $150^\circ\mathrm{C}$, showing a substantial yield increase of transmon qubits with Josephson elements realized using Al-contacted InAs nanowires.

Quantum hardware based on circuit quantum electrodynamics makes extensive use of airbridges to suppress unwanted modes of wave propagation in coplanar-waveguide transmission lines.Airbridges also provide an interconnect enabling transmission lines to cross.Traditional airbridge fabrication produces a curved profile by reflowing resist at elevated temperature prior to metallization.The elevated temperature can affect the coupling energy and even yield of prefabricated Josephson elements of superconducting qubits, tuneable couplers and resonators.We employ grayscale lithography in place of reflow to reduce the peak airbridge processing temperature from 200 to 150 • C, showing a substantial yield increase of transmon qubits with Josephson elements realized using Al-contacted InAs nanowires.
Free-standing metallic strips bridging separate planar conductors, called airbridges (ABs) 1 , are widely used in classical 2 and quantum [3][4][5][6] microwave-frequency integrated circuits.They are most commonly employed to suppress slotline-mode wave propagation in coplanar-waveguide transmission lines (CPWs) 7,8 by connecting the ground planes flanking the central conductor, thereby avoiding spurious resonance modes and reducing crosstalk.A second use of ABs is as interconnect allowing transmission lines to cross with low impedance mismatch and crosstalk.
ABs are intensely used in superconducting quantum hardware based on circuit QED 9,10 , where CPWs are commonly used to make resonators for qubit readout and qubit-qubit coupling, as well as qubit control lines.For example, in our planar quantum hardware architecture 11 designed for surface-code error correction, 7-and 17-qubit processors contain ∼ 600 and ∼ 1200 ABs, respectively, of which 3 and 20 are used for crossovers 12 .In the 49-qubit version, the number of AB crossovers jumps to 130 owing to the routing of qubit control lines from the chip periphery to more qubits at the center.Signal routing at higher qubit counts requires advanced methods based on three-dimensional integration, including throughsilicon vias [13][14][15] , bump bonding 16,17 , and the chip packaging itself 18 .In this context, ABs remain essential for slotlinemode suppression and crossovers.
ABs are typically added in the final fabrication step as otherwise resist non-uniformity induced by the few-µm height of ABs can reduce yield and increase variability of postfabricated circuit elements (for exceptions, see Refs. 19,20).The most traditional AB fabrication method uses resist reflow at elevated temperature to produce ABs with smooth, rounded profile.However, many types of Josephson junctions (JJs) are not compatible with this elevated temperature.Examples include the semiconductor-normal-superconductor (SNS) JJs based on InAs 21 and InSb nanowires 22 used in SNS transmons 23,24 (also called gatemons and nanowire transmons).The temperature excursions can reduce JJ yield at worst and unpredictably affect the JJ coupling energy at best, affecting qubit frequency targeting.
In this Letter, we apply grayscale lithography (GSL), a method most commonly used to fabricate microlenses [25][26][27] , to reduce the peak AB processing temperature from 200 • C (required for standard reflow) to 150 • C (limited by resist adhe-sion).We detail our calibration of GSL to accurately produce a curved resist-height profile by spatial control of electronbeam (e-beam) resist dose, with pre-compensation for proximity effect and resist nonlinearity.Our main result is the demonstration that the reduction in peak processing temperature increases the yield of SNS transmons with junctions realized using epitaxially grown, Al-contacted InAs nanowires.Very recent work 6 has demonstrated the use of GSL to fabricate ABs with a single e-beam step, showing compatibility with transmons based on standard superconductor-insulatorsuperconductor (SIS) JJs.Our focus here is on SNS JJ compatibility, with emphasis on the positive impact of AB fabrication at lower peak temperature as enabled by GSL.AB fabrication by GSL (Fig. 1) starts after defining the chip base layer containing all CPW structures and transmons, including their SNS junctions.A layer of PMGI (blue) SF15 (6.4 or 3 µm thick, see below) is spun and baked for 5 min on a hotplate at 150 • C.This is found to be the lowest viable temperature avoiding resist adhesion problems.Using e-beam lithography and GSL, the AB profile and clearances are then written.An AZ400K/water mixture in a 1:4 volume ratio is used for development.The chip is dunked into the developer for 35 s followed by a thorough water rinse for 30 s and blowdrying.At this point, we typically check for correctness by measuring the height profile along the curve of an AB using a profilometer [Fig.3(c)].Next, a 400 nm thick layer of PMMA 495K (orange) is spun and baked in a vacuum oven at 100 • C for 10 min, immediately followed by a 1.5 µm thick layer of PMMA 950k (orange) spun and baked in the same way.E-beam lithography and resist development define the lateral dimensions of the ABs.The top-layer resists must be compatible with the bottom-layer resist.This means that the top layer solvent cannot dissolve the bottom resist after it has been developed and that the developer for the top layer resists cannot develop the bottom layer.A 30 s buffered oxide etch with 1:1 dilution factor is performed prior to metal deposition.We next sputter 200 nm of NbTiN (gold) without any argon milling as the plasma can induce currents in the SNS junctions, causing their failure.A photoresist, 700 nm of S1805 baked at 85 • C for 3 min, is used for protection during dicing.After dicing, this resist is lift-off using 88 • C N-methyl pyrrolidone (NMP) for 15 min and followed by two rinses in isopropanol (IPA) at 80 • C for 10 min.Due to the conformal nature of sputtering, there is a vertical edge of NbTiN left that is approximately the height of the bottom PMMA layer.
Figure 2 shows a complete circuit QED test device with 185 ABs fabricated by GSL and with 100% yield.The device consists of 12 flux-tuneable SNS transmons each with a dedicated readout resonator coupling to a common feedline.Six of the transmons have dedicated flux bias lines, but all can be globally tuned using an external coil.The flux-tuneable Josephson element in each transmon consists of two Al/InAs/Al junctions in parallel with loop area ∼ 20 µm 2 .The two junctions are fabricated from a common hexagonal InAs nanowire with 100 nm diameter and two facets covered with epitaxially grown Al (10 nm thick).Each SNS junction is defined by etching a ∼ 200 nm section of Al [Fig.2(e)].
Contrary to the traditional method of producing a curved AB profile by reflowing the PMGI at elevated temperature (200 • C), GSL achieves the rounding by spatial control of the e-beam dose.For a positive resist like PMGI, a lower (higher) dose causes slower (faster) removal of the resist, resulting in a higher (lower) remnant resist thickness.Our desired resist- height profile is semi-circular, mimicking the profile achieved in the reflow process by surface tension.To achieve this, it is necessary to correct for proximity error as long-range scattering deposits up to 30% percent of the e-beam energy at a range exceeding 20 µm [Fig.3(a)].If this effect is not compensated, areas with dense (sparse) features are overexposed (underexposed).It is also important to calibrate the non-linear dose-height correspondence (contrast curve).Non-lineariy is desirable in typical microfabrication, as almost all processes require a binary resist profile (so-called perfect contrast) in which the resist is either not exposed or fully exposed.On the other hand, a linear resist is ideal for GSL.The non-linearity of PMGI (6.4 µm thick) is evident in the measured contrast curve shown Fig. 3(b).We precompensate proximity and resist nonlinearity using the three-dimensional proximity effect correction (3D-PEC) module in the GenISys BEAMER software 28 .The inputs are the point spread function of the energy deposited by the e-beam lithography machine on the resist stack, the interpolated contrast curve 29 and the desired height map [Fig.3(c)].The output is a prescribed position-dependent dose.Following these calibrations, we actually reduced the thickness of the PMGI layer to 3 µm in order to reduce stress in the film, which at the original thickness caused cracks in the resist and many nanowires to detach.By reducing the development time from 50 to 30 s, the calibrations were found to remain valid.This GSL process has very high yield and is stable with time.The first and last fabrication runs performed using the process, 16 months apart, yielded very similar airbridges without recipe adjustments.
GSL avoids the PMGI reflow step needed in the traditional method, reducing the peak PMGI temperature from 200 • C to 150 • C. We devise a simplified test to investigate the effect of PMGI peak temperature on SNS JJ room-temperature resistance.This test entails spinning 3 µm of PMGI on two chips with arrays of single junctions.Next, one chip is heated on a hotplate for 5 min to 150 • C while the other is heated to 200 • C. The chips are not directly placed on the hotplate; rather, as is standard practice, a Si wafer (6" diameter) is placed in between.Finally, the resist is stripped off using a bath of NMP at 88 • C followed by two baths of IPA at 80 • C.
For a valid comparison, it is important that initial junction resistances for both chips be similar.Two-point resistance measurements using a manual probe station confirm the overlap of cumulative distribution functions (CDFs) of initial resistance for both chips, as shown in Fig. 4(a).We perform a fit using kernel density estimation 30 to each of these CDFs and compute the derivative of the best fits to estimate the probability distribution functions (PDFs) of resistance.The results, shown in Fig. 5(c), reveal a pre-test concentration around 20 kΩ for both chips.The different temperature excur- sions make the resistance distributions become qualitatively different, as shown by the CDFs in Fig. 4(b) and the PDFs in Fig. 4(d) (similarly obtained).For junctions exposed to 150 • C (200 • C), the distribution of resistances shifts downward (upward).The trajectory of individual junctions can be followed in Fig. 4(e).For 150 • C, the majority of resistances stay close to their initial values.For 200 • C, however, the majority increase.Some junction resistances do decrease in both cases, particularly ones starting at the high end.While we do not understand the reason for this decrease, we speculate that it may arise from the different cleaning procedures used after the initial JJ contacting (see Supplementary Material) and after the simulated AB step.
Finally, we connect the of a transmon as a qubit at cryogenic temperature to the room-temperature resistance of its SNS junction pair.We deem a transmon to be operable if we can simply observe of a power-dependent shift of the frequency of its readout resonator (see Fig. S2 for an example).In total 78 qubits were measured from 8 different devices.These devices fall into three categories: 3 devices without ABs, in which 18 of 25 transmons were operable; 1 device with ABs fabricated by reflow, in which 1 of 9 transmons were operable; and 4 devices with ABs fabricated by GSL, in which 28 of 44 transmons were operable.Figure 5(a) shows numerical CDFs of the junction pair resistance for transmons that exhibit resonator power shifts (green) and for transmons that do not (red).These data clearly show that the resistance corresponding to an operable transmon is generally lower than that of a non-operable one.Fits to these numerical CDFs are done using kernel density estimation 30 .The derivative of each best fit gives a probability density function (PDF) [Fig.5(b)].Using a Bayesian update, we extract the posterior probability of a transmon being operable given its room-temperature resistance.The probability [Fig.5(c)] starts off close to unity and decreases to 0.5 by ∼ 18 kΩ.The probability reduces to near zero by ∼ 25 kΩ.We conclude that for a good SNS Josephson junction it is vital that the room-temperature resistance be as low as possible, cementing the benefits of GSL-based AB fabrication.
In summary, we have employed grayscale lithography to reduce the peak temperature for airbridge processing compared to the traditional reflow method.We have shown that lowering peak processing temperature from 200 • C (needed for PMGI reflow) to 150 • C (limited by PMGI adhesion) increases the yield of operable SNS transmons based on InAs-nanowire Josephson junctions.We have done this in two steps.First we showed that GSL-based fabrication produces lower roomtemperature JJ resistances.Secondly, we showed that lower JJ resistance increases the probability of having an operable SNS transmon at cryogenic temperature.For future work, it remains important to correlate the AB fabrication process with SNS transmon coherence time.It is also worthwhile to explore other e-beam resists that bake at lower temperatures without suffering adhesion problems as well as optical GSL using a direct laser writer, which could possibly lower baking even to room temperature.

FIG. 1 .
FIG. 1. Overview of airbridge fabrication by the GSL method, using (left) schematics and (right) optical images.(a,b) Pre-fabrication of the base layer.Our CPW transmission lines have 12 µm center conductor width and 4 µm gaps between the central conductor and the flanking ground planes.(c,d) Patterning of the PMGI (blue) bottom resist layer using GSL.(e,f) Patterning of the PMMA top resist bilayer (orange) defining the lateral dimensions of airbridges.(g, h) Sputtering of NbTiN (gold) and liftoff.

FIG. 2 .
FIG. 2. Images at various length scales of a circuit QED test device with 100% yield of 185 airbridges fabricated by the GSL method.(a) Optical image of the full device (7 mm × 2.3 mm), with added falsecolor.The device has 12 flux-tuneable SNS transmons (red) with dedicated readout resonators (purple) coupled to a common readout feedline (blue).Six of the SNS transmons have dedicated fluxcontrol lines (yellow).(b,e) Scanning electron micrographs (SEM) showing (b) one SNS transmon and its dedicated readout resonator; (c) the SNS junction pair and its connection to the transmon capacitor pads; (e) zoom-in on the SNS junction pair and SQUID loop; and (d) an example airbridge.

FIG. 3 .
FIG. 3. Calibration of grayscale e-beam lithography.(a) CDF of the energy of the e-beam in PMGI on top of NbTiN.Note that more than 30% of the energy is deposited beyond a 20 µm radius.(b) Calibration of PMGI height as a function of local e-beam dose (red) and fit (blue) used for interpolation by the software.(c) Two-dimensional image of the targeted resist height for the airbridge.(d) Image of the dose map required to achieve the height map in (d) with precompensation for proximity effect and resist nonlinearity.(e) Vertical line cut (red) of actual PMGI resist height as measured with a profilometer and best fit to a circle function (blue).

FIG. 4 .
FIG. 4. Temperature tests of two arrays of single SNS junctions that are exposed to either 150 • C (blue) and 200 • C (red) for 5 min in PMGI.The tests simulate the temperature excursions of the GSL method and the traditional reflow method, respectively.(a,b) CDFs of junction resistance (a) prior to and (b) following the temperature test.(c,d) PDFs derived from the CDFs (c) prior to and (d) following the temperature test.A clear shift toward higher resistances is observed for the 200 • C test.(e) Comparison of each junction resistance before and after the test.Note the relatively similar initial distributions of resistance and the different final distributions.

FIG. 5 .
FIG. 5. Study of the room-temperature resistance of the junction pairs in operable and non-operable SNS transmons.(a) Cumulative distribution function of the resistance for operable (green) and nonoperable (red) transmons.Here, operable is conditioned on the observation of a power-dependent frequency shift in the dedicated readout resonator (see Fig. S2 for an example).(b) PDF derived from (a).(c) Posterior probability [calculated from (b)] of having an operable transmon as a function of its room-temperature JJ resistance.
FIG. S2.Example shift of the resonance frequency of a dedicated readout resonator with increasing incident power on the feedline, indicating that the coupled SNS transmon is operable.(a) Image plot of normalized feedline transmission as a function of probe frequency and incident power.The resonance shifts from 6.0538 GHz at −110 dBm to 6.0560 GHz at −70 dBm.This positive shift indicates that the qubit transition frequency is above the resonator frequency.(b) Linecuts of feedline transmission versus frequency at −110 dBm (cyan) and −70 dBm (orange).